DETAILED ACTION
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: line B-B’. See FIG. 3. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "S12" and "S32" have both been used to designate “second side portion”. See paragraph [0040] and [0027]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 6, 9 thru 12, 14, 16, and 18 thru 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okada et al. US 2022/0059493 A1. Okada discloses (see, for example, FIG. 1) a semiconductor package 1, comprising: a package substrate 11 including a plurality of substrate pads 15/14 spaced apart from each other in a first direction and an upper insulation layer (i.e. bottom portion) SR1 on an upper surface of the package substrate 11, the upper insulation layer SR1 defining a recess that exposes the plurality of substrate pads 15/14; a dam structure (i.e. top portion) SR1 extending on the upper insulation layer SR1 to surround the recess; a plurality of semiconductor chips 50 stacked on the upper insulation layer SR1, the plurality of semiconductor chips 50 each including a first surface facing upwards and each chip pad 51 of a plurality of chip pads 51 on a respective first surface, the plurality of semiconductor chips 50 being spaced apart from the dam structure SR1 in a second direction perpendicular to the first direction; a plurality of bonding wires 70 connecting the plurality of substrate pads 15/14 to the plurality of chip pads 51 of the plurality of semiconductor chips 50; and an underfill member 80 filling an interior of the recess to cover an end portion of each of the plurality of bonding wires and each of the plurality of substrate pads. In FIG. 2, Okada discloses the dam structure SR1 surrounding the recess by extending around the edge of the recess. The upper part of the structure SR1 is being defined as the dam structure and the lower part of the structure SR1 is being defined as the upper insulation layer in the same manner as shown in applicant’s FIG. 1, which shows the upper insulation layer 110a and the dam structure 130 being the same integral structure, and also disclosed in applicant’s claim 9 (“the insulation material and the upper insulating layer include a same material.”), and paragraph [0064] of the applicant’s specification.
Regarding claims 2, and 12, see, for example, FIG. 1 wherein Okada discloses the dam
structure SR1 having a first height from the upper surface of the package substrate 11.
Regarding claims 4, and 14, see, for example, FIG. 1 wherein Okada discloses dam structure SR1 having a first width from an inner wall of the recess.
Regarding claims 6, and 16, see, for example, FIG. 1 wherein Okada discloses the plurality of semiconductor chips 50 being sequentially attached on the upper surface of the package substrate 11 by a plurality of adhesive films 60.
Regarding claims 9, and 18, see, for example, FIG. 1 wherein Okada discloses the dam structures SR1 includes an insulation material, and the insulating material and the upper insulation layer include a same material.
Regarding claims 10, and 19, see, for example, FIG. 1 wherein Okada discloses the upper insulation layer SR1 exposes a portion of each of a plurality of uppermost wires 13 in the package substrate 11, and wherein each of the plurality of substrate pads 15/14 is on a respective exposed portion of the plurality of uppermost wires 13.
Regarding claim 11, see, for example, FIG. 1 wherein Okada discloses a semiconductor package 1, comprising: a package substrate 11 having a first side portion (i.e. left side) extending in a first direction and a second side portion (i.e. right side) facing with the first side portion, the package substrate 11 having a plurality of substrate pads 15/14 spaced apart from each other along the first side portion and an upper insulation layer (i.e. bottom portion) SR1 defining a recess that exposes the plurality of substrate pads 15/14; a dam structure (i.e. top portion) SR1 extending on the upper insulation layer to surround the recess; a plurality of semiconductor chips 50 stacked on an upper surface of the package substrate 11 such that a first surface on which a plurality of chip pads 51 are formed faces upward, the plurality of semiconductor chips 50 being spaced apart from a side portion of the dam structure SR2 in a second direction perpendicular to the first direction; a plurality of bonding wires 70 connecting the plurality of substrate pads 15/14 to the plurality of chip pads 51 of the plurality of semiconductor chips 50; and an underfill member 80 filling an interior of the recess to cover an end portion of each of the plurality of bonding wires 70 and each of the plurality of substrate pads 15/14. In FIG. 2, Okada discloses the dam structure SR1 surrounding the recess by extending around the edge of the recess. The upper part of the structure SR1 is being defined as the dam structure and the lower part of the structure SR1 is being defined as the upper insulation layer in the same manner as shown in applicant’s FIG. 1, which shows the upper insulation layer 110a and the dam structure 130 being the same integral structure, and also disclosed in applicant’s claim 9 (“the insulation material and the upper insulating layer include a same material.”), and paragraph [0064] of the applicant’s specification.
Regarding claim 20, see, for example, FIG. 1 wherein Okada discloses a semiconductor package 1, comprising: a package substrate 11 having a plurality of uppermost wires 13 and an upper insulation layer (i.e. bottom portion) SR1 on an upper surface of the package substrate 11, the upper insulation layer SR1 defining a recess exposing the plurality of uppermost wires 13, a plurality of substrate pads 15/14 on the plurality of exposed uppermost wires 13, and a dam structure (i.e. top portion) SR1 extending on the upper insulation layer SR1 to surround the recess; a plurality of semiconductor chips 50 stacked on the upper surface of the package substrate 11 by a plurality of adhesive films 60 such that a first surface on which a plurality of chip pads 51 are formed faces upward; a plurality of bonding wires 70 connecting the plurality of substrate pads 15/14 to the plurality of chip pads 51 of the plurality of semiconductor chips 50; and an underfill member 80 filling an interior of the recess to cover an end portion of each of the plurality of bonding wires 70 and each of the plurality of substrate pads 15/14. In FIG. 2, Okada discloses the dam structure SR1 surrounding the recess by extending around the edge of the recess. The upper part of the structure SR1 is being defined as the dam structure and the lower part of the structure SR1 is being defined as the upper insulation layer in the same manner as shown in applicant’s FIG. 1, which shows the upper insulation layer 110a and the dam structure 130 being the same integral structure, and also disclosed in applicant’s claim 9 (“the insulation material and the upper insulating layer include a same material.”), and paragraph [0064] of the applicant’s specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 5, 13, and 15 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Okada et al. US 2022/0059493 A1 as applied to claims 1, 2, 4, 6, 9-12, 14, 16, and 18-20 above. Okada does not clearly disclose the first height being within a range of 5 μm to 10 μm. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first height is within a range of 5 μm to 10 μm in order to protect the outer edge of the substrate pad, and since it has been held that discovering the optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claims 5, and 15, Okada does not disclose the first width being within a range
of 50 μm to 150 μm. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first width is within a range of 50 μm to 150 μm.in order to protect the outer edge of the substrate pad, and since it has been held that discovering the optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 13, see the rejection for claim 5 above.
Claim(s) 7, 8, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okada et al. US 2022/0059493 A1 as applied to claims 1, 2, 4, 6, 9-12, 14, 16, and 18-20 above, and further in view of Haji et al. US 5,909,633. Okada does not disclose each of the plurality of substrate pads has a first conductive layer and a second conductive layer on the first conductive layer. However, Haji discloses (see, for example, FIG. 1, and abstract) a semiconductor package 30 comprising a pad 14 wherein the pad includes a first conductive layer and second conductive layer. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have each of the plurality of substrate pads has a first conductive layer and a second conductive layer on the first conductive layer in order to improve bonding performance that includes a stable nickel structure with a gold surface that readily accepts wire bonds.
Regarding claim 17, see the rejection for claim 7 above.
Regarding claims 8, and 19, see, for example, FIG. 2 wherein Haji discloses a nickel layer 22 and gold layer 23.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
July 29, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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