Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1- are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. No. 6525921 to Nakatani et al. (Nakatani).
Regarding Claim 1, Nakatani teaches in Figs. 4A-B at least, a capacitor embeddable in a substrate core of a semiconductor device, the capacitor comprising:
a conductive substrate 111 having a front side and a back side;
a dielectric layer 112 on the front side of the conductive substrate;
a conductive polymer layer 113a on the dielectric layer;
a carbonaceous layer on the conductive polymer layer 8:15-29;
a front metallization layer 113b on the carbonaceous layer and electrically connected to the conductive polymer layer; and
a back metallization layer 101 on the back side of the conductive substrate and electrically connected to the conductive substrate.
Regarding Claim 2, Nakatani teaches the capacitor of claim 1, wherein the conductive polymer layer, the carbonaceous layer, and the front metallization layer define a plurality of electrically isolated stacks on the front side of the conductive substrate (each separated by insulator 401).
Regarding Claim 3, Nakatani teaches the capacitor of claim 1, wherein the dielectric layer is conformal with a high surface area (HSA) portion of the conductive substrate on the front side of the conductive substrate (see Fig. 1C, the textured surface and interface is considered the high surface area).
Regarding Claim 4, Nakatani teaches the capacitor of claim 1, wherein the back metallization layer is on a solid metal portion of the conductive substrate on the back side of the conductive substrate (see Fig. 4B).
Regarding Claim 5, Nakatani teaches in Figs. 4A-B and 6A-E at least, a substrate of a semiconductor device, the substrate comprising:
a substrate core 604/608; and
a capacitor embedded in the substrate core, the capacitor including a conductive substrate having a front side and a back side, a dielectric layer on the front side of the conductive substrate, a conductive polymer layer on the dielectric layer, a carbonaceous layer on the conductive polymer layer, a front metallization layer on the carbonaceous layer and electrically connected to the conductive polymer layer, and a back metallization layer on the back side of the conductive substrate and electrically connected to the conductive substrate (see above rejection of Claim 1).
Regarding Claim 6, Nakatani teaches the substrate of claim 5, wherein the conductive polymer layer, the carbonaceous layer, and the front metallization layer define a plurality of electrically isolated stacks on the front side of the conductive substrate (separated by 401/604).
Regarding Claim 7, Nakatani teaches the substrate of claim 5, wherein the dielectric layer is conformal with a high surface area (HSA) portion of the conductive substrate on the front side of the conductive substrate (see Fig. 1C, the textured surface and interface is considered the high surface area).
Regarding Claim 8, Nakatani teaches the substrate of claim 5, wherein the back metallization layer is on a solid metal portion of the conductive substrate on the back side of the conductive substrate (see Fig. 4B).
Regarding Claim 9, Nakatani teaches the substrate of claim 5, wherein the substrate is a package substrate of the semiconductor device (see Fig. 6E, 608 may be a package).
Regarding Claim 10, Nakatani teaches the substrate of claim 5, wherein the substrate is an interposer of the semiconductor device (608 may be used as an interposer).
Regarding Claim 21, Nakatani teaches the capacitor of claim 1, wherein the conductive substrate comprises an etched (method of making does not bear weight, see MPEP 2113) aluminum foil 7:46.
Regarding Claim 25, Nakatani teaches the substrate of claim 5, wherein the conductive substrate comprises an etched (method of making does not bear weight, see MPEP 2113) aluminum foil 7:46.
Regarding Claim 29, Nakatani teaches a substrate of a semiconductor device, the substrate comprising:
a substrate core 604/608; and
a capacitor embedded in the substrate core, the capacitor including a conductive substrate having a front side and a back side, a dielectric layer on the front side of the conductive substrate, a conductive polymer layer on the dielectric layer (see above rejection of Claim 1), a first metallization layer 609a electrically connected to the conductive polymer layer, and a second metallization layer 609b electrically connected to the conductive substrate.
Regarding Claim 30, Nakatani teaches the substrate of claim 29, wherein the first and second metallization layers are connected to metal routing layers of the substrate (by through via 605).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 22 and 26 rejected under 35 U.S.C. 103 as being unpatentable over Nakatani in view of U.S. Pat. No. 5568352 to Hwang.
Regarding Claims 22 and 26, Nakatani teaches the capacitor and substrates of claims 1 and 5, but does not explicitly teach that the front metallization layer includes a diffusion barrier layer.
However, in analogous art, Hwang teaches diffusion barrier layers throughout and their importance on electrodes/ contacts. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Hwang to prevent diffusion of impurities into the capacitor.
Claims 23, 24, 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Nakatani.
Regarding Claim 23, 24, 26 and 27, Nakatani teaches the capacitor and substrates of claims 1 and 5, but does not explicitly teach that the capacitor has a thickness of less than 75 um.
However, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A)). Nakatani is silent regarding the thickness of the capacitor and nothing on the record indicates it would operate differently than one having the dimensions claimed.
Conclusion
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/EVREN SEVEN/ Primary Examiner, Art Unit 2812
