Listed by the USPTO as SEVEN, EVREN
Tech Center 2800 • Art Units: 2812 2825
This examiner grants 75% of resolved cases
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18802083 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18820798 | DISPLAY DEVICE | Non-Final OA | Samsung Display Co., Ltd. |
| 18467911 | FIELD EFFECT TRANSISTOR DEVICE | Non-Final OA | HUAWEI TECHNOLOGIES CO., LTD. |
| 18667899 | PACKAGE COMPRISING A PASSIVE DEVICE WITH A FRONT SIDE PROTECTION LAYER | Non-Final OA | QUALCOMM Incorporated |
| 18438419 | STACKED DIE STRUCTURE | Final Rejection | QUALCOMM Incorporated |
| 18425447 | INTEGRATED CIRCUIT (IC) PACKAGE WITH DIE INTERCONNECTS TERMINATING AT MULTIPLE METALLIZATION LAYERS IN A SUBSTRATE TO REDUCE SPACING REQUIREMENTS BETWEEN DIE INTERCONNECTS | Non-Final OA | QUALCOMM Incorporated |
| 18175591 | METAL GATE FABRICATION FOR NANORIBBON-BASED TRANSISTORS | Final Rejection | Intel Corporation |
| 18435091 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE | Final Rejection | Kioxia Corporation |
| 18625366 | NORMALLY-ON GALLIUM NITRIDE BASED TRANSISTOR WITH P-TYPE GATE | Non-Final OA | Texas Instruments Incorporated |
| 18757531 | PACKAGE STRUCTURE | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18674894 | APPARATUS INCLUDING COOLING STRUCTURE | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18766996 | METHOD OF MANUFACTURING AN INTEGRATED FAN-OUT PACKAGE HAVING FAN-OUT REDISTRIBUTION LAYER (RDL) TO ACCOMMODATE ELECTRICAL CONNECTORS | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18379304 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRO-MECHANICS CO., LTD. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy74.7% of resolved applications examined by Evren Seven were allowed (755 resolved cases), compared with 82.1% across Art Unit 2812 over the last five years.
This examiner's interview lift is +8.8 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Evren Seven took 832 days on average from filing to allowance.
Evren Seven examines applications in Art Unit 2812 in Tech Center 2800 (Semiconductors, Circuits & Optics).
