Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wu (US 20210384097 A1).
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CLAIM 1. Wu teaches a semiconductor device comprising:
a first semiconductor element 20 including a first obverse surface that faces in a first direction -Z-direction , and a first electrode 49/31 and a second electrode 49/31 that are located on a side opposite the first obverse surface in the first direction (Fig. 5);
a sealing resin 63 covering the first semiconductor element (Fig. 5); and
a heat dissipating layer 19/11-13 bonded to the first obverse surface,
wherein the heat dissipating layer includes a heat dissipating surface facing a same side as the first obverse surface in the first direction (Fig. 5),
the heat dissipating surface is exposed from the sealing resin to outside(Fig. 5), and
as viewed in the first direction, a peripheral edge of the heat dissipating surface surrounds the first obverse surface(Fig. 5).
CLAIM 2. Wu teaches the semiconductor device according to claim 1, further comprising a solid-phase diffusion bonding layer 19/29 (Fig 8) located between the first obverse surface and the heat dissipating layer (Fig. 5).
CLAIM 3. Wu teaches the semiconductor device according to claim 2, further comprising a first intermediate layer 11/12 located between the first obverse surface and the heat dissipating layer, wherein the solid-phase diffusion bonding layer 19/29 is located between the first obverse surface and the first intermediate layer, and a Vickers hardness of the first intermediate layer is lower than a Vickers hardness of the heat dissipating layer ¶67 (Fig. 5).
CLAIM 4. Wu teaches the semiconductor device according to claim 3, wherein a dimension of the first intermediate layer in the first direction is smaller than a dimension of the heat dissipating layer in the first direction (Fig. 5 & 8).
CLAIM 5. Wu teaches the semiconductor device according to claim 4, further comprising a second intermediate layer located between the first obverse surface and the first intermediate layer, wherein the solid-phase diffusion bonding layer is located between the first obverse surface and the second intermediate layer, a Vickers hardness of the second intermediate layer is lower than the Vickers hardness of the heat dissipating layer, and the Vickers hardness of the second intermediate layer is higher than the Vickers hardness of the first intermediate layer (¶67-68 & 72).
CLAIM 6. Wu teaches the semiconductor device according to claim 2, wherein the heat dissipating layer includes an end surface 13A facing in a direction orthogonal to the first direction, and the end surface is inclined to be farther away from the first obverse surface as viewed in the first direction as a distance from the first obverse surface increases in the first direction (Fig. 5).
CLAIM 7. Wu teaches the semiconductor device according to claim 2, wherein the heat dissipating layer includes an insulating layer 11 (AlN) and a first conductor layer 12/13 adjacent to the insulating layer in the first direction (Fig. 5&8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20210384097 A1).
CLAIM 8. Wu teaches the semiconductor device according to claim 7, however is silent up9on wherein a dimension of the first conductor layer in the first direction is larger than a dimension of the insulating layer in the first direction. Figure 5 of Wu depicts an aluminum nitride ceramic insulating layer 11 that is thicker in the Z-direction than the conductive layer 12/13. To arrive at the claimed structure where the dimension of the conductive layer 12/13 in the Z-direction is larger than the insulating layer 11, it would have been prima facie obvious to a person of ordinary skill in the art to modify the relative thickness ratio through routine optimization. Under MPEP § 2144.05, discovering an optimum value or dimension of a parameter that is already recognized in the background of the art as result-effective, such as tailoring layer thicknesses to modulate thermal conduction from element 20 through the heat-dissipating surface 10B, is achievable through routine experimentation. Furthermore, in accordance with MPEP § 2144.04, re-proportioning, resizing, or altering the dimensional relationship of known structural elements to enhance performance characteristics like heat transfer represents a normal design choice and layout optimization well within the standard skill set of a skilled artisan rather than a patentable distinction.
CLAIM 9. Wu teaches the semiconductor device according to claim 8, wherein the insulating layer includes a peripheral portion 13A that surrounds the heat dissipating surface as viewed in the first direction (Fig. 5).
CLAIM 10. Wu teaches the semiconductor device according to claim 8, wherein the first conductor layer is located on a side opposite the first semiconductor element in the first direction with respect to the insulating layer, and the first conductor layer 12/13includes the heat dissipating surface (Fig. 5).
CLAIM 11. Wu teaches the semiconductor device according to claim 8, wherein the insulating layer 11 is located on a side opposite the first semiconductor element in the first direction with respect to the first conductor layer 12 (Fig. 5).
CLAIM 12. Wu teaches the semiconductor device according to claim 11, wherein the heat dissipating layer includes a second conductor layer 10A located on a side opposite the first conductor layer 12 in the first direction with respect to the insulating layer 11, and the second conductor layer includes the heat dissipating surface (Fig. 5).
CLAIM 13. Wu teaches the semiconductor device according to claim 12, however may be silent upon
wherein a dimension of the second conductor layer in the first direction is larger than the dimension of the insulating layer in the first direction. Figure 5 of Wu depicts an aluminum nitride ceramic insulating layer 11 that is thicker in the Z-direction than the conductive layer 12/13. To arrive at the claimed structure where the dimension of the conductive layer 12/13 in the Z-direction is larger than the insulating layer 11, it would have been prima facie obvious to a person of ordinary skill in the art to modify the relative thickness ratio through routine optimization. Under MPEP § 2144.05, discovering an optimum value or dimension of a parameter that is already recognized in the background of the art as result-effective, such as tailoring layer thicknesses to modulate thermal conduction from element 20 through the heat-dissipating surface 10B, is achievable through routine experimentation. Furthermore, in accordance with MPEP § 2144.04, re-proportioning, resizing, or altering the dimensional relationship of known structural elements to enhance performance characteristics like heat transfer represents a normal design choice and layout optimization well within the standard skill set of a skilled artisan rather than a patentable distinction.
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20210384097 A1) in view of Choi et al. (US 20050104168 A1).
CLAIM 14. Wu teaches the semiconductor device according to claim 1, however is silent upon further comprising: a substrate; and a plurality of wirings disposed on the substrate, wherein the first electrode and the second electrode are electrically bonded to the plurality of wirings.
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MPEP § 2143 regarding implicit features and common knowledge. Choi et al. (Fig. 4B above) illustrates this standard arrangement by disclosing a comparable power semiconductor package featuring electrodes and leads on a first side alongside heat dissipation layers and a heat sink on an opposing side exposed through a molding, confirming that mounting such packages onto a substrate surface during operation was well-established in the art.
Consequently, modifying the device of Wu by mounting it onto a substrate as taught by Choi involves the application of a known technique to a known device ready for improvement to yield predictable results, a line of reasoning fully supported under MPEP § 2143(I)(A) and (D) in view of the principles set forth in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), making the combined arrangement obvious to a person of ordinary skill in the art at the time of the invention.
CLAIM 15. Wu in view of Choi teach the semiconductor device according to claim 14, further comprising a second semiconductor element (Wu Fig. 5 depicts first and second semiconductor elements) including a second obverse surface that faces a same side as the first obverse surface in the first direction and a third electrode and a fourth electrode that are located to face the plurality of wirings (Wu -Fig. 20 – numerous electrodes facing the wiring), wherein the third electrode and the fourth electrode are electrically bonded to the plurality of wirings, the heat dissipating layer is bonded to the second obverse surface (e.g. Wu Figs. 5 & 22), the second semiconductor element is covered with the sealing resin, and as viewed in the first direction, the peripheral edge of the heat dissipating surface surrounds the second obverse surface (e.g. Wu Figs. 5 & 22).
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 20210384097 A1) in view of Choi et al. (US 20050104168 A1) in view of Meiser et al. (US 20170213783 A1).
CLAIM 16. Wu in view of Choi teach the semiconductor device according to claim 15, however is silent upon further comprising an IC that is electrically connected to the plurality of wirings and drives the first semiconductor element and the second semiconductor element, wherein the IC is covered with the sealing resin.
It would have obvious to a person of ordinary skill in the art at the time of the invention to modify the power semiconductor package disclosed in Wu by integrating the integrated circuit driving circuitry taught by Meiser. As evidenced by Meiser, incorporating integrated circuits containing driver control and protection circuits directly into power semiconductor packaging was a well-known option for managing power devices.
A person of ordinary skill in the art possessing ordinary creativity would have found it obvious to apply this known technique to Wu's package, which was already ripe for improvement, with a reasonable expectation of success and in order to achieve the entirely predictable benefits of enhanced device control and operational protection. Such a modification represents the simple application of a known technique to a conventional device ready for improvement, resulting in predictable functional improvements as contemplated under 35 U.S.C. 103 and articulated within the framework of MPEP § 2143 (Rationale A: combining prior art elements according to known methods to yield predictable results).
CLAIM 17. Wu in view of Choi in view of Meiser teach the semiconductor device according to claim 14, further comprising a plurality of terminals electrically connected to the plurality of wirings, wherein the plurality of terminals are located on a side opposite the plurality of wirings in the first direction with respect to the substrate (Wu Fig. 5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/10/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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