DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14 have been considered but are moot in view of the new ground of rejection. No argument with respect to claims 15-20 have been presented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 11, 12, 15, and 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 7,093,171 B2).
Claim 1: Hsu teaches a memory device comprising:
a first memory bank (e.g. Bank 0, Fig. 2A) including first memory cells (e.g. each bank comprises memory cells – col. 1, lines 24-26) connected to a first wordline (e.g. Hsu states, in col. 1, lines 62-66, that when a wordline WL(m) is defective, all wordlines WL(m) across all eight banks… are replaced, which implies that each memory bank is connected to a correspondent wordline – see also claim 1);
a second memory bank (e.g. Bank 1, Fig. 2A) including second memory cells connected to a second wordline corresponding to the first wordline (e.g. Hsu states that when a wordline WL(m) is defective, all wordlines WL(m) across all eight banks… are replaced -This explicitly identifies wordlines of the same index m in different banks as corresponding wordlines, satisfying the limitation of a second memory bank with a “second wordline corresponding to the first wordline.”); and
a repair circuit (e.g. item 300, fig. 3) to selectively operate in a first repair mode and in a second repair mode based on positions of failed memory cells included in the first memory cells and the second memory cells (e.g. Hsu’s row redundancy circuit (300) selects a repair field size (RFS) during/prior to testing based on detected faulty wordline positions (col. 6, ll. 8–15). Different RFS values (1M, ½M, ¼M) correspond to different repair modes);
Wherein in the first repair mode, repair circuit is configured to repair the first wordline and the second wordline together (e.g. When RFS = 1M, a single redundant wordline (RWL) replaces the same defective wordline address across all eight banks in the repair field, i.e., the first and second wordlines are repaired together (col. 2, ll. 20–26; Fig. 2B).
Hsu fails to teach that in the second repair mode, repair circuit is configured to repair the first wordline or the second wordline individually. However, a POSITA, before the effective fling date of the claimed invention, would have found it obvious to extend Hsu’s selectable repair field sizes to a single-bank field size. Hsu explicitly teaches that (1) decreasing the repair field size increases repairability (col. 6, ll. 1–4), (2) the row fuse array stores per-bank fuse information (col. 5, ll. 47–52), and (3) copy logic can replicate faulty addresses to a variable number of banks (col. 9, ll. 55–67). Reducing the field size from 2 banks to 1 bank is a simple, predictable variation that yields the expected benefit of individual wordline repair.
As per claim 11, Hsu teaches:
First memory bank with first wordline group (Hsu teaches memory array 301 having banks (Bank0–Bank127), each bank having a plurality of wordlines WL(0–1023) (col. 3, ll. 48–52; Fig. 2B));
Second memory bank with second wordline group corresponding to the first wordline group (e.g.,Hsu teaches that wordlines across banks share the same row address (RA). For example, WL(m) in Bank0 corresponds to WL(m) in Bank1 (col. 2, ll. 20–26);
Row decoder configured to select wordlines based on an address from an external device (e.g., Hsu teaches decoding an incoming row address (RA) to select a wordline in the memory array. When no repair match occurs, the RA is decoded for accessing the desired row (col. 5, ll. 58–60; step 414 in Fig. 4));
Repair circuit configured to provide a spare wordline driving signal based on bank repair mode information (e.g., Hsu’s row redundancy circuit (300) generates a redundant row address (RRA) and control signal XADD (spare wordline driving signal) when a match is found between the incoming RA and stored faulty addresses (col. 5, ll. 53–57). The repair field size (repair mode) is selected based on test results and stored as configuration information (col. 6, ll. 8–15));
wherein in first repair mode, first and second wordline groups are repaired together (e.g., When Hsu selects a larger repair field size (e.g., 1M, 8 banks), a single redundant wordline replaces the defective wordline across all banks in that repair field, so the first and second wordline groups are repaired together (col. 2, ll. 20–26; Fig. 2B)).
Claim 12: Hsu teaches the memory device of claim 11, wherein the repair circuit comprises: a mode information register configured to store bank repair mode information according to the positions of the failed memory cells (e.g. Hsu teaches a “programmable register” (510, Fig. 5B) that is programmed with the selected repair field size -see Col. 7, lines 26-38. This register stores the “bank repair mode information” (e.g., 1M, ½M, ¼M RFS) which dictates whether wordlines are repaired together or individually); a mode selection circuit configured to generate a fuse selection signal and a repair mode signal based on an address received from an external device and the bank repair mode information (e.g. Hsu teaches a “copy logic module” (506, Fig. 5B) which acts as a mode selection circuit. This module generates control signals (e.g., determining how many copies of a faulty address to make) based on an incoming bank address (BA) and the bank repair mode information stored in the programmable register – see Col. 6, L. 58-67; Col. 7, lines 25-30). The output of this logic, which controls the repair scope, can be fairly characterized as a “fuse selection signal” and a “repair mode signal.” ); and a repair control circuit (e.g. item 306) configured to generate a spare wordline driving signal based on the fuse selection signal and the repair mode signal (e.g. The RRCB generates RRA (redundant row address) and XADD (repair control) to drive a redundant wordline- col. 6, lines 8-17).
Hsu fails to teach that in second repair mode, first wordline group or second wordline group are repaired individually. However, one of ordinary skill in the art would have found it obvious to extend Hsu’s selectable repair field sizes to a single-bank repair field (individual repair mode) for the following reasons: – Hsu’s row fuse array (302) stores per-bank fuse information (col. 5, ll. 47–52). The copy logic (506) replicates faulty addresses to a variable number of banks based on the selected repair field size (col. 9, ll. 55–67). One of ordinary skill would recognize that setting the copy count to “1” (i.e., copying faulty address to only one bank) is a simple and predictable programming change.
Claim 15: Hsu teaches a repair method of a memory device comprising: comparing an address received from an external device and bank repair mode information for determining a repair mode for each of a plurality of memory banks included in the memory device (e.g. Hsu's row redundancy comparator block (RRCB 306) compares a received row address (RA) with row fuse information (RFI) that contains the bank repair mode information (the programmed RFS and faulty addresses) (Hsu, Col. 5, L. 53-58; Fig. 4, step 408)); determining a repair mode of a first memory bank, from among the plurality of memory banks, corresponding to the address based on the comparison result (e.g. The outcome of the comparison in the RRCB, in the context of the pre-programmed RFS, determines whether a repair operation is triggered and, inherently, whether the repair will be for a large field ("together") or a small field ("individually"); repairing, in a first repair operation, a failed wordline included in the first memory bank and a wordline corresponding to the failed wordline in a second memory bank, from among the plurality of memory banks, together when the repair mode is determined to be a first repair mode; and individually repairing, in a second repair operation, the failed wordline included in the first memory bank and a failed wordline included in the second memory bank when the repair mode is determined to be a second repair mode (e.g. The "repairing together" and "repairing individually" steps are the functional results of operating Hsu's system with the selected RFS, as detailed in the rejection of claim 1).
Claim 17: Hsu teaches the method of claim 15, wherein the bank repair mode information is configured to be set to indicate the second repair mode when failed memory cells are concentrated in one of the first memory bank or the second memory bank (e.g. Hsu teaches that a smaller RFS (repair individually) is used to increase repairability when there are more localized failures (Col. 5, L. 43-45). This directly teaches setting the mode to the second repair mode when failures are concentrated.
Claim 18: Hsu teaches the method of claim 15, wherein the determining the repair mode is configured to include generating a fuse selection signal and a repair mode signal based on the address and the bank repair mode information (e.g. The "mode selection circuit" (i.e., the copy logic module 506 and associated decoding logic) generates signals (the control to copy a faulty address N times) based on the bank address (BA) and the bank repair mode information (the programmed RFS) (Hsu, Col. 6, L. 58-67; col. 7, lines 62-67).
Claim 19: Hsu teaches the method of claim 18, wherein, in the first repair operation, the fuse selection signal is configured to be set so that redundancy enable information is equally transmitted to a first repair wordline selection circuit corresponding to the first memory bank and a second repair wordline selection circuit corresponding to the second memory bank (e.g. Hsu states, in col. 1, lines 62-66, that when a defective wordline WL(m) is detected, all banks in the repair field receive and use the same row-repair information: “When a wordline WL(m) is found to be defective… all the wordlines WL(m) across all eight banks… are replaced by one redundancy wordline.” This means the redundancy-enable information (the RFI bits corresponding to the failed WL) is sent equally to all banks in the group. Also, Hsu describes that the copy logic module copies the failure-bit addresses (FABs) into multiple banks depending on the selected repair field size: “The copy logic module 506 is programmed to copy the FABs… a predetermined number of times in accordance with the repair field size.”
When the repair field is 1M (8 banks), RFI is copied to all 8 banks → exactly the “equal transmission” – see col. 6, lines 63-67 & col. 7, lines 1-4), and wherein the repair mode signal is configured to be set as a first repair mode signal (e.g. Hsu teaches, in col. 6, lines 23-29, repair-mode selection using the chosen repair field size: Different repair field sizes may be selected for different memory banks… the row fuse array may accommodate different repair field sizes. The repair field size dictates the mode: 1M = repair together mode (first mode); ½M, ¼M, 1/8M = individual modes (second mode) - col. 5, lines 28-30; col. 7, lines 1-12).
Claim 20: Hsu teaches the method of claim 18, wherein, in the second repair operation, the fuse selection signal is configured to be set so that a portion of redundancy enable information is transmitted to the first repair wordline selection circuit corresponding to the first memory bank, and another portion of the redundancy enable information is transmitted to the second repair wordline selection circuit corresponding to the second memory bank (e.g. Hsu states, in col. 5, lines 24-27, that during power-on, each set of RFI… is copied into the storage cells corresponding to the banks included in the repair field. For instance, for ¼M repair field: RFI copied into only two banks; this means only a portion of the fuse information (RFI) is sent to specific banks—not all. Aslo, Hsu states, in col. 5, lines 28-30, that the repair field size may also be 1/8M, which means that only one bank receives the repair enable information and other banks receive different (or no) RFI ), and wherein the repair mode signal is configured to be set as a second repair mode signal (e.g. Hsu’s “repair field size” functions as the repair mode signal: Large field size = repair together → first mode; Small field size (¼M, 1/8M, etc.) = repair individually → second mode).
As per claim 21, Hsu teaches:
Repair circuit determines repair mode at run time in response to an address selecting a wordline (e.g. Hsu’s row redundancy circuit operates during normal memory access (run time). When an incoming address (RA and BA) is received, the circuit compares the RA with stored faulty addresses to determine whether a repair is needed (col. 5, ll. 47–60; Fig. 4, steps 402–410);
Determination based on comparing bank repair mode information, generated from positions of failed memory cells, with the address. For instance, Hsu’s “bank repair mode information” corresponds to the stored row fuse information (RFI) that includes addresses of faulty wordlines detected during testing (col. 4, ll. 40–47). The comparison is performed by the row redundancy comparator block (RRCB 306) (col. 5, ll. 53–57). The repair field size (i.e., whether to repair one bank or multiple together) is predetermined, but the runtime decision of whether to activate a spare wordline is indeed based on comparing the incoming address with the stored faulty addresses.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 7,093,171 B2) as applied to claim 11 above, and further in view of Lee (US 6,704,226 B2).
Claim 13: Hsu the memory device of claim 11, but fails the repair circuit comprises: repair fuses including redundancy enable information; a first repair wordline selection circuit configured to generate a first bank spare wordline driving signal corresponding to the first wordline group based on the redundancy enable information; a second repair wordline selection circuit configured to generate a second bank spare wordline driving signal corresponding to the second wordline group based on the redundancy enable information; first latches configured to transmit the redundancy enable information to the first repair wordline selection circuit based on first fuse selection signals; and second latches configured to transmit the redundancy enable information to the second repair wordline selection circuit based on second fuse selection signals. However, Lee's row repair fuse boxes (RF00-RF73, 100, Fig. 4) contain fuses (F0-F23) that are programmed with redundancy enable information based on defective addresses (Lee, col. 4, L. 50-67 & col. 5, lines 13). Furthermore, Lee's "subwordline drivers" (510s, Fig. 3B, 8) are repair wordline selection circuits that generate subwordline drive signals (PXb<ij>) for specific wordlines. A skilled artisan would recognize that multiple such drivers are used for different banks, corresponding to the first and second circuits. Finally, Lee's fuse box (Fig. 4) includes a latch circuit formed by PMOS transistor P1 and inverter I10 to hold the state of the fuse decoding signal NRDb<i>. This latch transmits redundancy enable information (the state of the common node CN) based on the fuse decoding signals, which are generated in response to address inputs. The fuse selection signals claimed are generated by the mode selection circuit of Hsu in combination with the address decoding logic inherent in Lee's fuse boxes.
Therefore, a POSITA, before the effective filing date of the claimed invention, seeking to improve Hsu’s programmable system, would have found it obvious to adapt the well-known, flexible repair circuitry from Lee, in order to control latches and selection circuits.
Claim(s) 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu as applied to claim 1 above.
Claim 14: Hsu teaches the memory device of claim 11, but fails to teach a third memory bank including a third wordline group; and a fourth memory bank including a fourth wordline group corresponding to the third wordline group, wherein the first memory bank and the second memory bank are configured to be set to a first repair mode to repair the first wordline group and the second wordline group together, and wherein the third memory bank and the fourth memory bank are configured to be set to a second repair mode to individually repair the third wordline group or the fourth wordline group. However, Hsu expressly teaches that different repair field sizes (i.e., different repair modes) can be selected for different regions of the memory array (Hsu, col. 6, lines 23-27: "the redundancy allocation algorithm may define different repair field sizes for different memory arrays 301 within a memory system, or for different memory banks within a memory array"). Therefore, it would have been obvious to a skilled artisan, before the effective filing date of the claimed invention, seeking to optimize yield, to apply this teaching to set a first repair mode (e.g., RFS=1/2M for "repair together") for a first pair of banks (e.g., Banks 0-1) and a second repair mode (e.g., RFS=1/4M for "repair individually") for a second pair of banks (e.g., Banks 2-3), as claimed.
Claim 16: Hsu teach the method of claim 15, but fails to teach that the bank repair mode information is configured to be set to indicate the first repair mode when failed memory cells are distributed in the first memory bank and the second memory bank. However, Hsu teaches that the repair field size (and thus the repair mode) is selected "in accordance with results of the testing" (Col. 4, L. 13-15). Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have understood that a larger RFS (repair together) is advantageous when failures are distributed across many banks, as it conserves redundant resources.
Allowable Subject Matter
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 4/4/2026