DETAILED ACTION
This action is responsive to the following communications: the Application filed on August 15, 2024, the Foreign Priority papers retrieved on August 18, 2023 and February 16, 2024 and the Information Disclosure Statements filed on August 15, 2024 and February 6, 2025.
Claims 1-20 are pending. Claims 1, 15 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDSs) filed on August 15, 2024 and February 6, 2025. These IDSs have been considered.
Drawings
The drawings are objected to because all of the Figures filed on August 15, 2024 are degraded, showing dotted lines and dotted lettering and numbering, which may indicate applicant submitted Figures that were in greyscale. Applicant is reminded that solid lines used in the Drawings must be uniformly thick, black, and solid and the words and labels in the Drawings must be plain and legible. MPEP 608.02(f)(V).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 13-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Buyn et al. (US 20160027492) in view of Ware et al. (US 20220165326).
Regarding independent claim 1, Buyn et al. disclose a memory device [see Fig. 4: 400] comprising:
at least one bank comprising a first sub-bank and a second sub-bank disposed in a wordline direction [see Fig. 4, the first bank 410 may be divided into a first sub-bank 411 and a second sub-bank 412. The first sub-bank 411 and the second sub-bank 412 may be arranged in a direction, for example, a row direction, in which the plurality of word lines WLs of the plurality of memory cells MCs are arranged, para. 107],
wherein the first sub-bank is connected to a plurality of first wordlines [each of the plurality of banks 410-480 may include a plurality of word lines WLs, a plurality of bit-lines BLs, and a plurality of memory cells MCs disposed near intersections between the word lines WLs and the bit-lines BLs, as shown in FIG. 5. The plurality of word lines WLs to which the plurality of memory cells MCs are connected may be defined as rows of the plurality of banks 410-480, para. 30],
wherein the second sub-bank is connected to a plurality of second wordlines [each of the plurality of banks 410-480 may include a plurality of word lines WLs, a plurality of bit-lines BLs, and a plurality of memory cells MCs disposed near intersections between the word lines WLs and the bit-lines BLs, as shown in FIG. 5. The plurality of word lines WLs to which the plurality of memory cells MCs are connected may be defined as rows of the plurality of banks 410-480, para. 30].
However, Buyn et al. are silent with respect to wherein the first sub-bank is configured to store normal data, the second sub-bank is configured to store metadata corresponding to the normal data and
wherein metadata for normal data corresponding to each of the plurality of first wordlines is configured to be stored in each of the plurality of second wordlines that correspond to the plurality of first wordlines, respectively.
Ware et al. teach a DRAM has at least one data row and at least one tag row different from and associated with the at least one data row [see Abstract]. The tag includes flag bits like dirty, valid, parity which are attributes of the cached data line [para. 90]. Moreover, Ware et al. also disclose in Figure 2C there could be multiple regular wordlines, for cached data, and a single tag wordline, for tag data in a given mat 210 [para. 62]. Tags in the lower half of a segment (or bank 202) are assigned to data in the upper half of the segment (or bank 202). Tags in the upper half of the segment (or bank 202) are assigned to data in the lower half of the segment (or bank 202) [see Fig. 2B, para. 61].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Ware et al. to the teaching of Buyn et al. such that modifying Buyn et al.’s memory device to store Ware et al.’s tag data into Buyn et al.’s second sub-bank while storing Ware et al.’s cached data into Buyn et al.’s first sub-bank, thereby enabling coordinated access to data and its metadata.
Regarding claim 2, Buyn et al. in combination with Ware et al. teach the limitation with respect to claim 1.
Furthermore, Ware et al. disclose wherein based on a write or read operation being performed on normal data in the first sub-bank, a write or read is performed on metadata corresponding to the normal data in the second sub-bank [see Fig. 4B, after reading cached data from one of the banks of the multiway set associative cache DRAM, 256 bits of tag data are read out in parallel from the bank, using selected address bits for mat (and tag row) selection and column decode 306. Similar activity occurs across 32 banks of DRAM, resulting in the reading, in parallel, of the 4 kB block of cached data, para. 97].
Regarding claim 13, Buyn et al. in combination with Ware et al. teach the limitation with respect to claim 1.
Furthermore, Buyn et al. wherein the at least one bank [Fig. 4: 410] is connected to a plurality of global input/output (GIO) lines [Fig. 4: I/O1, I/O2], and
wherein the first and second sub-banks are connected to different GIO lines [see Fig. 4, The first sub-bank 411 and the second sub-bank 412 are respectively connected to first and second data input/output lines I/O1 and I/O2 which are independent from each other, para. 109].
Regarding claim 14, Buyn et al. in combination with Ware et al. teach the limitation with respect to claim 2.
Furthermore, Buyn et al. disclose at least one bank comprising a first sub-bank and a second sub-bank disposed in a wordline direction [see Fig. 4, the first bank 410 may be divided into a first sub-bank 411 and a second sub-bank 412. The first sub-bank 411 and the second sub-bank 412 may be arranged in a direction, for example, a row direction, in which the plurality of word lines WLs of the plurality of memory cells MCs are arranged, para. 107],
wherein the first sub-bank is connected to a plurality of first wordlines [each of the plurality of banks 410-480 may include a plurality of word lines WLs, a plurality of bit-lines BLs, and a plurality of memory cells MCs disposed near intersections between the word lines WLs and the bit-lines BLs, as shown in FIG. 5. The plurality of word lines WLs to which the plurality of memory cells MCs are connected may be defined as rows of the plurality of banks 410-480, para. 30],
wherein the second sub-bank is connected to a plurality of second wordlines [each of the plurality of banks 410-480 may include a plurality of word lines WLs, a plurality of bit-lines BLs, and a plurality of memory cells MCs disposed near intersections between the word lines WLs and the bit-lines BLs, as shown in FIG. 5. The plurality of word lines WLs to which the plurality of memory cells MCs are connected may be defined as rows of the plurality of banks 410-480, para. 30].
However, Buyn et al. are silent with respect to wherein the first sub-bank is configured to store normal data, the second sub-bank is configured to store metadata corresponding to the normal data and
wherein metadata for normal data corresponding to each of the plurality of first wordlines is configured to be stored in each of the plurality of second wordlines that correspond to the plurality of first wordlines, respectively.
Ware et al. teach a DRAM has at least one data row and at least one tag row different from and associated with the at least one data row [see Abstract]. The tag includes flag bits like dirty, valid, parity which are attributes of the cached data line [para. 90]. Moreover, Ware et al. also disclose in Figure 2C there could be multiple regular wordlines, for cached data, and a single tag wordline, for tag data in a given mat 210 [para. 62]. Tags in the lower half of a segment (or bank 202) are assigned to data in the upper half of the segment (or bank 202). Tags in the upper half of the segment (or bank 202) are assigned to data in the lower half of the segment (or bank 202) [see Fig. 2B, para. 61].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Ware et al. to the teaching of Buyn et al. such that modifying Buyn et al.’s memory device to store Ware et al.’s tag data into Buyn et al.’s first sub-bank while storing Ware et al.’s cached data into Buyn et al.’s second sub-bank, thereby enabling coordinated access to data and its metadata.
Regarding independent claim 15, Buyn et al. disclose a memory device [see Fig. 4: 400] comprising:
at least one bank comprising at least a first sub-bank and a second sub-bank disposed in a wordline direction [see Fig. 4, the first bank 410 may be divided into a first sub-bank 411 and a second sub-bank 412. The first sub-bank 411 and the second sub-bank 412 may be arranged in a direction, for example, a row direction, in which the plurality of word lines WLs of the plurality of memory cells MCs are arranged, para. 107];
a first row decoder [Fig. 4: 413] connected to the first sub-bank [Fig. 4: 411] through a plurality of first wordlines [see Fig. 4, the first sub-bank 111 may be connected to the first row decoder 413, para. 107. See Fig. 12, the row decoder 260a may select one or more word lines of a plurality of word lines WL0-WLm in response to a row address RA[12:0]; and
a second row decoder [Fig. 4: 414] connected to the second sub-bank [Fig. 4: 412] through a plurality of second wordlines [see Fig. 4, the second sub-bank 412 may be connected to the second row decoder 414, para. 107. See Fig. 12, the row decoder 260a may select one or more word lines of a plurality of word lines WL0-WLm in response to a row address RA[12:0],
However, Buyn et al. are silent with respect to wherein based on the first row decoder selecting a single first wordline from among the first wordlines to write normal data in the first sub-bank, the second row decoder is configured to select a single second wordline, corresponding to the single first wordline, from among the second wordlines to write metadata corresponding to the normal data.
Ware et al. teach a DRAM has at least one data row and at least one tag row different from and associated with the at least one data row [see Abstract]. The tag includes flag bits like dirty, valid, parity which are attributes of the cached data line [para. 90]. Moreover, Ware et al. also disclose in Figure 2C there could be multiple regular wordlines, for cached data, and a single tag wordline, for tag data in a given mat 210 [para. 62]. Tags in the lower half of a segment (or bank 202) are assigned to data in the upper half of the segment (or bank 202). Tags in the upper half of the segment (or bank 202) are assigned to data in the lower half of the segment (or bank 202) [see Fig. 2B, para. 61].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Ware et al. to the teaching of Buyn et al. such that modifying Buyn et al.’s memory device to write Ware et al.’s tag data into Buyn et al.’s first sub-bank using the first row decoder while writing Ware et al.’s cached data into Buyn et al.’s second sub-bank using the second row decoder, thereby enabling coordinated access to data and its metadata.
Regarding claim 16, Buyn et al. in combination with Ware et al. teach the limitation with respect to claim 15.
Furthermore, Buyn et al. further comprising:
a first column decoder [Fig. 4: 415] connected to the first sub-bank [Fig. 4: 411] through a plurality of first column select lines [see Fig. 4, the first sub-bank 411 is connected to the first column decoder 415 that receives the column addresses, para. 106]; and
a second column decoder [Fig. 4: 416] connected to the second sub-bank [Fig. 4: 412] through a plurality of second column select lines [see Fig. 4, the second sub-bank 412 is connected to the second column decoder 416 that receives the column addresses, para. 106].
Regarding independent claim 20, Buyn et al. discloses a memory device system [see Fig. 30] comprising:
a memory device [Fig. 30: 730] comprising at least one bank comprising a first sub-bank and a second sub-bank disposed in a wordline direction [see Fig. 4, the first bank 410 may be divided into a first sub-bank 411 and a second sub-bank 412. The first sub-bank 411 and the second sub-bank 412 may be arranged in a direction, for example, a row direction, in which the plurality of word lines WLs of the plurality of memory cells MCs are arranged, para. 107]; and
a memory controller [Fig. 30: 720] configured to control the memory device [Fig. 30: 730, para. 209],
wherein the first sub-bank is connected to a plurality of first wordlines [each of the plurality of banks 410-480 may include a plurality of word lines WLs, a plurality of bit-lines BLs, and a plurality of memory cells MCs disposed near intersections between the word lines WLs and the bit-lines BLs, as shown in FIG. 5. The plurality of word lines WLs to which the plurality of memory cells MCs are connected may be defined as rows of the plurality of banks 410-480, para. 30],
wherein the second sub-bank is connected to a plurality of second wordlines [each of the plurality of banks 410-480 may include a plurality of word lines WLs, a plurality of bit-lines BLs, and a plurality of memory cells MCs disposed near intersections between the word lines WLs and the bit-lines BLs, as shown in FIG. 5. The plurality of word lines WLs to which the plurality of memory cells MCs are connected may be defined as rows of the plurality of banks 410-480, para. 30].
However, Buyn et al. are silent with respect to wherein the first sub-bank is configured to store normal data, the second sub-bank is configured to store metadata corresponding to the normal data and
wherein metadata for normal data corresponding to each of the plurality of first wordlines is configured to be stored in each of the plurality of second wordlines that correspond to the plurality of first wordlines, respectively.
Ware et al. teach a DRAM has at least one data row and at least one tag row different from and associated with the at least one data row [see Abstract]. The tag includes flag bits like dirty, valid, parity which are attributes of the cached data line [para. 90]. Moreover, Ware et al. also disclose in Figure 2C there could be multiple regular wordlines, for cached data, and a single tag wordline, for tag data in a given mat 210 [para. 62]. Tags in the lower half of a segment (or bank 202) are assigned to data in the upper half of the segment (or bank 202). Tags in the upper half of the segment (or bank 202) are assigned to data in the lower half of the segment (or bank 202) [see Fig. 2B, para. 61].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Ware et al. to the teaching of Buyn et al. such that modifying Buyn et al.’s memory device to store Ware et al.’s tag data into Buyn et al.’s second sub-bank while storing Ware et al.’s cached data into Buyn et al.’s first sub-bank, thereby enabling coordinated access to data and its metadata.
Allowable Subject Matter
Claims 3-12 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, there is no teaching or suggestion in the prior art of record to provide the recited wherein each of the first and second sub-banks is connected to p column select lines, p being a positive integer greater than or equal to 2, wherein a first portion of the p column select lines are assigned to a region, in which the normal data of the first sub-bank is stored, as normal column select lines, and wherein a second portion of the p column select lines are assigned to a region, in which the metadata of the second sub-bank is stored, as meta column select lines.
With respect to claim 17, there is no teaching or suggestion in the prior art of record to provide the recited wherein a portion of the first column select lines are configured to be assigned to a region, in which the normal data is stored, as normal column select lines, and wherein a portion of the second column select lines are configured to be assigned to a region, in which the metadata is stored, as meta column select lines.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825