DETAILED ACTION
Priority Claim
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities: inconsistent reference numeral/naming/lack of clarity.
In the specification, for example ¶ [0030], metal layers are given the reference numeral ‘106’ and ‘116’. Further in the specification, for example ¶ [0072], the same reference numerals (106, 116) is given to structured metal layers. ¶ [0058] defines the “structured metal layer” as “the pattern of electrically conductive portions and electrically insulating portions may be formed as a structured metal layer” and ¶ [0041] defines “coded information” as “The coded information in the information section I that is provided as the pattern of electrically conductive portions and electrically insulating portions”. The relationship between metal layer, structured metal layer, and coded information is unclear.
In the specification, “electrically insulating portions” is not provided with a reference numeral. It is unclear which regions are to be considered electrically insulating portions within the ‘coded information’ region.
In the specification, “laminate layer” is described, but not provided with a reference numeral (in accordance with the drawings). As it is a claimed element, a reference numeral should be provided in accordance with the drawings. No new matter should be added.
In the specification, in ¶ [0035], it appears that ‘conductive’ is spelled incorrectly.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 9-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding dependent claim 9,
Claim 9, line 3 recites: “a structured metal layer”. The corresponding structure for “a structured metal layer” cannot be determined. It has been interpreted to mean there is at least a portion of a metal layer. Claims 10 and 11 are rejected by virtue of their dependency on Claim 9.
Regarding dependent claim 10,
Claim 10, lines 2-3 recites: “wherein the structured metal layer is formed from a continuous metal layer by selectively removing the structured metal layer..” it is unclear how a layer can be formed by removing it from itself. It has been interpreted to mean there is a metal layer.
Regarding dependent claim 11,
Claim 11, lines 2-3 recites: “wherein the structured metal layer is formed by selectively arranging the structured metal layer”. It is unclear how a layer is formed by arranging itself. It has been interpreted to mean there is a metal layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-11, 13-14, and 18 is rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Eilert (US 20050010725 A1).
Re: Independent Claim 1, Eilert discloses:
An embedded chip-package (Eilert, package; Figs. 3 and 4, elements 300/400), comprising:
a chip (Eilert; die; Fig. 4, element 416);
electrically insulating material (Eilert, passivation layer; Fig. 4, element 312, ¶ [0020]) at least partially encapsulating the chip;
at least one metal layer (Eilert, metal layer; Fig. 4, element 306) configured to provide at least one electrically conductive connection to the chip (Eilert, ¶ [0021]); and
an information section (Eilert, signal pass through; Fig. 4, element 420 or Fig. 3, element 320, both of which can be considered information sections as they are signal pass-through regions, see ¶ [0021] and ¶ [0026]) comprising coded information about the embedded chip-package (Eilert, the information section contains the coded information);
wherein, in the information section, the information is coded as a pattern of electrically conductive portions (Eilert, vias, through-silicon vias, Fig. 4, elements 308, and 310, respectively, can be considered electrically conductive portions, ¶ [0018 - 0021]) and electrically insulating portions (Eilert, interlayer dielectric (ILD) layers; Fig. 4, element 304).
Re: Dependent Claim 2, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
wherein the pattern of electrically conductive portions (Eilert, vias, through-silicon vias, Fig. 4, elements 308, and 310, respectively, can be considered electrically conductive portions, ¶ [0018 - 0021]) and electrically insulating portions (Eilert, interlayer dielectric (ILD) layers; Fig. 4, element 304) comprises a plurality of vertically elongated electrically conductive portions (Eilert, vias and through-silicon vias, Fig. 3, elements 308 and 310 are longer than they are wide, so they can be considered vertically elongated portions, ¶ [0027]) wherein at least two of the vertically elongated electrically conductive portions differ in diameter and/or in length (Eilert, Fig. 3 shows that elements 308 and 310 differ in length).
Re: Dependent Claim 3, Eilert disclose(s) all the limitations of claim 2 on which this claim depends. Eilert further discloses:
wherein at least one of the vertically elongated electrically conductive portions (Eilert, vias and through-silicon vias, Fig. 3, elements 308 and 310 are longer than they are wide, so they can be considered vertically elongated portions, ¶ [0027]) forms an electrically conductive connection between the chip (Eilert; die; Fig. 4, element 416) and the at least one metal layer (Eilert, metal layer; Fig. 4, element 306, ¶ [0019]).
Re: Dependent Claim 4, Eilert disclose(s) all the limitations of claim 2 on which this claim depends. Eilert further discloses:
wherein at least one of the vertically elongated electrically conductive portions (Eilert, vias and through-silicon vias, Fig. 3, elements 308 and 310 are longer than they are wide, so they can be considered vertically elongated portions, ¶ [0027]) has at least one electrically unconnected end (Eilert, Fig. 4, discloses one end of via 308 is connected to interconnect 404, which may be an optical connection, and not an electrical connection, ¶ [0026]).
Re: Dependent Claim 5, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
wherein the information section (Eilert, signal pass through; Fig. 4, element 420 or Fig. 3, element 320, both of which can be considered information sections as they are signal pass-through regions, see ¶ [0021] and ¶ [0026]) comprises a line or matrix of predefined pattern positions (Eilert, Figs. 3 and 4), and the pattern of electrically conductive portions (Eilert, vias, through-silicon vias, Fig. 4, elements 308, and 310, respectively, can be considered electrically conductive portions, ¶ [0018 - 0021]) and electrically insulating portions (Eilert, interlayer dielectric (ILD) layers; Figs. 3 and 4, element 304) is distributed over the predefined pattern positions (Eilert, Figs. 3 and 4).
Re: Dependent Claim 6, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
wherein the information section (Eilert, signal pass through; Fig. 4, element 420 or Fig. 3, element 320, both of which can be considered information sections as they are signal pass-through regions, see ¶ [0021] and ¶ [0026]) is exposed at an outer surface of the embedded chip-package (Eilert, Fig. 3, shows element 320 exposed at an outer surface of the embedded chip-package, element 300).
Re: Dependent Claim 7, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
wherein the information section (Eilert, signal pass through; Fig. 4, element 420 or Fig. 3, element 320, both of which can be considered information sections as they are signal pass-through regions, see ¶ [0021] and ¶ [0026]) is buried inside the embedded chip-package (Eilert, Fig. 4 shows 420 buried instead element 400).
Re: Dependent Claim 9, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
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wherein the pattern of electrically conductive portions (Eilert, vias, through-silicon vias, Fig. 4, elements 308, and 310, respectively, can be considered electrically conductive portions, ¶ [0018 - 0021]) and electrically insulating portions (Eilert, interlayer dielectric (ILD) layers; Fig. 4, element 304) is formed as a structured metal layer (Eilert, Fig. 4, see attached annotated image labeled structured metal layer, it contains the metal layers, element 306).
Re: Dependent Claim 10, Eilert disclose(s) all the limitations of claim 9 on which this claim depends. Eilert further discloses:
wherein the structured metal layer (Eilert, Fig. 4, see attached annotated image labeled structured metal layer) is formed from a continuous metal layer by selectively removing the structured metal layer in the electrically insulating portions (Eilert, the structured metal layer contains a metal layer, element 306).
Re: Dependent Claim 11, Eilert disclose(s) all the limitations of claim 9 on which this claim depends. Eilert further discloses:
wherein the structured metal layer (Eilert, Fig. 4, see attached annotated image labeled structured metal layer) is formed by selectively arranging the structured metal layer (Eilert, Fig. 4 shows metal layers (element 306) arranged around the conductive portions, which is a portion of the structured metal layer) in the electrically conductive portions (Eilert, vias, through-silicon vias, Fig. 4, elements 308, and 310, respectively, can be considered electrically conductive portions, ¶ [0018 - 0021]).
Re: Dependent Claim 13, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
wherein the pattern of electrically conductive portions (Eilert, vias, through-silicon vias, Fig. 4, elements 308, and 310, respectively, can be considered electrically conductive portions, ¶ [0018 - 0021]) and electrically insulating portions (Eilert, interlayer dielectric (ILD) layers; Fig. 4, element 304) is a two-dimensional or a three-dimensional pattern (Eilert, Fig. 4 shows 308, 310, and 304 as having at least a height and a width, and are therefore at least two-dimensional).
Re: Dependent Claim 14, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
wherein the coded information (Eilert, signal pass through; Fig. 4, element 420 or Fig. 3, element 320, both of which can be considered information sections as they are signal pass-through regions, see ¶ [0021] and ¶ [0026], the information section includes the coded information) about the embedded chip-package (Eilert, package; Figs. 3 and 4, elements 300/400) comprises at least one of a group of properties of the embedded chip-package, the group of properties consisting of:
a horizontal position of the chip (Eilert; die; Fig. 4, element 416) within the embedded chip-package (Eilert, Fig. 4 shows the chip has a horizontal position within the embedded chip);
a vertical position of the chip within the embedded chip-package (Eilert, Fig. 4 shows the chip has a vertical position within the embedded chip);
a lot ID;
an ID of the embedded chip-package; and
additional traceability data.
(Eilert discloses the coded information within the information section about the embedded chip package comprises at least one of the group of properties; a horizontal position and a vertical position, therefore the rest of the properties are not searched as the claim limitation is satisfied).
Re: Independent Claim 18, Eilert discloses:
An embedded chip-package (Eilert, package; Fig. 5 elements 400), comprising:
a chip (Eilert; die; Fig. 5, element 416);
electrically insulating material (Eilert, passivation layer; Fig. 5, element 312, ¶ [0020]) at least partially encapsulating the chip;
at least one metal layer (Eilert, metal layer; Fig. 5, element 306) configured to provide at least one electrically conductive connection to the chip (Eilert, ¶ [0021]); and
at least one vertically elongated electrically conductive portion (Eilert, through-silicon vias, Fig. 5, 310 are longer than they are wide, so they can be considered vertically elongated portions, ¶ [0019]) comprising a first end connected to the at least one metal layer (Eilert, Fig. 5, shows the top of element 310, which can be considered a first end, on die 416 connected to the metal layer, element 306) and a second end arranged in the electrically insulating material (Eilert, Fig. 5 shows the bottom end, which can be considered a second end of element 310, is arranged in the element 312 layer and connected to an interconnect, element 404),
wherein the second end is electrically unconnected (Eilert, Fig. 5 shows the second end of element 310 connected to the interconnect, 404, which may be an optical connection, and not an electrical connection, ¶ [0026], and therefore is electrically unconnected).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Eilert (US 20050010725 A1) in view of Kwon (US 20140062496 A1).
Re: Dependent Claim 8, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
wherein the coded information (Eilert, signal pass through; Fig. 4, element 420 or Fig. 3, element 320, both of which can be considered information sections as they are signal pass-through regions, see ¶ [0021] and ¶ [0026])
Eilert does not disclose:
wherein the coded information is configured to be determinable at least via X-ray imaging
Kwon discloses:
wherein the coded information (Kwon, density information, ¶ [0023]) is configured to be determinable at least via X-ray imaging (Kwon, X-ray image, ¶ [0023]).
Eilert discloses coded information but does not explicitly disclose this information to be determinable at least via X-ray imaging. Kwon discloses X-ray imaging for a semiconductor chip on a package substrate. Both disclose chip packaging structures and are therefore analogous art. It would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to use the configuration, as disclosed by Kwon, to the coded information of Eilert for the benefit of precise layering thickness (Kwon, ¶ [0023]).
Claim(s) 12 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Eilert (US 20050010725 A1) in view of Kim (US 7642203 B2).
Re: Dependent Claim 12, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
Eilert discloses:
the electrically insulating material (Eilert, passivation layer; Fig. 4, element 312, ¶ [0020])
Eilert does not explicitly disclose:
wherein the electrically insulating material comprises at least one laminate layer.
Kim discloses:
wherein the electrically insulating material (Kim, passivation layer with a triple layer structure; Fig. 2, not numbered) comprises at least one laminate layer (Kim, passivation layer are laminated, Col. 2, lines 28-33).
Eilert discloses the electrically insulating material (passivation layer) but does not disclose this layer to comprise at least one laminate layer. Kim discloses a passivation layer with a triple layer structure comprising multiple passivation layers that are laminated (i.e. containing at least one laminate layer). Eilert and Kim disclose semiconductor devices and are therefore analogous art. It would be obvious to a POSITA before the effective filing date to include the passivation structure comprising a least one laminate layer, as disclosed by Kim, to the passivation layer (electrically insulating material) disclosed by Eilert, arriving at the invention as claimed, for the benefit of strengthening the passivation layer, therefore protecting the semiconductor device underneath during any further processing (Kim, Col. 2, lines 57 - 62).
Claim(s) 15-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Eilert (US 20050010725 A1) in view of Kim (US 8873245 B2).
Re: Dependent Claim 15, Eilert disclose(s) all the limitations of claim 1 on which this claim depends. Eilert further discloses:
A semiconductor package, comprising:
the embedded chip-package of claim 1 (Eilert, package; Figs 3 and 4, element 300/400); and
material (Eilert, passivation layer; Fig. 4, element 312)
Eilert does not explicitly disclose:
packaging material at least partially encapsulating the embedded chip-package.
Kim discloses:
packaging material (Kim, encapsulation resin; Fig. 3, element 140) at least partially encapsulating the embedded chip-package (Kim, embedded COC package; Fig. 3, element 100A, element 140 covers a portion of the package 100A).
Eilert discloses an embedded chip-package structure, but does not explicitly disclose packaging material encapsulating the embedded chip-package. Kim discloses an encapsulation around the embedded chip package structure for use in a semiconductor device. In the absence of any criticality or unexpected results, it would be obvious to a POSITA before the effective filing date to use the packaging material (containing resin), as disclosed by Kim, on the device, as disclosed by Eilert, arriving at the invention as claimed, for additional layer protection that the encapsulation resin material provides (Kim, Col. 4, lines 23-26).
Re: Dependent Claim 16, Eilert and Kim disclose(s) all the limitations of claim 15 on which this claim depends. Eilert further discloses:
comprising a printed circuit board (PCB) (Eilert, printed circuit board; Fig. 5, element 440, ¶ [0035]) formed with the embedded chip-package (Eilert, ¶ [0035]) embedded as an inlay.
Re: Dependent Claim 17, Eilert and Kim disclose(s) all the limitations of claim 15 on which this claim depends. Eilert further discloses:
wherein a volume vertically above and/or below the information section (Eilert, signal pass through; Fig. 4, element 420 or Fig. 3, element 320, both of which can be considered information sections as they are signal pass-through regions, see ¶ [0021] and ¶ [0026]) is kept free from metal (Eilert, Fig. 4 shows no layers above element 420, and therefore that can be considered a volume vertically above free from metal) to allow for X-ray imaging of the information section (Eilert, Fig. 4 shows the structure required and therefore it is capable of allowing X-ray imaging).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Satoh (US 9478502 B2), Keeth (US 8130527 B2), Kagaya (US 7321165 B2) disclose semiconductor devices and elements such as conductive portions, information sections, and insulating portions and are therefore considered relevant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST).
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/NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
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