DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
In par. [0001]: insert US Patent no. 12094827.
Appropriate correction is required.
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,094,827 (US Application 18/216,989); 12,051,651 (US Application 18/202,136); and claims 1-22 of U.S. Patent No. 11,715,695 (US Application 17/555,213). Although the claims at issue are not identical, they are not patentably distinct from each other because they require similar limitations such as multiple-die IC package including first-fifth dies, first-fourth multi-die interconnect bridges coupling/communicating between the first die to second-fifth dies, organic substrate & embedded bridges, the brides with footprints, etc.
Current Appl. 18/806,287
1. A multi-die IC package, comprising:
a first die having a top surface and a bottom surface, a first side between the top surface and the bottom surface, and a second side between the top surface and the bottom surface, the second side opposite the first side;
a first multi-die interconnect bridge coupled to the first die proximate to the first side of the first die;
a second multi-die interconnect bridge coupled to the first die proximate to the first side of the first die;
a third multi-die interconnect bridge coupled to the first die proximate to the second side of the first die;
a fourth multi-die interconnect bridge coupled to the first die proximate to the second side of the first die;
a second die coupled to the first multi-die interconnect bridge, wherein the first multi-die interconnect bridge is electrically coupled to the first die and the second die;
a third die coupled to the second multi-die interconnect bridge, wherein the second multi-die interconnect bridge is electrically coupled to the first die and the third die;
a fourth die coupled to the third multi-die interconnect bridge, wherein the third multi-die interconnect bridge is electrically coupled to the first die and the fourth die; and
a fifth die coupled to the fourth multi-die interconnect bridge, wherein the fourth multi-die interconnect bridge is electrically coupled to the first die and the fifth die.
10. A multi-die IC package, comprising:
an organic substrate;
a first die coupled to the organic substrate, the first die having a top surface and a bottom surface, a first side between the top surface and the bottom surface, and a second side between the top surface and the bottom surface, the second side opposite the first side;
a first multi-die interconnect bridge embedded in the organic substrate, the first multi-die interconnect bridge coupled to the first die, wherein the first side of the first die overlaps the first multi-die interconnect bridge from a plan view perspective;
a second multi-die interconnect bridge embedded in the organic substrate, the second multi-die interconnect bridge coupled to the first die, wherein the first side of the first die overlaps the second multi-die interconnect bridge from the plan view perspective;
a third multi-die interconnect bridge embedded in the organic substrate, the third multi-die interconnect bridge coupled to the first die, wherein the second side of the first die overlaps the third multi-die interconnect bridge from the plan view perspective;
a fourth multi-die interconnect bridge embedded in the organic substrate, the fourth multi-die interconnect bridge coupled to the first die, wherein the second side of the first die overlaps the fourth multi-die interconnect bridge from the plan view perspective;
a second die coupled to the organic substrate, the second die coupled to the first multi-die interconnect bridge, wherein the second die overlaps the first multi-die interconnect bridge from the plan view perspective, and wherein the first multi-die interconnect bridge is electrically coupled to the first die and the second die;
a third die coupled to the organic substrate, the third die coupled to the second multi-die interconnect bridge, wherein the third die overlaps the second multi-die interconnect bridge from the plan view perspective, and wherein the second multi-die interconnect bridge is electrically coupled to the first die and the third die;
a fourth die coupled to the organic substrate, the fourth die coupled to the third multi-die interconnect bridge, wherein the fourth die overlaps the third multi-die interconnect bridge from the plan view perspective, and wherein the third multi-die interconnect bridge is electrically coupled to the first die and the fourth die; and
a fifth die coupled to the organic substrate, the fifth die coupled to the fourth multi-die interconnect bridge, wherein the fifth die overlaps the fourth multi-die interconnect bridge from the plan view perspective, and wherein the fourth multi-die interconnect bridge is electrically coupled to the first die and the fifth die.
18. A multi-die IC package, comprising:
a first die having a top surface and a bottom surface, a first side between the top surface and the bottom surface, and a second side between the top surface and the bottom surface, the second side opposite the first side;
a first multi-die interconnect bridge coupled to the first die proximate to the first side of the first die;
a second multi-die interconnect bridge coupled to the first die proximate to the first side of the first die;
a third multi-die interconnect bridge coupled to the first die proximate to the second side of the first die;
a second die coupled to the first multi-die interconnect bridge, wherein the first multi-die interconnect bridge enables is electrically coupled to the first die and the second die;
a third die coupled to the second multi-die interconnect bridge, wherein the second multi-die interconnect bridge is electrically coupled to the first die and the third die; and
a fourth die coupled to the third multi-die interconnect bridge, wherein the third multi-die interconnect bridge is electrically coupled to the first die and the fourth die.
US Patent no. 12,094,827
1. A multi-die IC package, comprising:
a first die having a top surface and a bottom surface, a first side between the top surface and the bottom surface, and a second side between the top surface and the bottom surface, the second side opposite the first side, the first die having a footprint;
a first multi-die interconnect bridge coupled to the first die, the first multi-die interconnect bridge overlapping with the first side of the first die from a plan view perspective, the first multi-die interconnect bridge having a footprint;
a second multi-die interconnect bridge coupled to the first die, the second multi-die interconnect bridge overlapping with the first side of the first die from the plan view perspective, the second multi-die interconnect bridge having a footprint;
a third multi-die interconnect bridge coupled to the first die, the third multi-die interconnect bridge overlapping with the second side of the first die from the plan view perspective, the third multi-die interconnect bridge having a footprint;
a fourth multi-die interconnect bridge coupled to the first die, the fourth multi-die interconnect bridge overlapping with the second side of the first die from the plan view perspective, the fourth multi-die interconnect bridge having a footprint;
a second die laterally spaced apart from the first side of the first die, the second die coupled to the first multi-die interconnect bridge, the second die having a footprint larger than the footprint of the first multi-die interconnect bridge;
a third die laterally spaced apart from the first side of the first die, the third die coupled to the second multi-die interconnect bridge, the third die having a footprint smaller than the footprint of the first die and larger than the footprint of the second multi-die interconnect bridge;
a fourth die laterally spaced apart from the second side of the first die, the fourth die coupled to the third multi-die interconnect bridge, the fourth die having a footprint smaller than the footprint of the first die and larger than the footprint of the third multi-die interconnect bridge; and
a fifth die laterally spaced apart from the second side of the first die, the fifth die coupled to the fourth multi-die interconnect bridge, the fifth die having a footprint smaller than the footprint of the first die and larger than the footprint of the fourth multi-die interconnect bridge.
US Patent No. 12,051,651
1. A multi-die IC package, comprising:
a first die having a top surface and a bottom surface, a first side between the top surface and the bottom surface, and a second side between the top surface and the bottom surface, the second side opposite the first side, the first die having a footprint;
a first multi-die interconnect bridge coupled to the first die proximate to the first side of the first die;
a second multi-die interconnect bridge coupled to the first die proximate to the first side of the first die;
a third multi-die interconnect bridge coupled to the first die proximate to the second side of the first die;
a fourth multi-die interconnect bridge coupled to the first die proximate to the second side of the first die;
a second die coupled to the first multi-die interconnect bridge, the second die having a footprint, wherein the first multi-die interconnect bridge enables communication between the first die and the second die;
a third die coupled to the second multi-die interconnect bridge, the third die having a footprint smaller than the footprint of the first die, wherein the second multi-die interconnect bridge enables communication between the first die and the third die;
a fourth die coupled to the third multi-die interconnect bridge, the fourth die having a footprint smaller than the footprint of the first die, wherein the third multi-die interconnect bridge enables communication between the first die and the fourth die; and
a fifth die coupled to the fourth multi-die interconnect bridge, the fifth die having a footprint smaller than the footprint of the first die, wherein the fourth multi-die interconnect bridge enables communication between the first die and the fifth die.
US Patent No. 11,715,695
1. A multi-die IC package, comprising:
a first die having a top surface and a bottom surface, a first side between the top surface and the bottom surface, and a second side between the top surface and the bottom surface, the second side opposite the first side;
a first multi-die interconnect bridge coupled to the first die proximate to the first side of the first die;
a second multi-die interconnect bridge coupled to the first die proximate to the first side of the first die;
a third multi-die interconnect bridge coupled to the first die proximate to the second side of the first die;
a fourth multi-die interconnect bridge coupled to the first die proximate to the second side of the first die;
a second die coupled to the first multi-die interconnect bridge, wherein the first multi-die interconnect bridge enables communication between the first die and the second die;
a third die coupled to the second multi-die interconnect bridge, wherein the second multi-die interconnect bridge enables communication between the first die and the third die;
a fourth die coupled to the third multi-die interconnect bridge, wherein the third multi-die interconnect bridge enables communication between the first die and the fourth die; and
a fifth die coupled to the fourth multi-die interconnect bridge, wherein the fourth multi-die interconnect bridge enables communication between the first die and the fifth die.
Allowable Subject Matter
4. Claims 1-22 would be allowable if rewritten or amended to overcome the rejection(s) under Double Patenting, set forth in this Office action.
Allowable subject matters include: “a first multi-die interconnect bridge coupled to the first die proximate to the first side of the first die; a second multi-die interconnect bridge coupled to the first die proximate to the first side of the first die; a third multi-die interconnect bridge coupled to the first die proximate to the second side of the first die; a fourth multi-die interconnect bridge coupled to the first die proximate to the second side of the first die; a second die coupled to the first multi-die interconnect bridge, wherein the first multi-die interconnect bridge is electrically coupled to the first die and the second die; a third die coupled to the second multi-die interconnect bridge, wherein the second multi-die interconnect bridge is electrically coupled to the first die and the third die; a fourth die coupled to the third multi-die interconnect bridge, wherein the third multi-die interconnect bridge is electrically coupled to the first die and the fourth die; and a fifth die coupled to the fourth multi-die interconnect bridge, wherein the fourth multi-die interconnect bridge is electrically coupled to the first die and the fifth die” (claim 1);
“a first multi-die interconnect bridge embedded in the organic substrate, the first multi-die interconnect bridge coupled to the first die, wherein the first side of the first die overlaps the first multi-die interconnect bridge from a plan view perspective; a second multi-die interconnect bridge embedded in the organic substrate, the second multi-die interconnect bridge coupled to the first die, wherein the first side of the first die overlaps the second multi-die interconnect bridge from the plan view perspective; a third multi-die interconnect bridge embedded in the organic substrate, the third multi-die interconnect bridge coupled to the first die, wherein the second side of the first die overlaps the third multi-die interconnect bridge from the plan view perspective; a fourth multi-die interconnect bridge embedded in the organic substrate, the fourth multi-die interconnect bridge coupled to the first die, wherein the second side of the first die overlaps the fourth multi-die interconnect bridge from the plan view perspective; a second die coupled to the organic substrate, the second die coupled to the first multi-die interconnect bridge, wherein the second die overlaps the first multi-die interconnect bridge from the plan view perspective, and wherein the first multi-die interconnect bridge is electrically coupled to the first die and the second die; a third die coupled to the organic substrate, the third die coupled to the second multi-die interconnect bridge, wherein the third die overlaps the second multi-die interconnect bridge from the plan view perspective, and wherein the second multi-die interconnect bridge is electrically coupled to the first die and the third die; a fourth die coupled to the organic substrate, the fourth die coupled to the third multi-die interconnect bridge, wherein the fourth die overlaps the third multi-die interconnect bridge from the plan view perspective, and wherein the third multi-die interconnect bridge is electrically coupled to the first die and the fourth die; and a fifth die coupled to the organic substrate, the fifth die coupled to the fourth multi-die interconnect bridge, wherein the fifth die overlaps the fourth multi-die interconnect bridge from the plan view perspective, and wherein the fourth multi-die interconnect bridge is electrically coupled to the first die and the fifth die” (claim 10); and
“a first multi-die interconnect bridge coupled to the first die proximate to the first side of the first die; a second multi-die interconnect bridge coupled to the first die proximate to the first side of the first die; a third multi-die interconnect bridge coupled to the first die proximate to the second side of the first die; a second die coupled to the first multi-die interconnect bridge, wherein the first multi-die interconnect bridge enables is electrically coupled to the first die and the second die; a third die coupled to the second multi-die interconnect bridge, wherein the second multi-die interconnect bridge is electrically coupled to the first die and the third die; and a fourth die coupled to the third multi-die interconnect bridge, wherein the third multi-die interconnect bridge is electrically coupled to the first die and the fourth die” (claim 18).
The closest prior arts include: Urashima et al. (US 2007/0045815, Fig. 1) teaches wiring board including substrate core, IC chips, and embedded ceramic capacitors; Gonzales et al. (US 2012/0161331, Fig. 5) teaches multi-chip package with plurality of embedded dies; Brothers et al. (US 2013/0141442, Fig. 3) teaches multiple modules, including stacked chips and embedded traces; Marais et al. (US 2013/0214425, Fig. 2) teaches dual side package on package including front & back side chips; and Roy et al. (US 2014/0174807, Fig. 3) teaches multi-chip interconnect using organic bridges, individually or in combination with/without prior arts of record, do not meet all limitations cited above.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 8/7/26
Prosecution Insights