DETAILED ACTION
This Office Action is in response to the Applicant’s Communication filed on 08/16/2024. In virtue of the communication:
Claims 1-26 are pending in the instant application.
Claims 27-57 canceled.
The references cited in the Information Disclosure Statement (IDS) filed on 10/31/2024 and 09/23/2025 have been considered by the examiner.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 13 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 4, line 4, “it” is not clear to what it is intended to be.
In claim 13, line 4, “it” is not clear to what it is intended to be.
In claim 19, line 4, “it” is not clear to what it is intended to be.
Clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Williams (U.S. Pub. 2013/0082615 A1).
Regarding claim 1, Williams discloses a light-emitting diode (LED) package configured for receiving and transmitting digital communication signals (Figs. 7-15C), the LED package comprising:
an LED chip (402, Fig. 8; 452A/452B, Fig. 9);
an LED driver (403, Fig. 8; 450, Fig. 9) configured to drive the LED chip by pulse width modulation (PWM from unit 459, Fig. 9, par [0169]); and
a PWM processor (459, Fig. 9) coupled to the LED driver of the LED chip, the PWM processor configured to provide an adjustable PWM phase (e.g., by phase A register 658A, Fig. 14) in a PWM output signal (timing circuit 459 generates two PWM pulses, par [0169]) to the LED driver for driving the LED chip.
Regarding claim 10, Williams discloses a method of light output control within a light-emitting diode (LED) package (Figs. 7-15C), the method comprising:
receiving an input brightness value (12 bits for PWM brightness duty factor, Fig. 15A-15C, par [0203]) for an LED chip (402, Fig. 8; 452A/452B, Fig. 9) within the LED package; and
producing a pulse width modulation (timing circuit 459 generates two PWM pulses, par [0169]) output signal within the LED package for electrically activating the LED chip according to the input brightness value, the PWM output signal comprising an adjustable PWM phase (e.g., by phase A register 658A, Fig. 14).
Regarding claim 16, Williams discloses a light-emitting diode (LED) display (pars [0171], Figs. 7-15C), comprising:
a display panel (LCD panel, par [0171]); and
at least one LED package (Figs. 7-15C) comprising:
an LED chip (402, Fig. 8; 452A/452B, Fig. 9);
an LED driver (403, Fig. 8; 450, Fig. 9) configured to drive the LED chip by pulse width modulation (PWM from unit 459, Fig. 9, par [0169]); and
a PWM processor (459, Fig. 9) coupled to the LED driver of the LED chip, the PWM processor configured to provide an adjustable PWM phase (e.g., by phase A register 658A, Fig. 14) in a PWM output signal (timing circuit 459 generates two PWM pulses, par [0169]) to the LED driver for driving the LED chip.
Regarding claim 23, Williams discloses a method of light output control for a light-emitting diode (LED) device (Figs. 3D, 7-15C), the method comprising:
sending a digital communication signal (from digital control and timing circuit 459, Fig. 9) to a plurality of serially connected LED packages (452A/452B, Fig. 9); and
electrically activating LED chips (452A/452B, Fig. 9, Fig. 14, par [0195]) within each LED package of the plurality of serially connected LED packages during a frame such that an overall current draw for the plurality of serially connected LED packages is defined during the frame (current draw as in Fig. 3D), and the overall current draw forms a profile with curved edges (Fig. 3D).
Regarding claims 2, 11 and 17, Williams discloses the LED package/display and method wherein the PWM processor is configured to receive a nonzero initial PWM counter value (data from PWM A register 657A is loaded into D latch 681A and data from Phase A register 658A is loaded into .PHI. latch 682A of Latch & Counter A block 680A, par [0195], Fig. 14) to provide the adjustable PWM phase (synthesizes two PWM pulses to the gates of DMOSFETs 519A and 519B, par [0195]).
Regarding claims 3, 12 and 18, Williams discloses the LED package/display and method wherein the PWM processor is configured to segment a PWM period of the PWM output signal into a plurality of sub-periods (PWM signals as in Figs. 15A-15C).
Regarding claims 4, 13 and 19, Williams discloses the LED package/display and method wherein a period of each frame of the PWM output signal is not an exact integer multiple of a PWM period of the PWM output signal (Figs. 15A-15C) such that a phase of the PWM output signal accumulates between each successive frame, and the phase continues with each successive frame from a point where it was stopped in a previous frame (the SLI bus data communication timing and clocking is asynchronous with the system's Vsync period and the Vsync pulse that begins each Vsync period, par [0210]).
Regarding claims 5, 14 and 20, Williams discloses the LED package/display and method wherein: the PWM processor is configured to provide a blanking time before the start of a PWM period of the PWM output signal (The counter used to count the GSC pulses during a blanking period can be included within latch 805, par [0240]); and the PWM processor is configured to adjust a length of the blanking time to adjust a start time for the start of the PWM period (the data from the digital counter used for PWM control, e.g., Latch & Counter A 680A in FIG. 14, can also be compared in magnitude against the blanking interval, par [0240]).
Regarding claims 6, 15 and 21, Williams discloses the LED package/display and method wherein: the PWM processor is configured to provide a blanking time before the start of a PWM period of the PWM output signal (The counter used to count the GSC pulses during a blanking period can be included within latch 805, par [0240]); and the PWM processor is configured to provide an intra-blanking signal to the LED driver during the blanking time (Blanking,…, operates by instructing SLED latch 805 to completely ignore the output of SLED comparator 801 for a specified number of GSC clock cycles, par [0240]).
Regarding claims 7, Williams discloses the LED package wherein the PWM processor is configured to provide a selectable number of PWM periods per frame in the PWM output signal (Figs. 15A-15C).
Regarding claims 8, Williams discloses the LED package wherein the PWM processor is configured to receive an input signal (from SPI data, Fig. 15A) designating the selectable number of PWM periods (Figs. 15A-15C).
Regarding claims 9, Williams discloses the LED package wherein the selectable number of PWM periods comprises continuous PWM periods until a stop event (Figs. 15A-15C).
Regarding claim 22, Williams discloses the display wherein the PWM processor is configured to provide a blanking time during each frame of the PWM output signal (The counter used to count the GSC pulses during a blanking period can be included within latch 805, par [0240]), and the blanking time is synchronized to an external signal (SPI data, Fig. 15A) received from other equipment external to the LED display.
Regarding claim 24, Williams discloses the method wherein electrically activating LED chips within each LED package of the plurality of serially connected LED packages comprises: providing a first pulse width modulation (PWM) phase for a first LED package of the plurality of serially connected LED packages; and providing a second PWM phase for a second LED package of the plurality of serially connected LED packages, wherein the second PWM phase is offset from the first PWM phase (Upon receiving a Vsync pulse, data from PWM A register 657A is loaded into D latch 681A and data from Phase A register 658A is loaded into .PHI. latch 682A of Latch & Counter A block 680A. At the same time, data from PWM B register 657B is loaded into D latch 681B and data from Phase B register 658B is loaded into .PHI. latch 682B of Latch & Counter B block 680B. Upon receiving subsequent clock signals on GSC grey scale clock, counter blocks 680A and 680B count the number of pulses in their .PHI. latches 682A and 682B and thereafter enable current flow in I-Precise circuits 518A and 518B, respectively, illuminating the associated LED string in Channel A or B, par [0195]).
Regarding claim 25, Williams discloses the method wherein the first PWM phase is provided by a first PWM processor (657A) of the first LED package (Channel A), and the second PWM phase is provided by a second PWM processor (657B) of the second LED package (Chanel B) (Fig. 14).
Regarding claim 26, Williams discloses the method further comprising: providing a first blanking time for the first LED package within the frame; and providing a second blanking time for the second LED package within the frame, wherein a start time or an end time of the second blanking time is offset from a start time or an end time of the first blanking time (The counter used to count the GSC pulses during a blanking period can be included within latch 805. Alternatively, the data from the digital counter used for PWM control, e.g., Latch & Counter A 680A in FIG. 14, can also be compared in magnitude against the blanking interval, par [0240] … it means unit 680A can offset the blanking time within the frame).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIMMY T VU whose telephone number is (571)272-1832. The examiner can normally be reached on 9:00 AM - 6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached on 571-270-7101. The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2800.
/JIMMY T VU/Primary Examiner, Art Unit 2844