DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 08/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 08/16/2024. These drawings are review and accepted by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-21 of U.S Patent No. 11,670,379 B2 (‘379). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘379 claims.
US Patent No. 11,670,379 B2
US Patent Application No. 2024/0412790 A1
1. An array of memory cells, comprising: a data line; a source; a plurality of pass gates connected in series between the data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, a second control gate capacitively coupled to its second channel, a first source/drain region connected to its first channel and to its second channel, and a second source/drain region connected to its first channel and to its second channel; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of the plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of the plurality of series-connected field-effect transistors are selectively connected to one another; and a plurality of backside gate lines, wherein each backside gate line is connected to the second control gate of a respective pass gate of the plurality of pass gates; wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.
2. The array of memory cells of claim 1, wherein, for each unit column structure of the plurality of unit column structures, a material forming the channel of the particular field-effect transistor of its respective plurality of field-effect transistors is electrically connected to the first control gate of its respective pass gate.
3. The array of memory cells of claim 1, wherein, for each unit column structure of the plurality of unit column structures, a material forming the channel of the particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first control gate of its respective pass gate.
4. The array of memory cells of claim 3, further comprising a high-K dielectric between the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of a particular unit column structure and the first channel of the respective pass gate of the particular unit column structure, wherein the high-K dielectric is formed below the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of the particular unit column structure.
5. The array of memory cells of claim 4, wherein the high-K dielectric is further formed adjacent sidewalls of the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of a particular unit column structure.
6. The array of memory cells of claim 1, wherein the first control gate of a particular pass gate of the plurality of pass gates is permanently electrically floating.
7. The array of memory cells of claim 1, wherein the first source/drain region and the second source/drain region of a particular pass gate of the plurality of pass gates each comprise a respective conductively-doped portion of an instance of a semiconductor.
8. The array of memory cells of claim 7, wherein the instance of the semiconductor has a serpentine shape.
9. The array of memory cells of claim 7, wherein the first channel of the particular pass gate and the second channel of the particular pass gate are a same channel of the particular pass gate.
10. The array of memory cells of claim 7, wherein the instance of the semiconductor contains the second channel of the particular pass gate.
11. The array of memory cells of claim 7, wherein the instance of the semiconductor is a first instance of the semiconductor, and wherein the first source/drain region and the second source/drain region of the particular pass gate each further comprise a respective conductively-doped portion of a second instance of a semiconductor.
12. The array of memory cells of claim 11, wherein the first instance of the semiconductor contains the second channel of the particular pass gate, and wherein the second instance of the semiconductor contains the first channel of the particular pass gate.
13. The array of memory cells of claim 1, wherein the first channel of a particular pass gate of the plurality of pass gates comprises a first semiconductor, wherein the second channel of the particular pass gate comprises a second semiconductor, wherein the first source/drain region of the particular pass gate comprises a first instance of conductively-doped semiconductor formed between the first semiconductor and the second semiconductor, and wherein the second source/drain region the particular pass gate comprises a second instance of the conductively-doped semiconductor formed between the first semiconductor and the second semiconductor.
14. An array of memory cells, comprising: a data line; a source; a plurality of pass gates connected in series between the data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, a second control gate capacitively coupled to its second channel, a first source/drain region connected to its first channel and to its second channel, and a second source/drain region connected to its first channel and to its second channel; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of the plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of the plurality of series-connected field-effect transistors are selectively connected to one another; and a plurality of backside gate lines, wherein each backside gate line is connected to the second control gate of a respective pass gate of the plurality of pass gates; wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to a conductive element of the first control gate of a respective pass gate of the plurality of pass gates.
15. The array of memory cells of claim 14, wherein the conductive element of the first control gate of the respective pass gate for a particular unit column structure of the plurality of unit column structures is formed below a material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of the particular unit column structure.
16. The array of memory cells of claim 15, wherein the conductive element of the first control gate of the respective pass gate for a particular unit column structure of the plurality of unit column structures is further formed adjacent sidewalls of the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of the particular unit column structure.
17. The array of memory cells of claim 14, wherein the conductive element of the first control gate of the respective pass gate for a particular unit column structure of the plurality of unit column structures comprises a conductively-doped polysilicon.
18. An array of memory cells, comprising: a data line; a source; a plurality of pass gates connected in series between the data line and the source, wherein each pass gate of the plurality of pass gates comprises a first channel, a second channel, a first control gate capacitively coupled to its first channel, a second control gate capacitively coupled to its second channel, a first source/drain region connected to its first channel and to its second channel, and a second source/drain region connected to its first channel and to its second channel; a plurality of unit column structures, wherein each unit column structure of the plurality of unit column structures comprises a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of the plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of the plurality of series-connected field-effect transistors are selectively connected to one another; and a plurality of backside gate lines, wherein each backside gate line is connected to the second control gate of a respective pass gate of the plurality of pass gates; wherein, for each unit column structure of the plurality of unit column structures, a material forming the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is electrically connected to a conductive element of the first control gate of a respective pass gate of the plurality of pass gates.
19. The array of memory cells of claim 18, wherein, for each unit column structure of the plurality of unit column structures, the conductive element of the first control gate of the respective pass gate for that unit column structure is formed below the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of that unit column structure.
20. The array of memory cells of claim 19, wherein, for each unit column structure of the plurality of unit column structures, the conductive element of the first control gate of the respective pass gate for that unit column structure is further formed adjacent sidewalls of the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of that unit column structure.
21. The array of memory cells of claim 18, wherein, for each unit column structure of the plurality of unit column structures, the conductive element of the first control gate of the respective pass gate for that unit column structure comprises a first conductively-doped polysilicon, and a second conductively-doped polysilicon formed between the first conductively-doped polysilicon and the material forming the channel of the particular field-effect transistor of the respective plurality of field-effect transistors of that unit column structure.
1. An apparatus, comprising: a plurality of series-connected first field-effect transistors selectively connected in series with a plurality of series-connected second field-effect transistors; wherein the plurality of series-connected first field-effect transistors are configured to store user data; and wherein a channel of the plurality of series-connected second transistors is capacitively coupled to a channel of a third transistor.
2. The apparatus of claim 1, wherein the plurality of series-connected second field-effect transistors are between the third transistor and the plurality of series-connected first field-effect transistors.
3. The apparatus of claim 1, wherein the channel of the second plurality of series-connected transistors is further capacitively coupled to a control gate of the third transistor.
4. The apparatus of claim 1, wherein the channel of the second plurality of series-connected transistors is connected to a control gate of the third transistor.
5. The apparatus of claim 1, further comprising: a plurality of series-connected third field-effect transistors connected in series with the plurality of series-connected first field-effect transistors and connected in series with the plurality of series-connected second field-effect transistors; wherein the plurality of series-connected third field-effect transistors are configured to selectively connect the plurality of series-connected first field-effect transistors to the plurality of series-connected second transistors.
6. The apparatus of claim 5, further comprising: a data line; and a plurality of series-connected fourth field-effect transistors connected in series with the plurality of series-connected first field-effect transistors and connected to the data line; wherein the plurality of series-connected fourth field-effect transistors are configured to selectively connect the plurality of series-connected first field-effect transistors to the data line.
7. The apparatus of claim 1, wherein the plurality of series-connected second field-effect transistors are configured to function collectively as a capacitance.
8. An apparatus, comprising: a data line; a channel material having a first end connected to the data line and having a second end; a charge-storage material surrounding the channel material and capacitively coupled to the channel material; a plurality of conductors, wherein each conductor of the plurality of conductors surrounds a respective portion of the charge-storage material and a respective portion of the channel material, and is capacitively coupled to its respective portion of the charge-storage material and its respective portion of the channel material; and a transistor having a channel capacitively coupled to the second end of the channel material.
9. The apparatus of claim 8, wherein the channel material is a hollow channel material, wherein its first end is an open end, and wherein its second end is a closed end.
10. The apparatus of claim 8, wherein the second end of the channel material is wider than the first end of the channel material.
11. The apparatus of claim 10, wherein a portion of the second end of the channel material extends laterally to underlie a portion of at least one conductor of the plurality of conductors.
12. The apparatus of claim 8, wherein the transistor further has a control gate capacitively coupled to the second end of the channel material.
13. The apparatus of claim 8, wherein the transistor further has a control gate connected to the second end of the channel material.
14. The apparatus of claim 8, wherein the plurality of conductors is a plurality of first conductors, wherein the charge-storage material surrounds only a portion of the channel material.
15. The apparatus of claim 14, wherein a second conductor surrounds a portion of the channel material not surrounded by the charge-storage material.
16. The apparatus of claim 15, wherein a control gate of the pass gate comprises the second conductor.
17. An array of memory cells, comprising: a first data line; a second data line; a source; a pass gate connected between the second data line and the source; a channel material connected to the first data line and capacitively coupled to a channel of the pass gate; a plurality of series-connected field-effect transistors, wherein respective portions of the channel material function as respective channels for the plurality of series-connected first field-effect transistors; a plurality of series-connected memory cells connected between the data line and the plurality of series-connected field-effect transistors, wherein respective portions of the channel material function as respective channels for the plurality of series-connected memory cells.
18. The array of memory cells of claim 17, wherein the plurality of series-connected first field-effect transistors are configured to function collectively as a capacitance.
19. The array of memory cells of claim 17, wherein a data state of a selected memory cell of the plurality of series-connected memory cells is programmable in response to a voltage level of a control gate of the selected memory cell and a voltage level of the first data line, and wherein the data state of the selected memory cell is able to be sensed on the second data line in response to a voltage level developed on a control gate of the pass gate by the channel material.
20. The array of memory cells of claim 19, wherein control gates of the plurality of series-connected field-effect transistors are configured to each receive a same voltage level lower than a pass voltage level during sensing of the data state of the selected memory cell.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al (US 10,762,973 B1 hereinafter “Lu”) in view of Bertin et al (US 7,528,437 B2 hereinafter “Bertin”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Lu, for example in Figs. 1-16, discloses an apparatus (see for example in Figs. 6-8 related in Figs. 1-5, 9-16), comprising: a plurality of series-connected first field-effect transistors selectively connected in series with a plurality of series-connected second field-effect transistors (e.g., strings 700n/710n/720n/730n within SB0/SB1/SB2/SB3 having a plurality of transistors; in Figs. 7-8 related in Figs. 1-6, 9-16); wherein the plurality of series-connected first field-effect transistors are configured to store user data (e.g., memory cells; in Figs. 7-8 related in Figs. 1-6, 9-16); and wherein a channel of the plurality of series-connected second transistors is coupled to a channel of a third transistor (e.g., channels 700a/710a/720a/730a; in Fig. 7-8 related in Figs. 1-6, 9-16).
However, Lu is silent with regard to the channel of the transistors is capacitively coupled to the channel of the transistor.
In the same field of endeavor, Bertin, for example in Figs. 1-9, discloses the channel of the transistors is capacitively coupled to the channel of the transistor (e.g., C.sub.CH-SUB capacitance is part of the device; in Fig. 1 related in Figs. 2-9).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Lu such as suppressing program disturb during program recovery in memory device (see for example in Figs. 1-16 of Lu) by incorporating the teaching of Bertin such as EEPROM using carbon nanotubes for cell storage (see for example in Figs. 1-9 of Bertin), for the purpose of controlling a capacitance network having typical relative capacitance value of C.sub.CH-SUB, coupled to the channel of the transistor (see Fig. 1 of Bertin disclosed).
Regarding claim 2, the above Lu/Bertin, combination discloses wherein the plurality of series-connected second field-effect transistors are between the third transistor and the plurality of series-connected first field-effect transistors (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 3, the above Lu/Bertin, combination discloses wherein the channel of the second plurality of series-connected transistors is further capacitively coupled to a control gate of the third transistor (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 4, the above Lu/Bertin, combination discloses wherein the channel of the second plurality of series-connected transistors is connected to a control gate of the third transistor (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 5, the above Lu/Bertin, combination discloses further comprising: a plurality of series-connected third field-effect transistors connected in series with the plurality of series-connected first field-effect transistors and connected in series with the plurality of series-connected second field-effect transistors (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above); wherein the plurality of series-connected third field-effect transistors are configured to selectively connect the plurality of series-connected first field-effect transistors to the plurality of series-connected second transistors (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 6, the above Lu/Bertin, combination discloses further comprising: a data line; and a plurality of series-connected fourth field-effect transistors connected in series with the plurality of series-connected first field-effect transistors and connected to the data line (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above); wherein the plurality of series-connected fourth field-effect transistors are configured to selectively connect the plurality of series-connected first field-effect transistors to the data line (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 7, the above Lu/Bertin, combination discloses wherein the plurality of series-connected second field-effect transistors are configured to function collectively as a capacitance (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding Independent Claim 8, Lu, for example in Figs. 1-16, discloses an apparatus (see for example in Figs. 6-8 related in Figs. 1-5, 9-16), comprising: a data line (e.g., BL; in Figs. 2-3, 5 related in Figs. 1, 4, 6-16); a channel material having a first end connected to the data line and having a second end (e.g., channels 700a/710a/720a/730a; in Fig. 7-8 related in Figs. 1-6, 9-16); a charge-storage material surrounding the channel material (see for example in Figs. 6-8 related in Figs. 1-5, 9-16); a plurality of conductors (see for example in Figs. 6-8 related in Figs. 1-5, 9-16), wherein each conductor of the plurality of conductors surrounds a respective portion of the charge-storage material and a respective portion of the channel material (see for example in Figs. 6-8 related in Figs. 1-5, 9-16), and is coupled to its respective portion of the charge-storage material and its respective portion of the channel material (see for example in Figs. 6-8 related in Figs. 1-5, 9-16); and a transistor having a channel capacitively coupled to the second end of the channel material (see for example in Figs. 6-8 related in Figs. 1-5, 9-16).
However, Lu is silent with regard to the charge-storage is capacitively coupled to the channel material.
In the same field of endeavor, Bertin, for example in Figs. 1-9, discloses the charge-storage is capacitively coupled to the channel material (e.g., C.sub.CH-SUB capacitance is part of the device; in Fig. 1 related in Figs. 2-9).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Lu such as suppressing program disturb during program recovery in memory device (see for example in Figs. 1-16 of Lu) by incorporating the teaching of Bertin such as EEPROM using carbon nanotubes for cell storage (see for example in Figs. 1-9 of Bertin), for the purpose of controlling a capacitance network having typical relative capacitance value of C.sub.CH-SUB, coupled to the channel of the transistor (see Fig. 1 of Bertin disclosed).
Regarding claim 9, the above Lu/Bertin, combination discloses wherein the channel material is a hollow channel material, wherein its first end is an open end, and wherein its second end is a closed end (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 10, the above Lu/Bertin, combination discloses wherein the second end of the channel material is wider than the first end of the channel material (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 11, the above Lu/Bertin, combination discloses wherein a portion of the second end of the channel material extends laterally to underlie a portion of at least one conductor of the plurality of conductors (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 12, the above Lu/Bertin, combination discloses wherein the transistor further has a control gate capacitively coupled to the second end of the channel material (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 13, the above Lu/Bertin, combination discloses wherein the transistor further has a control gate connected to the second end of the channel material (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 14, the above Lu/Bertin, combination discloses wherein the plurality of conductors is a plurality of first conductors, wherein the charge-storage material surrounds only a portion of the channel material (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 15, the above Lu/Bertin, combination discloses wherein a second conductor surrounds a portion of the channel material not surrounded by the charge-storage material (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 16, the above Lu/Bertin, combination discloses wherein a control gate
of the pass gate comprises the second conductor (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding Independent Claim 17, Lu, for example in Figs. 1-16, discloses an array of memory cells (within SB0/SB1/SB2/SB3 having a plurality of transistors; in Figs. 7-8 related in Figs. 1-6, 9-16), comprising: a first data line (e.g., BL; in Figs. 2-3, 5 related in Figs. 1, 4, 6-16); a second data line (e.g., BL; in Figs. 2-3, 5 related in Figs. 1, 4, 6-16); a source (e.g., SL; in Fig. 5 related in Figs. 1-4, 6-16); a pass gate connected between the second data line and the source (within SB0/SB1/SB2/SB3 having a plurality of transistors; in Figs. 7-8 related in Figs. 1-6, 9-16); a channel material connected to the first data line and coupled to a channel of the pass gate (e.g., channels 700a/710a/720a/730a; in Fig. 7-8 related in Figs. 1-6, 9-16); a plurality of series-connected field-effect transistors (e.g., strings 700n/710n/720n/730n within SB0/SB1/SB2/SB3 having a plurality of transistors; in Figs. 7-8 related in Figs. 1-6, 9-16), wherein respective portions of the channel material function as respective channels for the plurality of series-connected first field-effect transistors (see for example in Figs. 7-8 related in Figs. 1-6, 9-16); a plurality of series-connected memory cells connected between the data line and the plurality of series-connected field-effect transistors (see for example in Figs. 6-8 related in Figs. 1-5, 9-16), wherein respective portions of the channel material function as respective channels for the plurality of series-connected memory cells (see for example in Figs. 6-8 related in Figs. 1-5, 9-16).
However, Lu is silent with regard to the data line, capacitively coupled to the channel of the gate.
In the same field of endeavor, Bertin, for example in Figs. 1-9, discloses the data line, capacitively coupled to the channel of the gate (e.g., C.sub.CH-SUB capacitance is part of the device; in Fig. 1 related in Figs. 2-9).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Lu such as suppressing program disturb during program recovery in memory device (see for example in Figs. 1-16 of Lu) by incorporating the teaching of Bertin such as EEPROM using carbon nanotubes for cell storage (see for example in Figs. 1-9 of Bertin), for the purpose of controlling a capacitance network having typical relative capacitance value of C.sub.CH-SUB, coupled to the channel of the transistor (see Fig. 1 of Bertin disclosed).
Regarding claim 18, the above Lu/Bertin, combination discloses wherein the plurality of series-connected first field-effect transistors are configured to function collectively as a capacitance (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 19, the above Lu/Bertin, combination discloses wherein a data state of a selected memory cell of the plurality of series-connected memory cells is programmable in response to a voltage level of a control gate of the selected memory cell and a voltage level of the first data line (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above), and wherein the data state of the selected memory cell is able to be sensed on the second data line in response to a voltage level developed on a control gate of the pass gate by the channel material (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above).
Regarding claim 20, the above Lu/Bertin, combination discloses wherein control gates of the plurality of series-connected field-effect transistors are configured to each receive a same voltage level lower than a pass voltage level during sensing of the data state of the selected memory cell (see for example in Figs. 7-8 related in Figs. 1-6, 9-16 of Lu and also see in Fig. 1 related in Figs. 2-9 of Bertin, as discussed above). The structure in of prior art (Lu and Bertin) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 02/21/2026