Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chio et al (US Patent No. 11,349,053 B1) in view of Wang (US Patent Pub 20070207608 A1) and Brindle et al. (US Patent No. 6,574,114 B1).
Regarding Claim 1, Chio teaches a semiconductor package, comprising:
a package substrate having a first surface and a second surface, which are opposite to each other (Fig.12B, package substrate 1109 having a first surface and a second surface (See annotated figure below), which are opposite each other);
a substrate pad provided on the package substrate (Fig. 12B, substrate pad 1111A);
an anisotropic conductive pattern provided on the substrate pad, the anisotropic conductive pattern comprising conductive capsules and a polymer layer enclosing the conductive capsules (Fig. 12B, anisotropic conductive pattern 1115 provided on the substrate pad 1111A and comprising conductive capsules 1117. Column 24 lines 11-13 teaches 1117 are enclosed in a polymer layer);
a semiconductor chip mounted on the first surface of the package substrate (Fig. 12B, semiconductor chip 1101 mounted on the first surface of package substrate 1109);
and a coupling pillar pattern provided between the package substrate and the semiconductor chip (Fig. 12B, coupling pillar pattern 1105A).
Chio fails to teach a conductive coupling pattern in contact with a top surface of the substrate pad, wherein the coupling pillar pattern is connected to the conductive coupling pattern and the anisotropic conductive pattern is provided on the conductive coupling pattern.
However, Wang teaches a semiconductor package having a conductive coupling pattern in contact with a top surface of the substrate pad, wherein the coupling pillar pattern is connected to the conductive coupling pattern, and the anisotropic conductive pattern is provided on the conductive coupling pattern (Wang, fig. 4 teaches a conductive coupling pattern 360b in contact with the top surface of substrate pad 314/324, wherein the coupling pillar pattern 340 is connected to the conductive coupling pattern 360b, and the anisotropic conductive pattern 250 is provided on the conductive coupling pattern 360b).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Wang into the method of Chio by forming the semiconductor package having a conductive coupling pattern in contact with a top surface of the substrate pad, wherein the coupling pillar pattern is connected to the conductive coupling pattern, and the anisotropic conductive pattern is provided on the conductive coupling pattern. The ordinary artisan would have been motivated to modify Chio in the manner set forth above for at least the purpose of increasing the area of electrical connection (Wang, paragraph 0012).
While Chio in view of Wang teaches the semiconductor package described above, Chio in view of Wang fails to teach the semiconductor package having a trench formed in the first surface, wherein a top surface of the anisotropic conductive pattern is coplanar with the first surface.
However, Brindle teaches an electronic device having a trench formed in the first surface, wherein a top surface of the anisotropic conductive pattern is coplanar with the first surface (Brindle. Fig. 4 teaches an anisotropic conductive pattern 28 formed in trench (space between portions of 26). A top surface of 28 is coplanar with the first surface (top surface of 26)).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Brindle into the method of Chio in view Wang by forming the semiconductor package having a trench formed in the first surface, wherein a top surface of the anisotropic conductive pattern is coplanar with the first surface. The ordinary artisan would have been motivated to modify Chio in view of Wang in the manner set forth above for at least the purpose of optimize contact with target surfaces (Brindle, Column 9 lines 5-8).
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Regarding Claim 7, Chio in view of Wang and Brindle teaches the semiconductor package of claim 1, wherein a width of the coupling pillar pattern is smaller than a width of the substrate pad (Chio, fig. 12B teaches a width of coupling pillar pattern 1105A is smaller than a width of substrate pad 1111A).
Claim(s) 2-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chio in view of Wang and brindle as applied to claims 1 and 7 above, and further in view of Chu et al (Us Patent Pub 20170062374 A1) and Geyick et al. (US Patent Pub 20230420347 A1).
Regarding Claim 2, Chio in view of Wang and Brindle teaches the semiconductor package of claim 1.
Chio in view of Wang and Brindle fails to specifically teaches the package wherein each of the conductive capsules comprise gallium (Ga).
However, Chu teaches an electronic device utilizing an anisotropic conductive pattern wherein each of the conductive capsules comprise gallium (Ga) (Chu, Fig. 1 and paragraph 0101 teaches conductive capsules comprising gallium).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Chu unto the method of Chio in view of Wang and Brindle by forming the package wherein each of the conductive capsules comprise gallium (Ga). The ordinary artisan would have been motivated to modify Chio in view of Wang and Brindle in the manner set forth above for at least the purpose of improving device reliability/adhering process conditions while reducing error rate (Chu, paragraphs 0008-0010).
While Chio in view of Wang, Brindle, and Chu teach the package described above, Chio in view of Wang, Brindle, and Chu fails to specifically teach the package wherein the conductive coupling pattern comprises gallium (Ga).
However, Geyick teaches a semiconductor package wherein the conductive coupling pattern comprises gallium (Ga) (Geyick, Fgi. 1A and paragraph 0080 teaches 124 is a DTPS interconnect. Paragraph 0050 teaches that interconnects (such as interconnect 124) may be attached to structures such as substrate pads utilizing a conductive coupling pattern formed of gallium).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Geyick into the method of Chio in view of Wang, Brindle, and Chu by forming the semiconductor package wherein the conductive coupling pattern comprises gallium (Ga). The ordinary artisan would have been motivated to modify Chio in view of Wang, Brindle, and Chu in the manner set forth above for at least the purpose of mitigating mechanical failure (Geyick, paragraph 0048).
Regarding Claim 3, Chio in view of Wang, Brindle, Chu, and Geyick teaches the semiconductor package of claim 2, wherein the conductive capsules and the conductive coupling pattern further comprises at least one of indium (In), tin (Sn), nickel (Ni), gold (Au), or zinc (Zn) (Chio, column 24 lines 19-21 teach the conductive capsules comprise nickel. Geyick, paragraph 0050 teaches the conductive coupling pattern comprises indium).
Regarding Claim 4, Chio in view of Wang, Brindle, Chu, and Geyick teaches the semiconductor package of claim 1, wherein each of the conductive capsules comprises a conductor and a cover layer enclosing the conductor, and wherein a melting point of the conductor ranges from 10°C to 30°C (Paragraph 0024 of Applicant’s instant specification teaches the conductor of the conductive capsules that has a melting point between 10°C to 30°C can be gallium. Chu, Fig. 1 and paragraph 101 teaches conductive capsules 10 have a conductor C10 formed of gallium, and a cover layer S10 enclosing the conductor C10).
Regarding Claim 5, Chio in view of Wang, Brindle, Chu, and Geyick teaches the semiconductor package of claim 4, wherein the cover layer comprises at least one of a polymer layer and a metal oxide layer (Chio, column 24 lines 23-30 teach the conductive capsules comprise a polymer layer).
Regarding Claim 6, Chio in view of Wang, Brindle, and Chu teaches the semiconductor package of claim 1.
Chio in view of Wang, Brindle, and Chu fails to specifically teach the semiconductor package further comprises: an under-fill layer provided between the package substrate and the semiconductor chip to cover the top surface of the anisotropic conductive pattern; and a mold layer covering a top surface of the semiconductor chip and a portion of a top surface of the package substrate.
However, Geyick teaches a semiconductor package comprising:
an under-fill layer provided between the package substrate and the semiconductor chip to cover the top surface of the anisotropic conductive pattern (Geyick, fig. 6, under-fill layer 2266 provided between the package substrate 2252 and semiconductor chip 2257 to cover a top surface of the anisotropic conductive pattern 2265 (2265 is represented in figure 1 as 124. Paragraph 0080 teaches 124 is a DTPS interconnect, and paragraph 0047 teaches DTPS interconnects may be formed of an anisotropic conductive material. Therefore, 2265 may be formed of an anisotropic conductive material);
and a mold layer covering a top surface of the semiconductor chip and a portion of a top surface of the package substrate (Fig. 6, mold layer 2268 covering a top surface of semiconductor chip 2257 and and a portion of a top surface 2272 of package substrate 2252).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Geyick into the method of Chio in view of Wang, Brindle, and Chu by forming the semiconductor package comprising an under-fill layer provided between the package substrate and the semiconductor chip to cover the top surface of the anisotropic conductive pattern; and a mold layer covering a top surface of the semiconductor chip and a portion of a top surface of the package substrate. The ordinary artisan would have been motivated to modify Chio in view of Wang, Brindle, and Chu in the manner set forth above for at least the purpose of optimizing device performance and minimizing loss (Geyick, paragraph 0022).
Claim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chio in view of Wang and Brindle as applied to claims 1 and 7 above, and further in view of Karhade et al. (US Patent Pub 20220342150 A1).
Regarding Claim 8, Chio in view of Wang and Brindle teaches the semiconductor package of claim 1.
Chio in view of Wang and Brindle fails to teach the semiconductor package wherein the top surface of the substrate pad is located at a level lower than the first surface of the package substrate.
However, Karhade teaches a semiconductor package wherein the top surface of the substrate pad is located at a level lower than the first surface of the package substrate (Karhade, Fig. 1A teaches a package substrate 124 having a first surface and a second surface opposite each other (see annotated figure below) and a substrate pad formed in a trench within package substrate 124(see annotated figure below) with a top surface of the substrate pad located at a level lower than the first surface of the package substrate 124).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Karhade into the method of Chio in view of Wang and Brindle by forming the package substrate wherein the top surface of the substrate pad is located at a level lower than the first surface of the package substrate. The ordinary artisan would have been motivated to modify Chio in view of Wang and Brindle in the manner set forth above for at least the purpose of enabling high speed and low loss electrical communication between device components (Karhade, paragraph 0050).
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Regarding Claim 9, Chio in view of Wang, Brindle, and Karhade teaches the semiconductor package of claim 1, wherein the substrate pad is provided to cover the bottom surface of the trench and a side surface of the trench (Karhade, fig. 1A. See annotated figure above).
Regarding Claim 10, Chio in view of Wang, Brindle, and Karhade teaches the semiconductor package of claim 9, wherein the substrate pad comprises a protruding portion that is extended to a level higher than the first surface of the package substrate (Karhade, fig. 1A teaches the substrate pad comprises a protruding portion that is extended to a level higher than the first surface of the package substrate 124 (See annotated figure above)).
Regarding Claim 11, Chio in view of Wang, Brindle, and Karhade teaches the semiconductor package of claim 9, wherein the top surface of the substrate pad has a ring shape, when viewed in a plan view (Wang, Fig. 4 and paragraph 0031 teaches the top surface of substrate pad 314/324 has a ring shape when viewed in plan view).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chio (US Patent No. 11,349,053 B1) in view of Wang (US Patent Pub 20070207608 A1), Brindle (US Patent No. 6,574,114 B1), and Geyick (US Patent Pub 20230420347 A1).
Regarding Claim 12, Chio teaches a semiconductor package, comprising:
a package substrate having a first surface and a second surface, which are opposite to each other (Fig.12B, package substrate 1109 having a first surface and a second surface (See annotated figure below), which are opposite each other);
a substrate pad provided on the package substrate (Fig. 12B, substrate pad 1111A);
an anisotropic conductive pattern provided on the substrate pad, the anisotropic conductive pattern comprising conductive capsules including a first metal element and a polymer layer enclosing the conductive capsules (Fig. 12B, anisotropic conductive pattern 1115 provided on the substrate pad 1111A and comprising conductive capsules 1117. Column 24 lines 11-13 teaches the conductive capsules 1117 include a first metal element (inner portion of 1117, which can comprise silver) and a polymer layer (outer portion of 1117) enclosing the conductive capsules);
a semiconductor chip mounted on the first surface of the package substrate (Fig. 12B, semiconductor chip 1101 mounted on the first surface of package substrate 1109);
and a coupling pillar pattern provided between the package substrate and the semiconductor chip to penetrate the anisotropic conductive pattern (Fig. 12B, coupling pillar pattern 1105A provided between the package substrate 1109 and the semiconductor chip 1101 and penetrating the anisotropic conductive pattern 1117).
Chio fails to teach a conductive coupling pattern in contact with a bottom surface of the coupling pillar pattern and a top surface of the substrate pad, and that the coupling pillar pattern is coupled to the substrate pad.
However, Wang teaches a semiconductor package having a conductive coupling pattern in contact with a bottom surface of the coupling pillar pattern and a top surface of the substrate pad, and that the coupling pillar pattern is coupled to the substrate pad (Wang, fig. 4 teaches a conductive coupling pattern 360b in contact with the top surface of substrate pad 314/324 and a bottoms surface of the coupling pillar pattern 340. The coupling pillar pattern is electrically coupled to the substrate pad 314/324 through 360b).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Wang into the method of Chio by forming the semiconductor package having a conductive coupling pattern in contact with a bottom surface of the coupling pillar pattern and a top surface of the substrate pad, and that the coupling pillar pattern is coupled to the substrate pad. The ordinary artisan would have been motivated to modify Chio in the manner set forth above for at least the purpose of increasing the area of electrical connection (Wang, paragraph 0012).
While Chio in view of Wang teaches the semiconductor package described above, Chio in view of Wang fails to teach the semiconductor package having a trench formed in the first surface, wherein the anisotropic conductive pattern fills the trench.
However, Brindle teaches an electronic device having a trench formed in the first surface, wherein the anisotropic conductive pattern fills and the trench up to the first surface (Brindle. Fig. 4 teaches an anisotropic conductive pattern 28 formed in trench (space between portions of 26)).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Brindle into the method of Chio in view Wang by forming the semiconductor package having a trench formed in the first surface, wherein the anisotropic conductive pattern fills the trench. The ordinary artisan would have been motivated to modify Chio in view of Wang in the manner set forth above for at least the purpose of optimize contact with target surfaces (Brindle, Column 9 lines 5-8).
While Chio in view of Wang and Brindle teach the semiconductor package as described above, they fail to teach the conductive coupling pattern comprises the first metal element.
However, Geyick teaches a semiconductor package wherein the conductive coupling pattern comprises the first metal element (Geyick, Fig. 1A and paragraph 0080 teaches 124 is a DTPS interconnect. Paragraph 0050 teaches that interconnects (such as interconnect 124) may be attached to structures such as substrate pads utilizing a conductive coupling pattern formed of the first metal element, which comprises silver).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Geyick into the method of Chio in view of Wang and Brindle by forming the semiconductor package the conductive coupling pattern comprises the first metal element. The ordinary artisan would have been motivated to modify Chio in view of Wang and Brindle in the manner set forth above for at least the purpose of mitigating mechanical failure (Geyick, paragraph 0048).
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Regarding Claim 13, Chio in view of Wang, Brindle, and Geyick teaches the semiconductor package of claim 12, wherein each of the conductive capsules comprises a conductor and a cover layer enclosing a surface of the conductor, and wherein the conductor comprises the first metal element (Chio, fig. 12B teaches conductive capsules 1117 comprised of a conductor (inner portion of 1117) and a cover layer (outer portion of 1117) which encloses a surface of the conductor, and wherein the conductor comprises the first metal element (column 24 lines 11-13)).
Claim(s) 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chio in view of Wang, Brindle, and Geyick as applied to claims 12 and 13 above, and further in view of Chu (US Patent Pub 20170062374 A1).
Regarding Claim 14, Chio in view of Wang, Brindle, and Geyick teaches the semiconductor package of claim 12.
Chio in view of Wang, Brindle, and Geyick fail to specifically teach the melting point of the first metal element ranges from 10°C to 30°C.
However, Chu teaches an anisotropic conductive pattern having conductive capsules, wherein a melting point of the first metal element ranges from 10°C to 30°C (Paragraph 0024 of Applicant’s instant specification teaches the conductor of the conductive capsules that has a melting point between 10°C to 30°C can be gallium. Chu, Fig. 1 and paragraph 0101 teaches the first metal element C10 of the conductive capsules 10 can be formed of gallium).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Chu unto the method of Chio in view of Wang, Brindle, and Geyick by forming the package wherein a melting point of the first metal element ranges from 10°C to 30°C. The ordinary artisan would have been motivated to modify Chio in view of Wang and Brindle in the manner set forth above for at least the purpose of improving device reliability/adhering process conditions while reducing error rate (Chu, paragraphs 0008-0010).
Regarding Claim 15, Chio in view of Wang, Brindle, Chu, and Geyick teaches the semiconductor package of claim 12, wherein the first metal element comprises gallium (Ga) (Chu, paragraph 0101 teaches the first metal element C10 can be gallium).
Regarding Claim 16, Chio in view of Wang, Brindle, and Chu teaches the semiconductor package of claim 12.
Chio in view of Wang, Brindle, and Chu fails to specifically teach the semiconductor package further comprises: an under-fill layer provided between the package substrate and the semiconductor chip to cover the top surface of the anisotropic conductive pattern; and a mold layer covering a top surface of the semiconductor chip and a portion of a top surface of the package substrate.
However, Geyick teaches a semiconductor package comprising:
an under-fill layer provided between the package substrate and the semiconductor chip to cover the top surface of the anisotropic conductive pattern (Geyick, fig. 6, under-fill layer 2266 provided between the package substrate 2252 and semiconductor chip 2257 to cover a top surface of the anisotropic conductive pattern 2265 (2265 is represented in figure 1 as 124. Paragraph 0080 teaches 124 is a DTPS interconnect, and paragraph 0047 teaches DTPS interconnects may be formed of an anisotropic conductive material. Therefore, 2265 may be formed of an anisotropic conductive material);
and a mold layer covering a top surface of the semiconductor chip and a portion of a top surface of the package substrate (Fig. 6, mold layer 2268 covering a top surface of semiconductor chip 2257 and and a portion of a top surface 2272 of package substrate 2252).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Geyick into the method of Chio in view of Wang, Brindle, and Chu by forming the semiconductor package comprising an under-fill layer provided between the package substrate and the semiconductor chip to cover the top surface of the anisotropic conductive pattern; and a mold layer covering a top surface of the semiconductor chip and a portion of a top surface of the package substrate. The ordinary artisan would have been motivated to modify Chio in view of Wang, Brindle, and Chu in the manner set forth above for at least the purpose of optimizing device performance and minimizing loss (Geyick, paragraph 0022).
Regarding Claim 17, Chio in view of Wang, Brindle, Chu, and Geyick teaches the semiconductor package of claim 12, wherein a top surface of the conductive coupling pattern is located at a level that is lower than the first surface of the package substrate (Brindle, the embodiment of fig. 4 can be interpreted as being upside down. A top surface (surface in contact with 28) of conductive coupling pattern 20 is located at a level lower than the first surface of 26).
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chio in view of Wang, Brindle, and Geyick as applied to claims 12 and 13 above, and further in view of Karhade et al. (US Patent Patent Pub 20220342150 A1).
Regarding Claim 18, Chio in view of Wang, Brindle, and Geyick teaches the semiconductor package of claim 12.
Chio in view of Wang, Brindle, and Geyick fail to teach the semiconductor package wherein the substrate pad is provided to cover the bottom surface of the trench and a side surface of the trench.
However, Karhade teaches a semiconductor package wherein the substrate pad is provided to cover the bottom surface of the trench and a side surface of the trench (Karhade, Fig. 1A teaches a substrate pad to cover the bottom surface and side surface of a trench made by the substrate pad (see annotated figure below).
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It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Karhade into the method of Chio in view of Wang, Brindle, and Geyick by forming the semiconductor package wherein the substrate pad is provided to cover the bottom surface of the trench and a side surface of the trench. The ordinary artisan would have been motivated to modify Chio in view of Wang, Brindle, and Geyick in the manner set forth above for at least the purpose of enabling high speed and low loss electrical communication between device components (Karhade, paragraph 0050).
Regarding Claim 19, Chio in view of Wang, Brindle, Geyick, and Karhade teaches the semiconductor package of claim 12, wherein the substrate pad comprises a protruding portion that is extended to a level higher than the first surface of the package substrate (Karhade, fig. 1A teaches the substrate pad comprises a protruding portion that is extended to a level higher than the first surface of the package substrate 124 (See annotated figure above)).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chio (US Patent No. 11,349,053 B1) in view of Wang (US Patent Pub 20070207608 A1), Brindle (US Patent No. 6,574,114 B1), Geyick (US Patent Pub 20230420347 A1), and Chu (US Patent Pub 20170062374 A1).
Regarding Claim 20, Chio teaches a semiconductor package, comprising:
a package substrate having a first surface and a second surface, which are opposite to each other (Fig.12B, package substrate 1109 having a first surface and a second surface (See annotated figure below), which are opposite each other),
substrate pads (Fig. 12B, substrate pad 1111A);
anisotropic conductive patterns provided on the substrate pad, the anisotropic conductive patterns comprising conductive capsules and a polymer layer enclosing the conductive capsules (Fig. 12B, anisotropic conductive pattern 1115 provided on the substrate pad 1111A and comprising conductive capsules 1117. Column 24 lines 11-13 teaches 1117 are enclosed in a polymer layer);
a semiconductor chip mounted on the first surface of the package substrate (Fig. 12B, semiconductor chip 1101 mounted on the first surface of package substrate 1109);
coupling pillar patterns provided between the package substrate and the semiconductor chip to penetrate the anisotropic conductive patterns (Fig. 12B, coupling pillar patterns 1105A and 1105B provided between the package substrate 1109 and the semiconductor chip 1101 and penetrating the anisotropic conductive pattern 1117).;
Chio fails to specifically teach conductive coupling patterns disposed on the substrate pads, wherein the anisotropic conductive patterns are provided on the conductive coupling pattern, and the conductive coupling patterns are in contact with the coupling pillar patterns.
However, Wang teaches a semiconductor package having conductive coupling patterns disposed on the substrate pads, wherein the anisotropic conductive patterns are provided on the conductive coupling pattern, and the conductive coupling patterns are in contact with the coupling pillar patterns (Wang, fig. 4 teaches conductive coupling pattern 360b. 360b is disposed on substrate pads 314/324, on the anisotropic conductive pattern 250, and in contact with coupling pillar pattern 340).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Wang into the method of Chio by forming the semiconductor package having conductive coupling patterns disposed on the substrate pads, wherein the anisotropic conductive patterns are provided on the conductive coupling pattern, and the conductive coupling patterns are in contact with the coupling pillar patterns. The ordinary artisan would have been motivated to modify Chio in the manner set forth above for at least the purpose of increasing the area of electrical connection (Wang, paragraph 0012).
While Chio in view of Wang teaches the semiconductor package described above, Chio in view of Wang fail to teach the semiconductor package having comprising trenches spaced apart from each other, wherein the wherein the anisotropic conductive pattern fills the trenches, and a top surface of the anisotropic conductive pattern is coplanar with the first surface.
However, Brindle teaches an electronic device comprising trenches spaced apart from each other, wherein the wherein the anisotropic conductive pattern fills the trenches, and a top surface of the anisotropic conductive pattern is coplanar with the first surface (Brindle. Fig. 4 teaches an anisotropic conductive pattern 28 formed in trench (space between portions of 26). A top surface of 28 is coplanar with the first surface (top surface of 26). Fig. 1 teaches these structures in an array, therefore there are a plurality of trenches formed in a first surface and spaced apart).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Brindle into the method of Chio in view Wang by forming the semiconductor package comprising trenches spaced apart from each other, wherein the wherein the anisotropic conductive pattern fills the trenches, and a top surface of the anisotropic conductive pattern is coplanar with the first surface. The ordinary artisan would have been motivated to modify Chio in view of Wang in the manner set forth above for at least the purpose of optimize contact with target surfaces (Brindle, Column 9 lines 5-8).
While Chio in view of Wang and Brindle teach the semiconductor package described above, Chio in view of Wang and Brindle fail to teach the semiconductor package comprising an under-fill layer provided between the package substrate and the semiconductor chip to cover top surfaces of the anisotropic conductive patterns, a mold layer covering a top surface of the semiconductor chip and at least a portion of a top surface of the package substrate and solder balls on the second surface of the package substrate, and the conductive coupling pattern comprises gallium.
However, Geyick teaches a semiconductor package comprising an under-fill layer provided between the package substrate and the semiconductor chip to cover top surfaces of the anisotropic conductive patterns, a mold layer covering a top surface of the semiconductor chip and at least a portion of a top surface of the package substrate, and solder balls on the second surface of the package substrate, and the conductive coupling pattern comprises gallium (Geyick, fig. 6 teaches underfill layer 2266 provided between the package substrate 2252 and the semiconductor chip 2257 to cover top surfaces of anisotropic conductive patterns 2265 (2265 is represented by 124 in fig. 1. Paragraph 0080 teaches 124 is a DTPS interconnect. Paragraph 0047 teaches DTPS interconnects may be formed of an anisotropic conducive material. Therefore, 2265 is an anisotropic conductive pattern), a mold layer 2268 covering a top surface of the semiconductor chip 2257 and a portion of the top surface of the package substrate 2252, and solder balls 2270 on the second surface of the package substrate. Paragraph 0050 teaches that interconnects (such as interconnect 124) may be attached to structures such as substrate pads utilizing a conductive coupling pattern formed of gallium).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Geyick into the method of Chio in view of Wang and Brindle by forming the semiconductor package comprising an under-fill layer provided between the package substrate and the semiconductor chip to cover top surfaces of the anisotropic conductive patterns, a mold layer covering a top surface of the semiconductor chip and at least a portion of a top surface of the package substrate, and solder balls on the second surface of the package substrate, and the conductive coupling pattern comprises gallium. The ordinary artisan would have been motivated to modify Chio in view of Wang and Brindle in the manner set forth above for at least the purpose of mitigating mechanical failure (Geyick, paragraph 0048).
While Chio in view of Wang, Brindle, and Geyick teach the semiconductor device as described above, Chio in view of Wang, Brindle, and Geyick fail to teach the conductive capsules comprise gallium (Ga).
However, Chu teaches an electronic device having an anisotropic conductive pattern wherein the conductive capsules comprise gallium (Ga) (Chu, fig. 1 and paragraph 0101 teaches conductive capsules 10 comprise a metal C10, which can be formed of gallium).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Chu unto the method of Chio in view of Wang, Brindle, and Geyick by forming the package wherein the conductive capsules comprise gallium (Ga). The ordinary artisan would have been motivated to modify Chio in view of Wang, Brindle, and Geyick in the manner set forth above for at least the purpose of improving device reliability/adhering process conditions while reducing error
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rate (Chu, paragraphs 0008-0010).
Conclusion
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/V.R.G./ Examiner, Art Unit 2899
/JOHN M PARKER/ Primary Examiner, Art Unit 2899
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