Prosecution Insights
Last updated: October 27, 2026
Application No. 18/807,193

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

Non-Final OA §DOUBLEPATENT
Filed
Aug 16, 2024
Priority
Dec 20, 2013 — divisional of 9281401 +6 more
Examiner
VALENZUELA, PATRICIA D
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
655 granted / 725 resolved
+30.3% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
80 currently pending
Career history
833
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
67.2%
+27.2% vs TC avg
§102
16.8%
-23.2% vs TC avg
§112
6.5%
-33.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 725 resolved cases

Office Action

§DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 11 & 22 of U.S. Patent No. 10468305, in view of Glass (USPGPUB-DOCUMENT-NUMBER: 2014/0175543, hereinafter Glass). Regarding claim 1, claim(s) 11 of US Patent 10468305 recited “An integrated circuit comprising: a first gate electrode having a first longitudinal axis; a second gate electrode having a second longitudinal axis that is substantially aligned with the first longitudinal axis; a third gate electrode having a third longitudinal axis that is substantially parallel with the first longitudinal axis, wherein the second gate electrode is laterally spaced from the first gate electrode; a gate plug between the first gate electrode and the second gate electrode; a first contact electrode between the first gate electrode and the third gate electrode and having a fourth longitudinal axis that is substantially parallel with the first longitudinal axis; a second contact electrode spaced from the first contact electrode and having a fifth longitudinal axis that is substantially aligned with the fourth longitudinal axis; and a contact plug between the first contact electrode and the second contact electrode, wherein at least a portion of the contact plug is disposed between the first gate electrode and the third gate electrode, and wherein the contact plug has a different chemical composition than the gate plug US Patent 10468305 does not recite wherein the long axis of the first gate structure and the long axis of the second gate structure are along a same first central axis; wherein the long axis of the first contact electrode and the long axis of the second contact electrode are along a same second central axis; Glass disclose wherein the long axis of the first gate structure[0021,0022 of Glass] are along a same first central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Glass to the teachings of US Patent 10468305 in order to have for greater performance and/or providing smaller dies for smaller die implementations [0002, Glass]. In doing so, wherein the long axis of the first gate structure[0021,0022 of Glass] and the long axis of the second gate structure[US Patent 10468305] are along a same first central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; wherein the long axis of the first contact electrode [US Patent 10468305] and the long axis of the second contact electrode [US Patent 10468305] are along a same second central axis(since the axis is the main axis this may be interpreted as the central axis) [0075 of Glass]; Re claim 2 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 1, further comprising: a first fin structure having a long axis and a width, the long axis along a second direction, the second direction orthogonal to the direction, wherein the first gate electrode[US Patent 10468305] is over the first fin structure, and wherein the first contact electrode is over the first fin structure; a second fin structure having a long axis and a width, the long axis along the second direction, wherein the second gate electrode[US Patent 10468305] is over the second fin structure, and wherein the second contact electrode is over the second fin structure. Re claim 3 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 2, further comprising: a third gate electrode[US Patent 10468305] over the first fin structure, the third gate electrode[US Patent 10468305] having a long axis and a width, the long axis along the direction; and a fourth gate electrode[US Patent 10468305] over the second fin structure, the fourth gate electrode[US Patent 10468305] having a long axis and a width, the long axis along the direction, wherein the long axis of the third gate electrode[US Patent 10468305] and the long axis of the fourth gate electrode[US Patent 10468305] are along a same third central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; . Re claim 4 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 3, further comprising: a third contact electrode over the first fin structure, the third contact electrode having a long axis and a width, the long axis along the direction; and a fourth contact electrode over the second fin structure, the fourth contact electrode having a long axis and a width, the long axis along the direction, wherein the long axis of the third contact electrode and the long axis of the fourth contact electrode are along a same fourth central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; . Re claim 5 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 2, further comprising: a first gate dielectric layer between the first fin structure and the first gate electrode[US Patent 10468305]; and a second gate dielectric layer between the second fin structure and the second gate electrode[US Patent 10468305]. Re claim 6 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 1, wherein the gate plug has a width no greater than the width of the first gate electrode[US Patent 10468305] and no greater than the width of the second gate electrode[US Patent 10468305]. Re claim 7 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 1, wherein the contact plug has a chemical composition different than a chemical composition of the gate plug. Re claim 8 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 1, further comprising: a first nanowire structure having a long axis and a width, the long axis along a second direction, the second direction orthogonal to the direction, wherein the first gate electrode[US Patent 10468305] is over the first nanowire structure, and wherein the first contact electrode is over the first nanowire structure; a second nanowire structure having a long axis and a width, the long axis along the second direction, wherein the second gate electrode[US Patent 10468305] is over the second nanowire structure, and wherein the second contact electrode is over the second nanowire structure. Regarding claim 9, claim(s) 11 of US Patent 10468305 recited “integrated circuit comprising: a first gate electrode having a first longitudinal axis; a second gate electrode having a second longitudinal axis that is substantially aligned with the first longitudinal axis; a third gate electrode having a third longitudinal axis that is substantially parallel with the first longitudinal axis, wherein the second gate electrode is laterally spaced from the first gate electrode; a gate plug between the first gate electrode and the second gate electrode; a first contact electrode between the first gate electrode and the third gate electrode and having a fourth longitudinal axis that is substantially parallel with the first longitudinal axis; a second contact electrode spaced from the first contact electrode and having a fifth longitudinal axis that is substantially aligned with the fourth longitudinal axis; and a contact plug between the first contact electrode and the second contact electrode, wherein at least a portion of the contact plug is disposed between the first gate electrode and the third gate electrode, and wherein the contact plug has a different chemical composition than the gate plug US Patent 10468305 does not recite an integrated circuit structure, comprising: a first channel body having a long axis and a width, the long axis along a first direction; a second channel body having a long axis and a width, the long axis along the first direction; a first gate electrode over the first channel body, a second gate electrode over the second channel body, wherein the long axis of the first gate structure and the long axis of the second gate structure are along a same first central axis; a second contact electrode over the second channel body, wherein the long axis of the first contact electrode and the long axis of the second contact electrode are along a same second central axis; Glass disclose an integrated circuit structure, comprising: a first channel body(304 of Glass) wherein the axis of the first gate structure are along a same first central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Glass to the teachings of US Patent 10468305 in order to have for greater performance and/or providing smaller dies for smaller die implementations [0002, Glass]. In doing so, an integrated circuit structure, comprising: a first channel body(304 of Glass) having a long axis [US Patent 10468305] and a width, the long axis along a first direction; a second channel body(304 of Glass) having a long axis and a width, the long axis along the first direction; a first gate electrode[US Patent 10468305] over the first channel body(304 of Glass), a second gate electrode[US Patent 10468305] over the second channel body(304 of Glass), wherein the long axis[US Patent 10468305] of the first gate structure and the long axis of the second gate structure are along a same first central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; a first contact electrode[US Patent 10468305] over the first channel body, a second contact electrode over the second channel body(304 of Glass), the long axis along the second direction, wherein the long axis of the first contact electrode[US Patent 10468305] and the long axis of the second contact electrode[US Patent 10468305] are along a same second central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; Re claim 10 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 9, wherein the first channel body is a first nanowire, and the second channel body is second nanowire. Re claim 11 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 9, wherein the first channel body is a first fin structure, and the second channel body is second fin structure. Re claim 12 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 9, further comprising: a third gate electrode[US Patent 10468305] over the first channel body, the third gate electrode[US Patent 10468305] having a long axis and a width, the long axis along the second direction; and a fourth gate electrode[US Patent 10468305] over the second channel body, the fourth gate electrode[US Patent 10468305] having a long axis and a width, the long axis along the second direction, wherein the long axis of the third gate electrode[US Patent 10468305] and the long axis of the fourth gate electrode[US Patent 10468305] are along a same third central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; . Re claim 13 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 12, further comprising: a third contact electrode[US Patent 10468305] over the first channel body, the third contact electrode having a long axis and a width, the long axis along the second direction; and a fourth contact electrode[US Patent 10468305] over the second fin structure, the fourth contact electrode[US Patent 10468305] having a long axis and a width, the long axis along the second direction, wherein the long axis of the third contact electrode[US Patent 10468305] and the long axis of the fourth contact electrode are along a same fourth central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; . Re claim 14 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 9, further comprising: a third contact electrode[US Patent 10468305] over the first channel body, the third contact electrode[US Patent 10468305] having a long axis and a width, the long axis along the second direction; and a fourth contact electrode over the second channel body, the fourth contact electrode[US Patent 10468305] having a long axis and a width, the long axis along the second direction, wherein the long axis of the third contact electrode and the long axis of the fourth contact electrode[US Patent 10468305] are along a same third central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; . Re claim 15 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 9, further comprising: a first gate dielectric layer between the first channel body and the first gate electrode[US Patent 10468305]; and a second gate dielectric layer between the second channel body and the second gate electrode[US Patent 10468305]. Re claim 16 US Patent 10468305 and Glass disclose the integrated circuit structure of claim 9, wherein the insulating material has a width no greater than the width of the first gate electrode[US Patent 10468305] and no greater than the width of the second gate electrode[US Patent 10468305]. Regarding claim 17, claim(s) 22 of US Patent 10468305 recited “A computing device, comprising: a circuit board; and a die coupled with the circuit board, the die including: a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material; a gate plug between a first portion of a first individual line of the individual lines and a second portion of the first individual line, wherein the first portion corresponds to a first gate electrode of a first transistor device and the second portion corresponds to a second gate electrode of a second transistor device; a contact electrode material between the first individual line and a second individual line of the individual lines; and a contact plug between the first individual line and the second individual line and between a first contact electrode of the first transistor device and a second contact electrode of the second transistor device, wherein the contact plug comprises a first electrically insulative material and the gate plug comprises a second electrically insulative material that has a different chemical composition than the first electrically insulative material. US Patent 10468305 does not recite the first gate electrode having a long axis and a width, the long axis along a direction; a second gate electrode, the second gate electrode having a long axis and a width, the long axis along the direction, wherein the long axis of the first gate structure and the long axis of the second gate structure are along a same first central axis; the first contact electrode having a long axis and a width, the long axis along the direction; a second contact electrode, the second contact electrode having a long axis and a width, the long axis along the direction, wherein the long axis of the first contact electrode and the long axis of the second contact electrode are along a same second central axis; Glass disclose the first gate electrode[0021,0022 of Glass] , the long axis along a direction; wherein the long axis[0075 of Glass] of the first gate structure are along a same first central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Glass to the teachings of US Patent 10468305 in order to have for greater performance and/or providing smaller dies for smaller die implementations [0002, Glass]. In doing so, the first gate electrode[0021,0022 of Glass] having a long axis[0075 of Glass] and a width, the long axis along a direction; a second gate electrode[US Patent 10468305], the second gate electrode having a long axis[0075 of Glass] and a width, the long axis[0075 of Glass] along the direction, wherein the long axis[0075 of Glass] of the first gate structure and the long axis[0075 of Glass] of the second gate structure[US Patent 10468305] are along a same first central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; the first contact electrode[US Patent 10468305] having a long axis[0075 of Glass] and a width, the long axis[0075 of Glass] along the direction; a second contact electrode[US Patent 10468305], the second contact electrode having a long axis[0075 of Glass] and a width, the long axis[0075 of Glass] along the direction, wherein the long axis of the first contact electrode and the long axis[0075 of Glass] of the second contact electrode are along a same second central axis(since the axis is the main axis this may be interpreted as the central axis)[0075 of Glass]; Re claim 18 US Patent 10468305 and Glass disclose the computing device of claim 17, further comprising: a memory coupled to the board[US Patent 10468305]. Re claim 19 US Patent 10468305 and Glass disclose the computing device of claim 17, further comprising: a communication chip coupled to the board[US Patent 10468305]. Re claim 20 US Patent 10468305 and Glass disclose the computing device of claim 17, wherein the component is a packaged integrated circuit die[US Patent 10468305]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Aug 16, 2024
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §DOUBLEPATENT (current)

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.0%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 725 resolved cases by this examiner. Grant probability derived from career allowance rate.

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