DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. Amendments filed on 11/18/2025 have been entered.
Response to Arguments
2. Regarding to claim 1, applicant contends that Lee “describes a barrier layer 110 that is interposed between the BML, the node connection line 171 and the connection electrode 172. Therefore, it appears that Lee fails to disclose "a second conductive layer disposed on the first conductive layer and including a first conductive pattern overlapping the first voltage line’” Examiner respectfully disagrees. The claimed limitation in claim 1 does not include “a second conductive layer directly disposed on the first conductive layer and including a first conductive pattern overlapping the first voltage line’”
Regarding to independent claim 17, applicant argues that “Referring again to Lee's FIG. 6 below, the BML (e.g., middle BMLC) is disposed beneath the data line 181 and separated from the data line 181 by several intervening layers, including a second barrier layer 110b and a first planarization layer 118… Therefore, Lee does not appear to disclose "the first voltage line includes a body portion and a shielding portion extending from the body portion in the second direction to overlap the data line."”
Examiner respectfully disagrees. The claimed limitation in claim 17 does not include “the first voltage line includes a body portion and a shielding portion extending from the body portion in the second direction to directly overlap the data line”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. Claim(s) 1, 3, 5, 11-12, 14 and 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 2022/0181354).
As to claim 1, Lee teaches a display apparatus including pixels arranged in a display area, the display apparatus comprising:
a first conductive layer including a first voltage line (a shield layer BML, Figs. 5, 6, 7A, [0094] One end of the shield layer BML, that is, an end of one side of the first connection line BMLC1 may be connected to the first driving voltage supply line 11a);
a second conductive layer disposed on the first conductive layer (layer formed by connection electrode 172 and a node connection line 171, fig. 6) and including a first conductive pattern overlapping the first voltage line (a node connection line 171, fig. 6);
a semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the first conductive pattern ([0128] The semiconductor layer AS may include a first semiconductor layer AS1 of the first transistor T1 including the first channel region A1, the first source region S1 and the first drain region D1, fig. 6);
a third conductive layer disposed on the semiconductor layer (a layer formed by G1, CE1 and CE3, fig. 6) and including a second conductive pattern overlapping the first conductive pattern (CE1, fig. 6); and
a fourth conductive layer disposed on the third conductive layer and including a data line (layer including data lines 181 and driving voltage line 183, fig. 6) and a third conductive pattern overlapping the second conductive pattern (data lines 181, fig. 6),
wherein the first voltage line includes a body portion extending in a first direction and a shielding portion extending from the body portion in a second direction to overlap the data line, wherein the second direction crosses the first direction ([0204] The first connection lines BMLC1′ may each be arranged in parallel to the data line for each column, and the second connection lines BMLC2′ may each be arranged in parallel to the emission control line for each row. The first connection lines BMLC1′ may partially overlap the emission control line, and the second connection lines BMLC2′ may partially overlap the data line. Fig. 15 further illustrates that the horizontal part of BML overlapping the data line DL).
As to claim 3, Lee teaches the display apparatus, wherein the shielding portion is spaced apart from the first semiconductor pattern in a plan view (fig. 6 illustrates that the horizontal part of BML (corresponding to the shielding portion) only overlap the data line DL and not a node connection line 171).
As to claim 5, Lee teaches the display apparatus, wherein the data line includes a first data line, a second data line, and a third data line (fig. 13 illustrates plurality of data lines), and wherein the shielding portion includes a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line (fig. 14 illustrates a plurality of shield layer. [0204] The first connection lines BMLC1′ may partially overlap the emission control line, and the second connection lines BMLC2′ may partially overlap the data line. Fig. 15 further illustrates that the horizontal part of BML overlapping the data line DL), wherein the first shielding portion, the second shielding portion, and the third shielding portion have a same area (see fig. 14).
As to claim 11, Lee teaches the display apparatus, further comprising a fifth conductive layer (a layer comprising a first initialization voltage line 147, G4A, scan line 145 and CE2, fig. 6) disposed on the fourth conductive layer and including a third voltage line (a first initialization voltage line 147) extending in the second direction and overlapping the data line (fig. 5 illustrates a first initialization voltage line 147 overlapping data line DL).
As to claim 12, Lee teaches the display apparatus, further comprising a voltage supply line disposed in a peripheral area outside the display area and extending in the first direction (voltage supply line 11b, fig. 9), wherein the third voltage line crosses the display area and is connected to the voltage supply line in the peripheral area (driving voltage line PL, fig. 9).
As to claim 14, Lee teaches the display apparatus, wherein the pixel includes a display element including a pixel electrode (pixel electrode 310, fig. 6), an opposite electrode (opposite electrode 330, fig. 6), and an intermediate layer disposed between the pixel electrode and the opposite electrode (an intermediate layer 320, fig. 6), wherein a voltage supplied to the third voltage line is different than a voltage supplied to the opposite electrode ([0171] The opposite electrodes 330 may be provided as one body over a plurality of organic light-emitting diodes to correspond to the plurality of pixel electrodes 310).
As to claim 17, Lee teaches a display apparatus comprising:
a first pixel circuit electrically connected to a first light-emitting diode and a second pixel circuit electrically connected to a second light-emitting diode (fig. 3 illustrates a display with a plurality of pixels and fig. 2 illustrates one of the plurality of pixels having a pixel circuit and a light emitting diode OLED connected to it),
wherein each of the first pixel circuit and the second pixel circuit comprises:
a first voltage line extending in a first direction (fig. 15 illustrates power line BML of PL extending in horizontal direction);
a data line disposed on the first voltage line and extending in a second direction crossing the first direction (fig. 15 illustrates data line DL extending in a vertical direction and crossing the BML);
a capacitor (Cst, fig. 6) including a first capacitor electrode (CE1, fig. 6) and a second capacitor electrode (CE2, fig. 6) disposed on the first capacitor electrode (fig. 6);
a first transistor (T1, fig. 2) electrically connected between the first voltage line (ELVDD, fig. 2) and the capacitor (Cst, fig. 2);
a second transistor (T2, fig. 2) electrically connected to the data line (DATA, fig. 2) and a gate electrode of the first transistor (T1, fig. 2);
a third transistor (T4, fig. 2) electrically connected to a second voltage line (Vint1, fig. 2) extending in the first direction (fig. 15 illustrates VIL1 extending in the horizontal direction) and the gate electrode of the first transistor (T1, fig. 2); and
a fourth transistor (T5, fig. 2) electrically connected between the first voltage line (PL, fig. 2) and the first transistor (T1, fig. 2),
wherein the first voltage line includes a body portion (middle BML line BMLC connecting two BMLPs, fig. 15) and a shielding portion (BMLC overlapping the data line DL) extending from the body portion in the second direction to overlap the data line (BMLC that overlapped the data line DL is shifted in the second direction or shifted vertically from the middle BMLC).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 6-7 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0181354) in view of Wan et al (US 2024/0315075).
As to claim 6, Lee teaches the display apparatus, wherein the data line includes a first data line, a second data line, and a third data line (fig. 13 illustrates plurality of data lines), and wherein the shielding portion includes a first shielding portion overlapping the first data line, a second shielding portion overlapping the second data line, and a third shielding portion overlapping the third data line (fig. 14 illustrates a plurality of shield layer. [0204] The first connection lines BMLC1′ may partially overlap the emission control line, and the second connection lines BMLC2′ may partially overlap the data line. Fig. 15 further illustrates that the horizontal part of BML overlapping the data line DL),
Lee does not teach wherein an area of the first shielding portion is different from
an area of the second shielding portion and an area of the third shielding portion.
However, Wan teaches wherein an area of the first shielding portion is different from an area of the second shielding portion and an area of the third shielding portion ([0057] In the second direction Y, the farther the second pixel P2 is from the first pixel structure P1, the larger the area of the light-shielding layer in the pixel region of the second pixel P2 is, fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee to teach, wherein an area of the shielding portion of the first pixel circuit is less than an area of the shielding portion of the second pixel circuit, as suggested by Wan. The motivation would have been in order to control the gray-scale luminance of the pixel ([0057]).
As to claim 7, Lee in view of Wan teaches the display apparatus, wherein the pixels include a red pixel that emits red light, a blue pixel that emits blue light, and a green pixel that emits green light (Wan: RGB pixel, fig. 4), wherein the first data line is electrically connected to the red pixel (Wan: data line D, fig. 4).
As to claim 18, Lee does not teach the display apparatus as claimed.
However, Wan teaches the display apparatus, wherein an area of the shielding portion of the first pixel circuit is less than an area of the shielding portion of the second pixel circuit ([0057] the farther the second pixel P2 is from the first pixel P1, the larger the area of the light-shielding layer in the pixel region of the second pixel P2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee to teach, wherein an area of the shielding portion of the first pixel circuit is less than an area of the shielding portion of the second pixel circuit, as suggested by Wan. The motivation would have been in order to control the gray-scale luminance of the pixel ([0057]).
As to claim 19, Lee in view of Wan teaches the display apparatus, wherein the first light-emitting diode emits red light (Lee: [0086] The display element may emit, for example, red, green, blue, or white light).
5. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0181354) in view of Lee et al (US 2022/0156477).
As to claim 20, Lee354 does not teach the display apparatus as claimed.
However, Lee477 teaches the display apparatus, wherein the first voltage line and the second voltage line are disposed in a same layer ([0166] the first power line and the first initialization line may be disposed on the same layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee354 to teach, wherein the first voltage line and the second voltage line are disposed in a same layer, as suggested by Lee477. The motivation would have been in order to improve authentication methods using fingerprints ([0003]).
6. Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0181354) in view of Moon et al (US 2021/0234119).
As to claim 22, Lee teaches the display apparatus, wherein each of the first light-emitting diode and the second light-emitting diode includes a pixel electrode (pixel electrode 310, fig. 6), an opposite electrode (opposite electrode 330, fig. 6), and an intermediate layer disposed between the pixel electrode and the opposite electrode (intermediate layer 320, fig. 6),
Lee does not teach auxiliary electrodes located in a same layer as the pixel electrode; and a third voltage line extending in the first direction and electrically connecting the auxiliary electrodes to each other.
However, Moon teaches the display apparatus further comprising: auxiliary electrodes located in a same layer as the pixel electrode; and a third voltage line extending in the first direction and electrically connecting the auxiliary electrodes to each other ([0113] The auxiliary electrode APE and the pixel electrode PXE of the light emitting element EMD may be disposed on a same layer, fig. 4, [0114] The auxiliary electrode APE … may be electrically connected to the second power line 45, fig. 5 illustrates that auxiliary electrodes APE connected to each other ).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee to teach, auxiliary electrodes located in a same layer as the pixel electrode; and a third voltage line extending in the first direction and electrically connecting the auxiliary electrodes to each other, as suggested by Moon. The motivation would have been in order to reduce “reduction in reliability and a display failure of the display device” ([0005]).
Allowable Subject Matter
7. Claims 2, 4, 8-10, 13, 15-16, 21, and 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMEN W BOGALE/Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628