DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of information disclosure statement filed 16 August 2024.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIN et al; (Publication number: US 2021/0226020 A1), hereafter Lin.
Regarding claim 1:
Lin discloses a method for forming a semiconductor structure (Figure 1 10 semiconductor structure), comprising:
forming a first active region (Lin Figure 2A – 1 200p) and a second active region (Lin Figure 2A-1 200N), wherein each of the first active region and the second active region includes first semiconductor layers and second semiconductor layers alternatingly stacked (Lin Figure 2A-2 illustrates layers 106 and 108 alternately stacked);
replacing the first semiconductor layers of the second active region with dielectric layers (Lin Figure 2B – 1 dielectric layer 111 replaces layers removed to form trench 107 at region 200N);
removing the dielectric layers to form first gaps (Lin Figure 2C-1 dielectric layer is etched to form first gaps 113);
removing the first semiconductor layers of the first active region to form second gaps (Lin Figure 2B – 1 dielectric layer 111 replaces layers removed to form trench 107 at region 200P); and
forming a first gate stack to fill the first gaps and the second gaps (Lin Figure 2D-3 dummy gate 114 fills gaps illustrated in 2C -1).
Regarding claim 2:
Lin discloses the method for forming the semiconductor structure as claimed in claim 1, wherein the first gate stack surrounds the second semiconductor layers of the first active region to form a pull-up transistor, and the first gate stack surrounds the second semiconductor layers of the second active region to form a pull-down transistor (Lin Figure 6-1 [0125]).
Regarding claim 7:
Lin discloses the method for forming the semiconductor structure as claimed in claim 1, wherein the first active region and the second active region are formed in a static random-access memory (SRAM) cell region (Lin Figure 6-1 [0125]).
Allowable Subject Matter
Claims 9 – 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 9, the prior art does not disclose alone or in combination a method for forming a semiconductor structure, comprising: forming a first active region and a second active region, wherein the first active region includes first semiconductor layers and second semiconductor layers alternatingly stacked, and the second active region includes dielectric layers and the second semiconductor layers alternatingly stacked; removing the dielectric layers of the second active region while recessing the second semiconductor layers of the second active region with a first etching amount; removing the first semiconductor layers of the first active region while recessing the second semiconductor layers of the first active region with a second etching amount, wherein the second etching amount is higher than the first etching amount; and forming a gate stack to surround the second semiconductor layers of the first active region and the second semiconductor layers of the second active region, as claimed (emphasis added).
Regarding claim 14, the prior art does not disclose a semiconductor structure, comprising: a first transistor in a cell region and including first nanostructures and a first gate stack; a second transistor in the cell region and including second nanostructures and the first gate stack; and a gate spacer layer along the first gate stack, wherein: the first gate stack extends in a first horizontal direction, the first nanostructures include respective center portions surrounded by the first gate stack and having a first width in the first horizontal direction, and respective edge portions surrounded by the gate spacer layer and having a second width in the first horizontal direction, the second nanostructures include respective center portions surrounded by the first gate stack and having a third width in the first horizontal direction, and respective edge portions surrounded by the gate spacer layer and having a fourth width in the first horizontal direction, and a first ratio of the second width to the first width is less than a second ratio of the fourth width to the third width, as claimed (emphasis added).
Claims 10 – 13 and 15 – 20 depend on one of claims 9 and 14, accordingly, and are therefore similarly allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 3 – 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIHIR K RAYAN whose telephone number is (571)270-5719. The examiner can normally be reached Monday - Friday 9 - 5pm (EST).
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/MIHIR K RAYAN/ 20 August 2026primary Examiner, Art Unit 2622
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