Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated August 16, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the phrase “the number of bits”, both first and second occurrences, are unclear. In the first occurrence, the phrase lacks antecedent basis. In the second occurrence, the phrase, which appears to reference the first occurrence, that are “flipped” [line 7], is unclear since its use is for a different intended meaning making the antecedent unclear. It is suggested that the second occurrence should be made to distinct from the first phrase.
In claim 1, the phrase “corresponding first result at the target read voltage” is unclear. The phrase is used to “obtain a first threshold”, and then used to “determine a target valley voltage…after one adjustment” is confusing. The phrase appears to reference the two processes that is supposed to occur at the same time; however, the “determine” process appears to occur at a different time than that of the “obtain” process since it indicates that it’s done “after” an adjustment of the target read voltage.
In claim 1, the phrase “a corresponding first result at a maximum value in an effective range of predicted valley voltages” is unclear. The “first threshold”, in the claim, correlates to the maximum value, but is the “result” itself a value, or does it correspond to a maximum value of the range?
In claim 1, the phrase “a first result” is unclear. It is unclear because it was used to obtain different processes – the first was to “obtain a first result corresponding to at least one codeword at a target read voltage”; the second was to “obtain a first result corresponding to the at least one codeword at the adjusted target read voltage”. The later suggests a new type of result, yet both are called “first result”. It is unclear which “first result” is being used for subsequent calculations.
The dependent claims, claims 2-13, are rejected because they depend on the indefiniteness of the claim(s) from which they depend.
In claim 14, the phrase “the number of bits”, both first and second occurrences, are unclear. In the first occurrence, the phrase lacks antecedent basis. In the second occurrence, the phrase, which appears to reference the first occurrence, that are “flipped” [line 7], is unclear since its use is for a different intended meaning making the antecedent unclear. It is suggested that the second occurrence should be made to distinct from the first phrase.
In claim 14, the phrase “corresponding first result at the target read voltage” is unclear. The phrase is used to “obtain a first threshold”, and then used to “determine a target valley voltage…after one adjustment” is confusing. The phrase appears to reference the two processes that is supposed to occur at the same time; however, the “determine” process appears to occur at a different time than that of the “obtain” process since it indicates that it’s done “after” an adjustment of the target read voltage.
In claim 14, the phrase “a corresponding first result at a maximum value in an effective range of predicted valley voltages” is unclear. The “first threshold”, in the claim, correlates to the maximum value, but is the “result” itself a value, or does it correspond to a maximum value of the range?
In claim 14, the phrase “a first result” is unclear. It is unclear because it was used to obtain different processes – the first was to “obtain a first result corresponding to at least one codeword at a target read voltage”; the second was to “obtain a first result corresponding to the at least one codeword at the adjusted target read voltage”. The later suggests a new type of result, yet both are called “first result”. It is unclear which “first result” is being used for subsequent calculations.
In claim 15, the phrase “the number of bits”, both first and second occurrences, are unclear. In the first occurrence, the phrase lacks antecedent basis. In the second occurrence, the phrase, which appears to reference the first occurrence, that are “flipped” [line 7], is unclear since its use is for a different intended meaning making the antecedent unclear. It is suggested that the second occurrence should be made to distinct from the first phrase.
In claim 15, the phrase “corresponding first result at the target read voltage” is unclear. The phrase is used to “obtain a first threshold”, and then used to “determine a target valley voltage…after one adjustment” is confusing. The phrase appears to reference the two processes that is supposed to occur at the same time; however, the “determine” process appears to occur at a different time than that of the “obtain” process since it indicates that it’s done “after” an adjustment of the target read voltage.
In claim 15, the phrase “a corresponding first result at a maximum value in an effective range of predicted valley voltages” is unclear. The “first threshold”, in the claim, correlates to the maximum value, but is the “result” itself a value, or does it correspond to a maximum value of the range?
In claim 15, the phrase “a first result” is unclear. It is unclear because it was used to obtain different processes – the first was to “obtain a first result corresponding to at least one codeword at a target read voltage”; the second was to “obtain a first result corresponding to the at least one codeword at the adjusted target read voltage”. The later suggests a new type of result, yet both are called “first result”. It is unclear which “first result” is being used for subsequent calculations.
The dependent claims, claims 16-20, are rejected because they depend on the indefiniteness of the claim(s) from which they depend.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 12-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 3 and 10 of U.S. Patent No. 12411609 [‘609]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘609
1. A memory device, comprising: an array of memory cells comprising multiple memory cells, wherein a preset number of memory cells form one codeword; and peripheral circuit coupled with the array of memory cells and configured to: obtain a first result corresponding to at least one codeword at a target read voltage, wherein the first result comprises the number of bits which represents the number of bits in the at least one codeword which are flipped in two read results at a first read voltage and a second read voltage, and a difference between the first read voltage and the second read voltage is less than a preset voltage; obtain a first threshold according to the corresponding first result at the target read voltage, wherein the first threshold is to represent a corresponding first result at a maximum value in an effective range of predicted valley voltages; make at least one adjustment to the target read voltage, and after each adjustment, obtain a corresponding first result at the adjusted target read voltage; and determine a target valley voltage according to a relationship between a corresponding first result at a target read voltage after one adjustment and the first threshold meeting a first preset condition or according to a corresponding first result at a target read voltage after multiple adjustments meeting a second preset condition, wherein the target valley voltage is taken as a read voltage at which a read operation is performed on the at least one codeword.
1. A memory device, comprising: an array of memory cells, including a plurality of memory cells, wherein a preset number of the plurality of memory cells form a code word; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to at least one of the code words at a target read voltage, wherein the first result includes a number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; adjust the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage; obtain a first result corresponding to at least one of the code words at the adjusted read voltage; and determine a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words.
12. The memory device of claim 1, wherein the peripheral circuit is configured to: read storage data of the at least one codeword at the first read voltage, to obtain a second result; read storage data of the at least one codeword at the second read voltage, to obtain a third result; perform a logical operation on the second result and the third result, to obtain a fourth result; and count the number of bits in the fourth result which represent flip of bits in the third result relative to the second result, to obtain the first result.
2. The memory device of claim 1, wherein the peripheral circuit is configured to: read data stored in at least one of the code words at the target read voltage to obtain a second result; perform a first adjustment to the target read voltage, and read data stored in at least one of the code words at the adjusted target read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent flip of bits in the third result relative to the second result to obtain a first result.
13. The memory device of claim 12, wherein the peripheral circuit comprises: a first latch configured to store the second result; a second latch configured to store the third result; and a third latch configured to store the fourth result.
3. The memory device of claim 2, wherein the peripheral circuit comprises: a first latch configured to store the second result; a second latch configured to store the third result; and a third latch configured to store the fourth result.
14. A memory system, comprising: one or more memory devices, the memory device comprising: an array of memory cells comprising multiple memory cells, wherein a preset number of memory cells form one codeword; and peripheral circuit coupled with the array of memory cells and configured to: obtain a first result corresponding to at least one codeword at a target read voltage, wherein the first result comprises the number of bits which represents the number of bits in the at least one codeword which are flipped in two read results at a first read voltage and a second read voltage, and a difference between the first read voltage and the second read voltage is less than a preset voltage;
obtain a first threshold according to the corresponding first result at the target read voltage, wherein the first threshold is to represent a corresponding first result at a maximum value in an effective range of predicted valley voltages;
make at least one adjustment to the target read voltage, and after each adjustment, obtain a corresponding first result at the adjusted target read voltage;
and determine a target valley voltage according to a relationship between a corresponding first result at a target read voltage after one adjustment and the first threshold meeting a first preset condition or according to a corresponding first result at a target read voltage after multiple adjustments meeting a second preset condition, wherein the target valley voltage is taken as a read voltage at which a read operation is performed on the at least one codeword; and a memory controller coupled with the memory device and controlling the memory device.
10. A memory system, comprising: one or more memory device, comprising: an array of memory cells, including a plurality of memory cells, wherein a preset number of the plurality memory cells form a code word; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to at least one of the code words at a target read voltage, wherein the first result includes the number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage;
adjust the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage; obtain a first result corresponding to at least one of the code words at the adjusted read voltage;
and determine a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words; and a memory controller coupled to the memory device and controlling the memory device.
15. A memory controller, comprising a control component configured to: obtain a first result corresponding to at least one codeword at a target read voltage, wherein the at least one codeword is formed by a preset number of memory cells in an array of memory cells of at least one memory device coupled with the memory controller, wherein the first result comprises the number of bits which represents the number of bits in the at least one codeword which are flipped in two read results at a first read voltage and a second read voltage, and a difference between the first read voltage and the second read voltage is less than a preset voltage; obtain a first threshold according to the corresponding first result at the target read voltage, wherein the first threshold is to represent a corresponding first result at a maximum value in an effective range of predicted valley voltages; make at least one adjustment to the target read voltage, and after each adjustment, obtain a first result corresponding to the at least one codeword at the adjusted target read voltage; and determine a target valley voltage according to a relationship between a corresponding first result at a target read voltage after one adjustment and the first threshold meeting a first preset condition or according to a corresponding first result at a target read voltage after multiple adjustments meeting a second preset condition, wherein the target valley voltage is taken as a read voltage at which a read operation is performed on the at least one codeword.
10. A memory system, comprising: one or more memory device, comprising: an array of memory cells, including a plurality of memory cells, wherein a preset number of the plurality memory cells form a code word; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to at least one of the code words at a target read voltage, wherein the first result includes the number of bits which represents the number of bits in at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage, and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; adjust the target read voltage in accordance with the first result corresponding to at least one of the code words at the target read voltage; obtain a first result corresponding to at least one of the code words at the adjusted read voltage; and determine a valley voltage in accordance with a plurality of the first results, wherein the valley voltage is a read voltage for performing a read operation on at least one of the code words; and a memory controller coupled to the memory device and controlling the memory device.
As can be seen from the above table, similar to claim 1 of the patent '609, claim 1 of the application recites a memory device comprising an array of memory cells with a preset number of memory cells forming a codeword. The memory device also has peripheral circuit coupled to the array of memory cells configured to process a first result corresponding to the codeword at a target read voltage, wherein the first result has a number of bits which represents bits in the codeword which are flipped in two reading at two read voltages, and that the difference between the read voltages is less than a preset voltage. Additionally, and similar to the patent, the application also has a step of determining a valley voltage based on the first result, and a step to adjust the target read voltage according to the first result. Unlike the patent, the application included several steps in between to process similar operations such as process a step, prior to the "determining" to determine a valley voltage, which determines a threshold value to determine a valley voltage. Similarly, the application also has additional steps to adjust the target read voltage by adding in a cycle of adjustment to the target read voltage. However, all of the additional step result in determining a valley voltage which is taken as a read voltage.
In regards to claim 12, similar to claim 2 of the patent ‘609, the application recites the same processes – specifically, having the peripheral circuit read data of the codeword at the first read voltage and second read voltage to obtain a second result and third result, respectively. Perform a logical operation on the second and third results to obtain a fourth result. Count the number of bits in the fourth result that represent flip of bits in the third result relative to the second result to obtain a first result. Unlike the patent, the application recites "storage data" instead of "data stored" and “second read voltage” instead of performing an adjustment to the target read voltage to get another read voltage; however, it is reasonably understood that they are the same.
In regards to claim 13, similar to claim 3 of the patent ‘609, the application recites similar components and processes.
In regards to claim 14, similar to claim 10 of the patent ‘609, the application recites a memory system having an array of memory cells, wherein a preset number of cells form a codeword. The system also has peripheral circuit coupled to the memory array configured to first result corresponding to the codeword at a target read voltage. The first result includes the number of bits in the codeword which are flipped in two results of reading at a first and second read voltages, wherein a difference between the two read voltages is less than a preset voltage. Obtain first results at the adjusted target read voltage. Degerming a target valley voltage according to first results, wherein the valley voltage is a read voltage. Unlike the patent, the application further recites additional steps, such as obtaining a first threshold according to result at the target read voltage to determine a target valley voltage. However, all of the additional step result in determining a valley voltage which is taken as a read voltage.
In regards to claim 15, similar to the reasons provided in claim 14, the application further includes a recitation regarding a controller. However, it is reasonable to assume that the claimed memory device or process would have a controller to issue the instructions necessary to perform the claimed steps.
As can be seen, though the claim languages are not identical, claims 1 and 12-15 of the application recite similar overall processes as that of claims 1, 2, 3 and 10 of the patent. Thus, the patent protections have been granted to the earlier filed patent application.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 15, 2026