Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated August 16, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Claim Objections
Claims 2-13 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ayyapureddi [CN 111627487 A].
With respect to claim 1, Ayyapureddi discloses a memory device [fig. 1], comprising: a first
memory bank [any bank 12]; a second memory bank [any other bank 12]; and a redundancy analysis circuit [32] coupled to both the first memory bank and the second memory bank, and including: a redundancy circuit [within 50 – 2nd par. of the Specific implementation examples section] which stores invalid address information for the first memory bank and the second memory bank [“…the fuse array can be programmed to store (e.g., latch) invalid memory address…” – 1st par. of the Description section], and is configured to: output an invalid address signal according to an enable signal of the first memory bank or the second memory bank [it is noted that if a fuse array is programmed to store an invalid memory address, we can infer that the fuse array outputs that invalid address when read], wherein the invalid address signal includes the invalid address information for the first memory bank or the second memory bank [“…Each of the set of fuse banks may correspond to respective invalid memory addresses within a memory array of memory devices…” – 2nd par. of the Specific implementation examples section]; and a matching circuit [“…the fuse circuit may include a fuse latch (e.g., fuse latch circuit) and a matching circuit. …” - 2nd par. of the Specific implementation examples section] coupled to the redundancy circuit and configured to: receive a to-be-activated address signal and the invalid address signal, match to-be-activated address information in the to-be-activated address signal with the invalid address information in the invalid address signal, and output a matching address signal [“…after receiving the command of accessing the memory address, the memory device can use the matching circuit of the fuse bank and other circuits and/or logic to determine whether the memory address is corresponding to the stored invalid memory address. In addition, if the memory device determines that the memory address corresponds to the stored invalid memory address, then the memory device can reboot the command of accessing the redundant memory address associated with the fuse bank….” - 2nd par. of the Specific implementation examples section]. Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ayyapureddi [CN
111627487 A].
With respect to claim 14, Ayyapureddi discloses a memory system [fig. 1], comprising: one or more memory devices [10], each comprising: a first memory bank [any bank 12]; a second memory bank [any other bank 12]; and a redundancy analysis circuit [32] coupled to both the first memory bank and the second memory bank, and including: a redundancy circuit [within 50 – 2nd par. of the Specific implementation examples section] which stores invalid address information for the first memory bank and the second memory bank [“…the fuse array can be programmed to store (e.g., latch) invalid memory address…” – 1st par. of the Description section], and is configured to: output an invalid address signal according to an enable signal of the first memory bank or the second memory bank [it is noted that if a fuse array is programmed to store an invalid memory address, we can infer that the fuse array outputs that invalid address when read], wherein the invalid address signal includes the invalid address information for the first memory bank or the second memory bank [“…Each of the set of fuse banks may correspond to respective invalid memory addresses within a memory array of memory devices…” – 2nd par. of the Specific implementation examples section]; and a matching circuit [“…the fuse circuit may include a fuse latch (e.g., fuse latch circuit) and a matching circuit. …” - 2nd par. of the Specific implementation examples section] coupled to the redundancy circuit and configured to: receive a to-be-activated address signal and the invalid address signal, match to-be-activated address information in the to-be-activated address signal with the invalid address information in the invalid address signal, and output a matching address signal [“…after receiving the command of accessing the memory address, the memory device can use the matching circuit of the fuse bank and other circuits and/or logic to determine whether the memory address is corresponding to the stored invalid memory address. In addition, if the memory device determines that the memory address corresponds to the stored invalid memory address, then the memory device can reboot the command of accessing the redundant memory address associated with the fuse bank….” - 2nd par. of the Specific implementation examples section]; and a memory controller [“…The memory device 10 performs operations (e.g., read commands and write commands) based on a command/address signal received from an external device (e.g., a processor). In one embodiment, the command/address bus may be a 14-bit bus that receives a command/address signal (CA <13: 0 >). The command/address signal uses the clock signal (Clk_t/ and Clk_c) to time to the command interface 14. The command interface may include a command address input circuit 20 configured to receive and transmit commands to (e.g.,) provide access to the memory bank 12 by command decoder 32….” – par. 11th of The memory device 10 performs operations (e.g., read commands and write commands) based on a command/address signal received from an external device (e.g., a processor). In one embodiment, the command/address bus may be a 14-bit bus that receives a command/address signal (CA <13: 0 >). The command/address signal uses the clock signal (Clk_t/ and Clk_c) to time to the command interface 14. The command interface may include a command address input circuit 20 configured to receive and transmit commands to (e.g.,) provide access to the memory bank 12 by command decoder 32…”] coupled to the memory devices and configured to control the memory devices.
Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ayyapureddi [CN
111627487 A].
With respect to claim 15, Ayyapureddi discloses a method for operating a memory device [fig. 1], wherein the memory device includes a first memory bank [any bank 12] and a second memory bank [any other bank 12], and a redundancy analysis circuit [32] coupled to both the first memory bank and the second memory bank, the method comprising: by a redundancy circuit [within 50 – 2nd par. of the Specific implementation examples section] of the redundancy analysis circuit, storing invalid address information for the first memory bank and the second memory bank [“…the fuse array can be programmed to store (e.g., latch) invalid memory address…” – 1st par. of the Description section], outputting an invalid address signal according to an enable signal of the first memory bank or the second memory bank [it is noted that if a fuse array is programmed to store an invalid memory address, we can infer that the fuse array outputs that invalid address when read], the invalid address signal including the invalid address information for the first memory bank or the second memory bank [“…Each of the set of fuse banks may correspond to respective invalid memory addresses within a memory array of memory devices…” – 2nd par. of the Specific implementation examples section]; and by a matching circuit [“…the fuse circuit may include a fuse latch (e.g., fuse latch circuit) and a matching circuit. …” - 2nd par. of the Specific implementation examples section] of the redundancy analysis circuit coupled to the redundancy circuit, receiving a to-be-activated address signal and the invalid address signal, matching to-be-activated address information in the to-be-activated address signal with the invalid address information in the invalid address signal, and outputting a matching address signal [“…after receiving the command of accessing the memory address, the memory device can use the matching circuit of the fuse bank and other circuits and/or logic to determine whether the memory address is corresponding to the stored invalid memory address. In addition, if the memory device determines that the memory address corresponds to the stored invalid memory address, then the memory device can reboot the command of accessing the redundant memory address associated with the fuse bank….” - 2nd par. of the Specific implementation examples section].
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 2: The memory device of claim 1, further comprising: a decoding circuit including a first decoding circuit which is coupled to the redundancy analysis circuit and configured to: receive the to-be-activated address signal and the matching address signal; and generate a first decoding signal according to the to-be-activated address signal and the matching address signal, wherein the first decoding signal includes at least one of to-be-activated normal address information or to-be-activated redundancy address information for the first memory bank or the second memory bank; a first register coupled to the first decoding circuit, and configured to: store the first decoding signal, in response to an enable signal of the first memory bank being in an enable state; and a second register coupled to the first decoding circuit, and configured to: store the first decoding signal in response to an enable signal of the second memory bank being in an enable state.
-with respect to claim 5: The memory device of claim 1, further comprising: a decoding circuit, including: a second decoding circuit coupled to the redundancy analysis circuit and configured to: receive the to-be-activated address signal and the matching address signal, in response to the enable signal of the first memory bank being in an enable state; and generate a second decoding signal according to the to-be-activated address signal and the matching address signal, wherein the second decoding signal includes at least one of to-be-activated normal address information or to-be-activated redundancy address information for the first memory bank; and a third decoding circuit coupled to the redundancy analysis circuit and configured to: receive the to-be-activated address signal and the matching address signal, in response to the enable signal of the second memory bank being in an enable state; and generate a third decoding signal according to the to-be-activated address signal and the matching address signal, wherein the third decoding signal includes at least one of to-be-activated normal address information or to-be-activated redundancy address information for the second memory bank.
-with respect to claim 16: The method of claim 15, further comprising: by a first decoding circuit in a decoding circuit coupled to the redundancy analysis circuit, receiving the to-be-activated address signal and the matching address signal, and generating a first decoding signal according to the to-be-activated address signal and the matching address signal, wherein the first decoding signal includes at least one of to-be-activated normal address information or to-be-activated redundancy address information for the first memory bank or the second memory bank; by a first register coupled to the first decoding circuit, storing the first decoding signal, in response to the enable signal of the first memory bank; and by a second register coupled to the first decoding circuit, storing the first decoding signal, in response to the enable signal of the second memory bank.
-with respect to claim 19: The method of claim 15, further comprising: by a second decoding circuit in a decoding circuit coupled to the redundancy analysis circuit, receiving the to-be-activated address signal and the matching address signal in response to the enable signal of the first memory bank being in an enable state, and generating a second decoding signal according to the to-be-activated address signal and the matching address signal, wherein the second decoding signal includes at least one of to-be-activated normal address information or to-be-activated redundancy address information for the first memory bank; and by a third decoding circuit in a decoding circuit coupled to the redundancy analysis circuit, receiving the to-be-activated address signal and the matching address signal in response to the enable signal of the second memory bank being in an enable state, and generating a third decoding signal according to the to-be-activated address signal and the matching address signal, wherein the third decoding signal includes at least one of to-be-activated normal address information or to-be-activated redundancy address information for the second memory bank.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 16, 2026