DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/11/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 8, 9, 13-16, and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 7, 8, 13, 14, 17, 18, and 20 of U.S. Patent No. 11,630,788. Please see chart below for comparison between independent claim 2 of the instant patent application and claim 1 of the US Patent. Note that independent claims 14 and 21 are rejected for Double Patenting for the same reasons as independent claim 1.
Instant Patent Application
US Patent No. 11,630,788
Notes
2. (New) A memory controller to control the operation of a first memory device and a second memory device, the memory controller comprising:
1. A memory controller to control the operation of a first memory device and a second memory device, the memory controller comprising:
same
a timing circuit, including:
a first storage element to store a first calibration value used to control timing for receiving data from the first memory device, and a second storage element to store a second calibration value used to control writing data to the first memory device; and
a first register to store a first phase value for receiving data
from the first memory device;
a second register to store a second phase value for
receiving data from the second memory device;
replaces register with storage element and replaces phase value with calibration value
a third storage element to store a third calibration value used to control timing for receiving data from the second memory device, and a fourth storage element to store a fourth
calibration value used to control writing data to the second memory device;
instant application merely adds more storage elements performing the same function
a timing circuit to derive the first phase value based on first calibration data associated with the first memory device, wherein the first calibration data is to be established based on a strobe signal received from the first
memory device via a respective strobe signal line, and to derive the second phase value based on second calibration data associated with the second memory device, wherein the second calibration data is to be
established based on a strobe signal received from the second memory device via a respective strobe signal line; and
instant application omits the use of strobe signals to establish the calibration data. Instant application is thus more broad but not patentably distinct
a sampling circuit, coupled to the timing circuit, to receive data from the first memory device based on the first calibration value and from the second memory device based on the third calibration value; and
a sampling circuit, coupled to the timing circuit and at least one signal line, to receive data based on the first phase value and the second phase value.
basically the same limitation
a transmitter, coupled to the timing circuit, to write data to the first memory device based
on the second calibration value and to write data to the second memory device based on the
fourth calibration value.
13. The memory controller of claim 1, further comprising a transmitter, coupled to the timing circuit, to transmit data to the first memory device in accordance with the first phase
value and to transmit data to the second memory device in
accordance with the second phase value.
basically same limitation from claim 13 of the US Patent
Although the claims at issue are not identical, they are not patentably distinct from each other because both the instant patent application and the US Patent No. 11,630,788 teach a memory controller comprising timing circuitry and a sampling circuit coupled therewith to receive data from memory devices based on calibration values; however, changes and omissions cited in Notes column of the chart above do not make the instant patent application patentably distinct from the US Patent.
Allowable Subject Matter
Claims 3-7, 10-12, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable (with resolution to the above Double Patenting rejection) if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2-21 would be allowable with resolution to the above Double Patenting rejection.
The following is a statement of reasons for the indication of allowable subject matter: With exception of parent patent applications including above cited US Patent 11,630,788, prior art fails to specifically teach timing circuitry including multiple storage elements storing associated calibration values for controlling timing for receiving data from memory devices and receiving data from the memory devices based on the calibration values. Accordingly, with a timely filed Terminal Disclaimer the instant patent application would be in condition for allowance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael J. Brown whose telephone number is (571)272-5932. The examiner can normally be reached Monday-Thursday from 5:30am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini Shah can be reached at (571)272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael J Brown/
Primary Examiner, Art Unit 2115
Prosecution Insights