Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
4. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, 2, 7, 3, 8, 9, 4, 5, 6, 10, 11, 14, 12, 15, 13, 16, 17, 18, 20, 19 in Patent No. 12,066,969 respectively.Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1, 2, 7, 3, 8, 9, 4, 5, 6, 10, 11, 14, 12, 15, 13, 16, 17, 18, 20, 19 of the US Patent No. 12,066,969 are similar in scope to claims 1-20 of the present application with only obvious wording variations.
Present Application
Pat No. 12,066,969
1. A integrated circuit (IC) die, comprising: an adaptive chip-to-chip (C2C) interface comprising circuitry for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection,
wherein the semiconductor chip is configured to, during boot time, configure the adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with the external IC die; and
processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die, wherein the IC die and the external IC die are components of a chip-to-chip configuration.
2. The IC die of claim 1, wherein the plurality of different C2C protocols are streaming C2C protocols.
3. The IC die of claim 2, wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol.
4. The IC die of claim 1, wherein the adaptive C2C interface further comprises: a de-multiplexer (de-mux) comprising outputs coupled to data paths corresponding to the plurality of different C2C protocols, wherein the de-mux is configured to select only one of the data paths as an output during runtime; and a mux coupled to the data paths as inputs and configured to and select between one of the data paths to output to one of the external IC die or the processing circuitry.
5. The IC die of claim 4, wherein the adaptive C2C interface further comprises: options circuitry disposed along the data paths and between the de-mux and the mux, wherein the options circuitry permits the adaptive C2C interface to customize the plurality of different C2C protocols.
6. The IC die of claim 5, wherein the adaptive C2C interface further comprises: coarse registers for storing coarse grain configuration for controlling the de-mux and the mux to select only one of the data paths; and fine registers for storing fine grain configuration for controlling the options circuitry to customize the one of the plurality of different C2C protocols.
7. The IC die of claim 1, wherein the adaptive C2C interface is configured to receive a first data word (DW) from the external IC die and transmit a second DW to the external IC die, wherein the adaptive C2C interface is configurable, at boot time, to use a first one of the plurality of different C2C protocols to receive the first DW and use a second, different one of plurality of different C2C protocols to transmit the second DW.
8. The IC die of claim 1, further comprising: a second adaptive C2C interface disposed on a different side of the IC die than the adaptive C2C interface, wherein the second adaptive C2C interface comprising circuitry for supporting the plurality of different C2C protocols, wherein the IC die is configured to, during boot time, configure the second adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with a second external IC die.
9. The IC die of claim 1, wherein the circuitry in the adaptive C2C interface corresponding to one of the plurality of different C2C protocols that was not selected during boot time is not used during runtime, wherein the IC die is one of an anchor or a chiplet in the chip-to-chip configuration.
10. A system, comprising: a first IC die comprising a hardened C2C interface comprising circuitry for supporting only a first C2C protocol; and
a second IC die connected to the first IC die, wherein one of the first and second IC dies is an anchor and the other is a chiplet, wherein the second IC die comprising an adaptive C2C interface comprising circuitry for supporting a plurality of different C2C protocols,
wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform only the first C2C protocol to communicate with the hardened C2C interface in the first IC die.
11. The system of claim 10, further comprising: an interposer, wherein the hardened C2C interface and the adaptive C2C interface communicate with each other via the interposer.
12. The system of claim 11, further comprising: a third IC die connected to the interposer and comprising a second hardened C2C interface comprising circuitry for supporting only the first C2C protocol, wherein the second IC die comprises a second adaptive C2C interface comprising circuitry for supporting the plurality of different C2C protocols, wherein the first IC die is configured to, during boot time, configure the second adaptive C2C interface to perform only the first C2C protocol to communicate with the second hardened C2C interface in the third IC die via the interposer.
13. The system of claim 10, wherein the plurality of different C2C protocols are streaming C2C protocols.
14. The system of claim 13, wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol.
15. The system of claim 10, wherein the adaptive C2C interface further comprises: a de-mux comprising outputs coupled to data paths corresponding to the plurality of different C2C protocols, wherein the de-mux is configured to select only one of the data paths as an output during runtime; and a mux coupled to the data paths as inputs and configured to and select between one of the data paths to output to the first IC die.
16. The system of claim 15, wherein the adaptive C2C interface further comprises: options circuitry disposed along the data paths and between the de-mux and the mux, wherein the options circuitry permits the adaptive C2C interface to customize the plurality of different C2C protocols.
17. A system, comprising: a chiplet comprising a first adaptive C2C interface comprising circuitry for supporting a plurality of different C2C protocols, wherein the chiplet is configured to, during boot time, configure the first adaptive C2C interface to perform only a first C2C protocol of the plurality of different C2C protocols; and
an anchor connected to the chiplet, the anchor comprising a second adaptive C2C interface comprising circuitry for supporting the plurality of different C2C protocols,
wherein the anchor is configured to, during boot time, configure the first adaptive C2C interface to perform only the first C2C protocol to communicate with the first adaptive C2C interface in the chiplet.
18. The system of claim 17, further comprising: an interposer, wherein the first and second adaptive C2C interfaces communicate with each other via the interposer.
19. The system of claim 18, further comprising: a second chiplet connected to the interposer and comprising a third adaptive C2C interface, wherein the anchor comprises a fourth adaptive C2C interface configured to communicate with the third adaptive C2C interface in the second chiplet via the interposer.
20. The system of claim 17, wherein the plurality of different C2C protocols are streaming C2C protocols.
1. An integrated circuit (IC) die, comprising: an adaptive chip-to-chip (C2C) interface comprising a [mux and a de-mux] (i.e. as circuitry) for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection,
processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die, wherein the IC die and the external IC die are components of a chip-to-chip configuration.
2. The IC die of claim 1, wherein the plurality of different C2C protocols are streaming C2C protocols.
7. The IC die of claim 2, wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol.
3. The IC die of claim 1, wherein the de-mux comprises outputs coupled to the data paths corresponding to the plurality of different C2C protocols, wherein the de-mux is configured to select only one of the data paths as an output during runtime; and the mux coupled to the data paths as inputs and configured to and select between one of the data paths to output to one of the external IC die or the processing circuitry.
8. The IC die of claim 3, wherein the adaptive C2C interface further comprises: options circuitry disposed along the data paths and between the de-mux and the mux, wherein the options circuitry permits the adaptive C2C interface to customize the plurality of different C2C protocols.
9. The IC die of claim 8, wherein the adaptive C2C interface further comprises: coarse registers for storing coarse grain configuration for controlling the de-mux and the mux to select only one of the data paths; and fine registers for storing fine grain configuration for controlling the options circuitry to customize the one of the plurality of different C2C protocols.
4. The IC die of claim 1, wherein the adaptive C2C interface is configured to receive a first data word (DW) from the external IC die and transmit a second DW to the external IC die, wherein the adaptive C2C interface is configurable, at boot time, to use a first one of the plurality of different C2C protocols to receive the first DW and use a second, different one of plurality of different C2C protocols to transmit the second DW.
5. The IC die of claim 1, further comprising: a second adaptive C2C interface disposed on a different side of the IC die than the adaptive C2C interface, wherein the second adaptive C2C interface comprising circuitry for supporting the plurality of different C2C protocols, wherein the IC die is configured to, during boot time, configure the second adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with a second external IC die.
6. The IC die of claim 1, wherein the circuitry in the adaptive C2C interface corresponding to one of the plurality of different C2C protocols that was not selected during boot time is not used during runtime, wherein the IC die is one of an anchor or a chiplet in the chip-to-chip configuration.
10. A system, comprising: a first IC die comprising a hardened C2C interface comprising circuitry for supporting only a first C2C protocol; and
a second IC die connected to the first IC die, wherein one of the first and second IC dies is an anchor and the other is a chiplet, wherein the second IC die comprising an adaptive C2C interface comprising [a mux and a de-mux] (i.e. as circuitry) for supporting a plurality of different C2C protocols,
wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform only the first C2C protocol to communicate with the hardened C2C interface in the first IC die.
11. The system of claim 10, further comprising: an interposer, wherein the hardened C2C interface and the adaptive C2C interface communicate with each other via the interposer.
14. The system of claim 11, further comprising: a third IC die connected to the interposer and comprising a second hardened C2C interface comprising circuitry for supporting only the first C2C protocol, wherein the second IC die comprises a second adaptive C2C interface comprising circuitry for supporting the plurality of different C2C protocols, wherein the first IC die is configured to, during boot time, configure the second adaptive C2C interface to perform only the first C2C protocol to communicate with the second hardened C2C interface in the third IC die via the interposer.
12. The system of claim 10, wherein the plurality of different C2C protocols are streaming C2C protocols.
15. The system of claim 12, wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol.
13. The system of claim 10, wherein the de-mux comprises outputs coupled to the data paths corresponding to the plurality of different C2C protocols, wherein the de-mux is configured to select only one of the data paths as an output during runtime; and the mux coupled to the data paths as inputs and configured to and select between one of the data paths to output to the first IC die.
16. The system of claim 13, wherein the adaptive C2C interface further comprises: options circuitry disposed along the data paths and between the de-mux and the mux, wherein the options circuitry permits the adaptive C2C interface to customize the plurality of different C2C protocols.
17. A system, comprising: a chiplet comprising a first adaptive C2C interface comprising circuitry for supporting a plurality of different C2C protocols, wherein the chiplet is configured to, during boot time, configure the first adaptive C2C interface to perform only a first C2C protocol of the plurality of different C2C protocols; and
an anchor connected to the chiplet, the anchor comprising a second adaptive C2C interface comprising [a mux and a de-mux] (i.e. as a circuitry) for supporting the plurality of different C2C protocols,
wherein the anchor is configured to, during boot time, configure the first adaptive C2C interface to perform only the first C2C protocol to communicate with the first adaptive C2C interface in the chiplet.
18. The system of claim 17, further comprising: an interposer, wherein the first and second adaptive C2C interfaces communicate with each other via the interposer.
20. The system of claim 18, further comprising: a second chiplet connected to the interposer and comprising a third adaptive C2C interface, wherein the anchor comprises a fourth adaptive C2C interface configured to communicate with the third adaptive C2C interface in the second chiplet via the interposer.
19. The system of claim 17, wherein the plurality of different C2C protocols are streaming C2C protocols.
In re Karlson, 136 USPQ 189 (ccPA 1963).
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "the semiconductor chip" on page 1, line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7-8, 10-14, 17-20 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by Tang et al. (US No. 11,216,397).
In regard to claim 1, Tang et al. disclose an integrated circuit (IC) die, comprising: an adaptive chip-to-chip (C2C) interface (item 13 or 14 of figure 3) comprising circuitry (item 15 of figure 2) for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection, wherein the semiconductor chip (item 34 of figure 3) is configured to, during boot time, configure the adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with the external IC die (as shown in Fig. 3, which is reproduced below for ease of reference and convenience, Tang discloses the interconnect circuitry 13, interconnect circuitry 15 and the interconnect circuitry 14 of FIG. 2 may form a first communicative embodiment using one or more AIB interconnect standards where more than one chiplet or communicative dies are communicatively coupled. The translation circuitry 34 may include, among other things, a transceiver adapter that may enable data transmission and reception between circuitry using different versions of data transmission protocols and/or completely different transmission protocols. See ¶ (14-17));
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and processing circuitry (item 54 of figure 3) coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die, wherein the IC die and the external IC die are components of a chip-to-chip configuration (in Tang, to perform conversions between transmission mechanisms, the translation circuitry 34 may a low-swing receiver circuitry 52, an input/output translation circuitry 54, an AIB adaptor 56 and a full-swing transmission voltage adaptor 58, among other functional blocks. The input/output translation circuitry 54 that translates the data received from the low-swing receiver circuitry 52 using the levels specified in the low swing configuration. Figure 1 show chiplet 8 and chiplet 10 are formed as chip-to-chip configuration. See ¶ (19-22)).
In regard to claims 2, 13, 20, Tang et al. disclose wherein the plurality of different C2C protocols are streaming C2C protocols (in Tang, the AIB 2.0 transmitter interface bus may transfer data at 4 Gbps using a data encoding scheme. See ¶ (20-21)).
In regard to claims 3, 14, Tang et al. disclose wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol (in Tang, the interconnect circuitry 13 may utilize another suitable transmission mechanism other than AIB 2.0. The interconnect circuitry 14 may utilize an AIB 1.0 data reception interface bus. Alternatively, the interconnect circuitry 14 may utilize another transmission mechanism other than AIB 1.0. AIB 2.0 and AIB 1.0 (or other transmission mechanisms used by the interconnect circuitries 13 and/or 14) may not be compatible for direct transmission and reception of data between the interconnection circuitries 13 and 14. See ¶ 19).
In regard to claim 7, Tang et al. disclose wherein the adaptive C2C interface is configured to receive a first data word (DW) from the external IC die and transmit a second DW to the external IC die, wherein the adaptive C2C interface is configurable, at boot time, to use a first one of the plurality of different C2C protocols to receive the first DW and use a second, different one of plurality of different C2C protocols to transmit the second DW(in Tang, the data may be adjusted to a level suitable for the input/output translation circuitry 54 that translates the data received from the low-swing receiver circuitry 52 using the levels specified in the low swing configuration. The conversion may include converting between a double data rate (DDR) data and a single data rate (SDR) data. The conversion may also include any decoding of the protocol used by the AIB 2.0 data transmission interface bus 46 and encoding the data in the protocol used for reception of data by the AIB 1.0 data reception interface bus. See ¶ 22, 24).
In regard to claim 8, Tang et al. disclose further: a second adaptive C2C interface (item 58 of figure 3) disposed on a different side of the IC die than the adaptive C2C interface (item 52 of figure 3), wherein the second adaptive C2C interface comprising circuitry (item 56 of figure 3) for supporting the plurality of different C2C protocols, wherein the IC die is configured to, during boot time, configure the second adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with a second external IC die (in Tang, the full-swing transmission voltage adaptor 58 may translate the low-swing voltage level to a full-swing (or high-swing) voltage level. Thus, the translation circuitry 34 may translate the data received from the interconnection circuitry 13 to a format recognizable by the interconnection circuitry 14 without conversion performed at the interconnection circuitry 14. The AIB adaptor 56 may be a functional block, residing within the input/output translation circuitry 54 and may account for physical differences between the interconnection mechanisms used by the interconnection circuitries 13 and 14. See ¶ 23-24).
In regard to claim 10, Tang et al. disclose a system, comprising: a first IC die (item 12 of figure 1) comprising a hardened C2C interface (item 14 of figure 1) comprising circuitry (i.e. FPGA) for supporting only a first C2C protocol; and a second IC die (item 16 of figure 1) connected to the first IC die, wherein one of the first and second IC dies is an anchor and the other is a chiplet (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Tang discloses the chiplet 8 may include Field Programmable Gate Array (FPGA) or another programmable logic die. The package 6 also includes a transceiver chiplet 10 that may be communicatively coupled through interconnect circuitry 15. The chiplet 8 may include an FPGA die 9 (or other circuitry) and an interconnect circuitry 13, among other things. See ¶ 10-12),
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wherein the second IC die comprising an adaptive C2C interface (item 52 of figure 3) comprising circuitry (item 54 of figure 3) for supporting a plurality of different C2C protocols, wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform only the first C2C protocol to communicate with the hardened C2C interface in the first IC die (in Tang, the interconnect circuitry 13, interconnect circuitry 15 and the interconnect circuitry 14 of FIG. 2 may form a first communicative embodiment using one or more AIB interconnect standards where more than one chiplet or communicative dies are communicatively coupled. The translation circuitry 34 may include, among other things, a transceiver adapter that may enable data transmission and reception between circuitry using different versions of data transmission protocols and/or completely different transmission protocols. See ¶ (14-17)).
In regard to claim 11, Tang et al. disclose further: an interposer (item 16 of figure 1), wherein the hardened C2C interface and the adaptive C2C interface communicate with each other via the interposer (in Tang, the interconnect circuitry 14 may include an AIB. The interconnect circuitry 15 may be implemented through an interposer medium 16, such as a silicon interposer medium. The interconnect circuitry 14 may include an Embedded Multi-die Interconnect Bridge (EMIB) 17 or other suitable packaging circuitry that is embedded into a substrate 18 as part of the interconnect circuitry 14. See Figure 1, ¶ 10).
In regard to claim 12, Tang et al. disclose further: a third IC die (item 8 of figure 1) connected to the interposer (item 16 of figure 1) and comprising a second hardened C2C interface (item 13 of figure 1) comprising circuitry for supporting only the first C2C protocol. wherein the second IC die comprises a second adaptive C2C interface comprising circuitry for supporting the plurality of different C2C protocols, wherein the first IC die is configured to, during boot time, configure the second adaptive C2C interface to perform only the first C2C protocol to communicate with the second hardened C2C interface in the third IC die via the interposer (in Tang, the protocols in the chiplets 8 and 10 may include adding translation circuitry 34 to the interposer medium 16. Thus, the interposer medium 16, via the translation circuitry 34, may convert the different parameters of the protocols when data is passed between the chiplets 8 and 10. See figure 1 and 3, ¶ 17-23).
In regard to claim 17, Tang et al. disclose a system, comprising: a chiplet (item 10 of figure 1) comprising a first adaptive C2C interface (item 14 of figure 1) comprising circuitry for supporting a plurality of different C2C protocols, wherein the chiplet is configured to, during boot time, configure the first adaptive C2C interface to perform only a first C2C protocol of the plurality of different C2C protocols (as shown in Fig. 3, which is reproduced below for ease of reference and convenience, Tang discloses the interconnect circuitry 13, interconnect circuitry 15 and the interconnect circuitry 14 of FIG. 2 may form a first communicative embodiment using one or more AIB interconnect standards where more than one chiplet or communicative dies are communicatively coupled. The translation circuitry 34 may include, among other things, a transceiver adapter that may enable data transmission and reception between circuitry using different versions of data transmission protocols and/or completely different transmission protocols. See ¶ (14-17));
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and an anchor (i.e. interposer 16 of figure 1) connected to the chiplet, the anchor comprising a second adaptive C2C interface (item 58 of figure 3) comprising circuitry (item 56 of figure 3) for supporting the plurality of different C2C protocols, wherein the anchor is configured to, during boot time, configure the first adaptive C2C interface to perform only the first C2C protocol to communicate with the first adaptive C2C interface in the chiplet (in Tang, the interconnect circuitry 13, interconnect circuitry 15 and the interconnect circuitry 14 of FIG. 2 may form a first communicative embodiment using one or more AIB interconnect standards where more than one chiplet or communicative dies are communicatively coupled. The translation circuitry 34 may include, among other things, a transceiver adapter that may enable data transmission and reception between circuitry using different versions of data transmission protocols and/or completely different transmission protocols. See ¶ (10, 14-17)).
In regard to claim 18, Tang et al. disclose further: an interposer (item 16 of figure 1), wherein the first and second adaptive C2C interfaces communicate with each other via the interposer (in Tang, the interconnect circuitry 14 may include an AIB. The interconnect circuitry 15 may be implemented through an interposer medium 16, such as a silicon interposer medium. The interconnect circuitry 14 may include an Embedded Multi-die Interconnect Bridge (EMIB) 17 or other suitable packaging circuitry that is embedded into a substrate 18 as part of the interconnect circuitry 14. See Figre 1, ¶ 10).
In regard to claim 19, Tang et al. disclose further: a second chiplet (item 8 of figure 1) connected to the interposer and comprising a third adaptive C2C interface (item 13 of figure 3), wherein the anchor comprises a fourth adaptive C2C interface (item 58 of figure 3) configured to communicate with the third adaptive C2C interface in the second chiplet via the interposer (in Tang, the protocols in the chiplets 8 and 10 may include adding translation circuitry 34 to the interposer medium 16. Thus, the interposer medium 16, via the translation circuitry 34, may convert the different parameters of the protocols when data is passed between the chiplets 8 and 10. See figure 1 and 3, ¶ 17-23).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
Claims 4-6, 9, 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 4, 9, 15 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein the adaptive C2C interface further comprises: a de-multiplexer (de-mux) comprising outputs coupled to data paths corresponding to the plurality of different C2C protocols, wherein the de-mux is configured to select only one of the data paths as an output during runtime; and a mux coupled to the data paths as inputs and configured to and select between one of the data paths to output to one of the external IC die or the processing circuitry (claims 4, 15);
wherein the circuitry in the adaptive C2C interface corresponding to one of the plurality of different C2C protocols that was not selected during boot time is not used during runtime, wherein the IC die is one of an anchor or a chiplet in the chip-to-chip configuration (claim 9).
Conclusion
All claims are rejected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Vanesko et al. (US Pub No. 2023/0067771) disclose a tile-based result buffering in memory-computer systems.
Tummala et al. (US No. 11,537,543) disclose a technique for handling protocol conversion.
McLellan (US Pub No. 2018/0102338) discloses a circuit board with bridge chiplets.
Jackson et al. (US Pub No. 2018/0307863) disclose a removable chiplet for hardware trusted platform module.
Das Sharma (US Pub No. 2020/0226018) discloses a multi-protocol support on-common physical layer.
Das Sharma et al. (US Pub No. 2021/0399982) disclose a technique to support multiple protocols between computer system interconnects.
Subbareddy et al. (US Pub No. 2022/0102281) discloses a selective use of different advanced interface bus with electronic chips.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175