Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: RCE accompanied by the amendment filed on August 5, 2026 responding to the Final Office Action mailed on June 3, 2026. The amendment filed on August 5, 2026 has been entered.
This application has been examined. Claims 21-39 are pending. Claims 1-20 are cancelling.
Double Patenting
3. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claims 21, 22, 30, 31, 34, 35 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, 1, 1, 2, 10, 6 in Patent No. 12,066,969 respectively. Although the conflicting claims are not identical, they are not patentably distinct from each other because the pending claims are either verbatim or broader than the patented claims thus breadth alone does not confer patentable distinction under ODP when the broader claims cover the same inventive concept.
Regarding claim 21, claim 1 of the '969 Patent recites an integrated circuit (IC) die comprising an adaptive chip-to-chip (C2C) interface comprising a mux and a de-mux (i.e., circuitry) for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection, wherein, during boot time, the adaptive C2C interface is configured to perform only one of the plurality of different C2C protocols to communicate with the external IC die, and processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die, wherein the IC die and the external IC die are components of a chip-to-chip configuration - i.e., every limitation of instant claim 21 apart from the "different data path"/de-mux-outputs limitation added by the present amendment. While that added limitation was cancelled from claim 1 during prosecution of the '969 Patent (as reflected in the file history), it was not abandoned from the patent as a whole: claim 10 of the '969 Patent, directed to a system employing the identical adaptive C2C interface architecture disclosed in the same specification, expressly recites "an adaptive C2C interface comprising a mux and a de-mux for supporting a plurality of different C2C protocols, wherein each of the plurality of different C2C protocols corresponds to a different data path of a plurality of data paths." It would have been obvious to a person of ordinary skill in the art to incorporate this already-patented data-path/de-mux limitation into the adaptive C2C interface of claim 1, as both claims are drawn to the same adaptive C2C interface structure disclosed in a single, common specification, and no unexpected result or patentable distinction is apparent from adding a feature the patentee has already claimed elsewhere in the same patent. Claim 21 is therefore not patentably distinct from claim 1 in view of claim 10 of the '969 Patent.
Regarding claim 22-33, claims 22-33 depend from claim 21 and add limitations (a mux coupled to the data paths and the de-mux; the de-mux routing data to the data path corresponding to the protocol configured during boot time; the de-mux selecting only one data path as output during runtime; the mux selecting a data path for output to the external IC die or processing circuitry; options circuitry between the mux and de-mux; coarse and fine registers; streaming protocols; a standard-defined protocol and a proprietary protocol; and unused circuitry for the non-selected protocol) that are disclosed in claims 1, 2, and 10 of the '969 Patent and/or the common specification, substantially for the reasons given in the claim chart and analysis of the Final Office Action mailed June 3, 2026 (pages 3-9), which findings are incorporated herein by reference and are unaffected by the present amendment. Claims 22-33 are accordingly not patentably distinct from claims 1, 2, and 10 of the '969 Patent, taken alone or in combination.
Regarding claim 34, claim 10 of the '969 Patent recites, in haec verba: "a first IC die comprising a hardened C2C interface comprising circuitry for supporting only a first C2C protocol; and a second IC die connected to the first IC die, wherein one of the first and second IC dies is an anchor and the other is a chiplet, wherein the second IC die comprising an adaptive C2C interface comprising a mux and a de-mux for supporting a plurality of different C2C protocols, wherein each of the plurality of different C2C protocols corresponds to a different data path of a plurality of data paths and wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform only the first C2C protocol to communicate with the hardened C2C interface in the first IC die." This language is substantively identical to, and at least as broad as, instant claim 34 as amended, including the newly added "different data path" and "de-mux having outputs coupled to data paths" limitations, which the amendment filed July 28, 2026 represented as distinguishing over the cited art. Because claim 10 of the '969 Patent already recites these very limitations verbatim in the context of the same two-die system, claim 34 is anticipated by, or at minimum not patentably distinct from, claim 10 of the '969 Patent.
Regarding claim 35-39, claims 35-39 depend from claim 34 and recite limitations (unused circuitry for the non-selected protocol; an interposer; a mux and de-mux; the de-mux routing/selecting a single data path during runtime and the mux selecting that data path for output; options circuitry; coarse and fine registers) that are disclosed in claim 6 of the '969 Patent (as to claim 35, per the analysis at page 8 of the Final Office Action mailed June 3, 2026, incorporated herein by reference) and in claim 10 and the common specification of the '969 Patent (as to claims 36-39), and are accordingly not patentably distinct therefrom.
Present Application
Pat No. 12,066,969
21. A integrated circuit (IC) die, comprising: an adaptive chip-to-chip (C2C) interface comprising circuitry for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection,
wherein, during boot time, configure the adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with the external IC die; and
processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die, wherein the IC die and the external IC die are components of a chip-to-chip configuration.
22. (New) The IC die of claim 21, wherein the circuitry supporting the plurality of different C2C protocols includes at least a mux and a de-mux.
23. (New) The IC die of claim 22, wherein the de-mux comprises outputs coupled to data paths corresponding to the plurality of different C2C protocols.
24. (New) The IC die of claim 23, wherein the de-mux is configured to select only one of the data paths as an output during runtime.
25. (New) The IC die of claim 24, wherein the mux is coupled to the data paths as inputs and configured to select between one of the data paths to output to one of the external IC die or the processing circuitry.
26. (New) The IC die of claim 22, wherein the adaptive C2C interface further comprises options circuitry disposed between the mux and the de-mux.
27. (New) The IC die of claim 26, wherein the options circuitry permits the adaptive C2C interface to customize the plurality of different C2C protocols.
28. (New) The IC die of claim 27, wherein the adaptive C2C interface further comprises coarse registers storing coarse grain configurations to control the mux and the de-mux.
29. (New) The IC die of claim 28, wherein the adaptive C2C interface further comprises fine registers storing fine grain configurations to control the options circuitry to customize the one of the plurality of different C2C protocols.
30. (New) The IC die of claim 21, wherein each of the plurality of different C2C protocols corresponds to a different data path of a plurality of data paths.
31. (New) The IC die of claim 21, wherein the plurality of different C2C protocols are streaming C2C protocols.
32. (New) The IC die of claim 22, wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol.
33. (New) The IC die of claim 22, wherein the circuitry corresponding to one of the plurality of different C2C protocols not selected during boot time remains unused during runtime.
34. (New) A system, comprising:
a first IC die comprising a hardened C2C interface comprising first circuitry supporting a first C2C protocol; and
a second IC die connected to the first IC die, wherein the second IC die includes an adaptive C2C interface comprising second circuitry supporting a plurality of different C2C protocols, wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform the first C2C protocol to communicate with the hardened C2C interface in the first IC die.
35. (New) The system of claim 34, wherein the second circuitry corresponding to one of the plurality of different C2C protocols not selected during boot time remains unused during runtime.
36. (New) The system of claim 34, further comprising an interposer, wherein the hardened C2C interface and the adaptive C2C interface communicate with each other via the interposer.
37. (New) The system of claim 34, wherein the second circuitry supporting the plurality of different C2C protocols includes at least a mux and a de-mux.
38. (New) The system of claim 37
wherein the de-mux comprises outputs coupled to data paths corresponding to the plurality of different C2C protocols and wherein the de-mux is configured to select only one of the data paths as an output during runtime; and
wherein the mux is coupled to the data paths as inputs and configured to select between one of the data paths to output to the second IC die.
39. (New) The system of claim 38, wherein the adaptive C2C interface further comprises:
options circuitry disposed between the mux and the de-mux;
coarse registers storing coarse grain configurations to control the mux and the de-mux; and
1. An integrated circuit (IC) die, comprising: an adaptive chip-to-chip (C2C) interface comprising a [mux and a de-mux] (i.e. as circuitry) for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection,
wherein, during boot time, the adaptive C2C interface is configured to perform only one of the plurality of different C2C protocols that is in common with the external IC die to communicate with the external IC die; and
processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die, wherein the IC die and the external IC die are components of a chip-to-chip configuration.
Claim 1
Claim 1
2. The IC die of claim 1, wherein the plurality of different C2C protocols are streaming C2C protocols.
10. A system, comprising: a first IC die comprising a hardened C2C interface comprising circuitry for supporting only a first C2C protocol; and
a second IC die connected to the first IC die, wherein one of the first and second IC dies is an anchor and the other is a chiplet, wherein the second IC die comprising an adaptive C2C interface comprising a mux and a de-mux for supporting a plurality of different C2C protocols, wherein each of the plurality of different C2C protocols corresponds to a different data path of a plurality of data paths and wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform only the first C2C protocol to communicate with the hardened C2C interface in the first IC die.
Claim 6
In re Karlson, 136 USPQ 189 (ccPA 1963).
NO Double Patenting rejection
Claim 40 is a newly presented independent system claim reciting a chiplet having a first adaptive C2C interface (mux/de-mux, boot-time selection of a first C2C protocol) and an anchor having a second adaptive C2C interface that is likewise configured, during boot time, to perform the same first C2C protocol so as to communicate with the chiplet. Unlike claim 10 of the '969 Patent - which recites one hardened (single-protocol) interface and one adaptive (multi-protocol) interface - claim 40 recites an adaptive interface on both sides of the C2C connection. On the present record the Office has not identified a claim of the '969 Patent reciting two adaptive, mux/de-mux-based C2C interfaces configured to converge on a common protocol at boot time. No double patenting rejection of claim 40 is made at this time on the present record; however, Applicant and the undersigned should reassess this issue if the '969 Patent family includes any allowed or copending claims directed to a bilateral adaptive-adaptive C2C configuration, as such claims, if present, would likely also anticipate or render obvious claim 40.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 21-33, 40 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by Spry et al. (“Spry”) (US No. 9,734,116).
In regard to claim 1, Spry discloses an integrated circuit (IC) die, comprising:
an adaptive chip-to-chip (C2C) interface comprising circuitry for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection (as shown in Fig. 7, which is reproduced below for ease of reference and convenience, Spry discloses Claim 1: A first integrated circuit (IC) chip comprising… that IC chip = IC die; same preamble in substance. Claim 1: The IC chip comprises “a first physical layer and a second physical layer' each corresponding to a different C2C protocol stack (single-ended OPIO protocol vs. PCIe differential protocol). MUX logic (col. 10:62-11:30) is “operable to select a particular one (e.g. only one) of the first set of circuitry and the second set of circuitry” thus this is circuitry supporting a plurality of different C2C protocols. The OPIO and PCIe stacks each define a different data path between dies),
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wherein each of the plurality of different C2C protocols corresponds to a different data path (in Spry, the first and second protocol stacks are implemented through separate circuit paths - link layer 620 to single-ended Phy 652, and link layer 620 to PCIe Phy 654, respectively - such that each protocol's data necessarily traverses a data path dedicated to that protocol's associated physical layer; col. 10:62-11:30, Fig. 7), and wherein the circuitry comprises a de-mux having outputs coupled to data paths corresponding to the plurality of different C2C protocols (in Spry, configuration logic 650 “may include any of a variety of switches, fuses or other such circuitry which is operable to select and configure paths for data, control, power, clock and/or other signals to be variously exchanged between link layer 620 and one (i.e. only one) of single-ended Phy 652 and PCIe Phy 654,” col. 9:12-10:45, Fig. 6; because configuration logic 650 is coupled, via such switches, to both single-ended Phy 652 and PCIe Phy 654 - i.e., to both protocol-specific data paths - and selectively directs data to whichever data path is configured, it discloses a de-mux having outputs coupled to data paths corresponding to the plurality of different C2C protocols),
wherein, during boot time, configure the adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with the external IC die (in Spry, Claim 1: configuration circuitry “provides for configuration of a first protocol stack or “an alternative configuration of a second protocol stack”. Claim 2: a system comprises a packaged device including the first IC chip, an interconnect and a second IC chip, wherein operation of the first transaction layer, the first link layer and the first physical layer as the first protocol stack is enabled” thus protocol stack is selected/configured before runtime communication, i.e., at initialization/boot time. Col. 10:62-11:30: 'MUX logic…is operable to select a particular one…only one' of the circuitry sets during initialization); and
processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die (in Spry, Claim 7: “…the first IC chip further comprising a plurality of processor cores and a bus fabric coupling the plurality of cores to the first transaction layer”. The transaction/link/physical layers form the adaptive C2C interface; processor cores = processing circuitry; “bus fabric coupling the cores to the transaction layer” = coupled to the adaptive C2C interface. During runtime the protocol stack selected at initialization is used by the processor cores to communicate with the second IC chip), wherein the IC die and the external IC die are components of a chip-to-chip configuration (in Spry, Claim 2: “a system comprises a packaged device including the first IC chip, an interconnect and a second IC chip” that two IC chips (dies) connected chip-to-chip. Claim 6: “…the system comprises a first packaged device including the first IC chip and a second packaged device including a second IC chip” that explicit C2C configuration).
In regard to claim 22, Spry discloses wherein the circuitry supporting the plurality of different C2C protocols includes at least a mux coupled to the data paths and the de-mux (in Spry, MUX logic 770 is coupled to configuration logic and to the protocol-specific data paths via signal lines 780, and operates together with configuration logic 650 to select and forward data associated with the configured protocol; col. 10:62-11:30, Fig. 7).
In regard to claim 23, Spry discloses wherein the de-mux routes data to the data path corresponding to the one of the plurality of different C2C protocols configured during boot time (in Spry, once configuration logic 650 is configured, at initialization, for “a first protocol stack” or, alternatively, “a second protocol stack” (claim 1), it couples data exclusively to the data path - single-ended Phy 652 or PCIe Phy 654 - associated with the protocol so configured; col. 9:12-10:45).
In regard to claim 24, Spry discloses wherein the de-mux is configured to select only one of the data paths as an output during runtime (in Spry, Col. 10:62-11:30: MUX logic “is operable to select a particular one (e.g. only one) of the first set of circuitry and the second set of circuitry”. Once configured, only one data path is active during runtime. “The other unselected set of circuitry may be excluded…by being disabled”).
In regard to claim 25, Spry discloses wherein the mux is coupled to the data paths as inputs and configured to select one of the data paths to output to one of the external IC die or the processing circuitry (in Spry, Col. 10:62-11:30: MUX logic 770 is “coupled to configuration logic which is operable to select a particular one…of the first set of circuitry and the second set of circuitry. MUX logic 770 may forward signal[s] from the selected set of circuitry to the one or more signal lines [780]” thus signal lines 780 couple to the external IC chip (second die) or the processing cores. The mux takes the data paths (OPIO path vs. PCIe path) as inputs and outputs the selected one).
In regard to claim 26, Spry discloses wherein the adaptive C2C interface further comprises options circuitry disposed between the mux and the de-mux (in Spry, Col. 10:62-11:30 + Fig. 7: “Glue logic 720' is disposed in each protocol data path between the incoming data (de-mux side) and the outgoing selection (mux side). Glue logic provides protocol-specific adaptation between the protocol paths and the mux/de-mux which directly analogous to 'options circuitry between mux and de-mux”).
In regard to claim 27, Spry discloses wherein the options circuitry permits the adaptive C2C interface to customize the plurality of different C2C protocols (in Spry, Col. 10:62-11:30: Glue logic 720 is specifically designed to interface and customize operation of each protocol stack (OPIO vs. PCIe). “Glue logic 730 may include…link layer circuitry and/or physical layer circuitry which facilitates single-ended communications via AFE 730” (i.e., options/glue circuitry customizes how each protocol operates within the interface)).
In regard to claim 28, Spry discloses wherein the adaptive C2C interface further comprises coarse registers storing coarse grain configurations to control the mux and the de-mux (in Spry, col. 9:12-10:45 + Fig. 6: Configuration circuitry includes registers that store protocol stack selection. Claim 1: “configuration circuitry to select from among: a first configuration…and a second configuration…” thus these selection registers are coarse-grain controls directing the MUX logic to choose one entire protocol path over another. Spry does not use the label “coarse,” but the function is identical: a register-stored selection that steers the mux/de-mux to one data path).
In regard to claim 29, Spry discloses wherein the adaptive C2C interface further comprises fine registers storing fine grain configurations to control the options circuitry to customize the C2C protocol configured during boot time (in Spry, link-layer configuration registers controlling sub-features of the selected protocol stack, e.g., independence from ACK messages (claim 3), independence from CRC (claim 4), and simplified link training (claim 5); col. 9:12-10:45).
In regard to claim 30, Spry discloses wherein the adaptive chip-to-chip interface selects the one of the plurality of different C2C protocols before initiating communication with the external IC die (in Spry, protocol stack selection and configuration occurs during initialization/boot time, prior to runtime communication; Spry, claim 1; col. 10:62-11:30).
In regard to claim 31, Spry discloses wherein the plurality of different C2C protocols are streaming C2C protocols (in Spry, col. 4:50-5:32: The OPIO protocol and PCIe protocol are both chip-to-chip streaming protocols used for high-bandwidth data streaming between IC dies on an interconnect. “OPIO architecture…to run at high bandwidth” for streaming data between dies. PCIe is a standard high-speed streaming serial protocol. Both are streaming C2C protocols in the chip-to-chip context).
In regard to claim 32, Spry discloses wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol (in Spry, Spec col. 2:38-60: Second protocol stack uses PCIe™ specification - a standard-defined protocol (IEEE/PCI-SIG standard). First protocol stack uses OPIO (Intel proprietary on-package I/O) that a proprietary protocol. Thus Spry expressly discloses one standard-defined (PCIe) and one proprietary (OPIO) C2C protocol in the same adaptive interface).
In regard to claim 33, Spry discloses wherein the circuitry corresponding to one of the plurality of different C2C protocols not selected during boot time remains unused during runtime (in Spry, Col. 10:62-11:30: “the other unselected set of circuitry may be excluded from a protocol stack by being disabled (e.g. where Glue logic 720 and/or LP AFE 730 (or alternatively, Phy logic 740 and/or AFE 760)) is fusedly, switchedly or otherwise disconnected from one or more supply voltage lines”. Disabled/disconnected = unused during runtime. Expressly disclosed).
Claim 40 (system) recites the same operative limitations as device claim 21. The change in claim format from system to device does not confer patentability where the underlying operations are identical to those taught by the applied references. See MPEP § 2114; In re Bernhart, 417 F.2d 1395 (CCPA 1969). The element-by-element mapping set forth for claim 21 applies with equal force to claim 40.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 34-39 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Spry in view of Subramaniam et al. (“Subramaniam”) (US No. 11,100,028).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Spry and Subramaniam references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 34, Spry discloses a system substantially as claimed, comprising:
a first IC die comprising a hardened C2C interface comprising first circuitry supporting a first C2C protocol (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Spry discloses Claim 2 + col. 5:46-6:40: “a system comprises a packaged device including the first IC chip, an interconnect and a second IC chip, wherein operation of the first…protocol stack is enabled”);
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wherein each of the plurality of different C2C protocols corresponds to a different data path, and wherein the second circuitry comprises a de-mux having outputs coupled to data paths corresponding to the plurality of different C2C protocols, and wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform the first C2C protocol to communicate with the first IC die, all for the same reasons given above with respect to claim 21 (in Spry, configuration logic 650 / MUX logic 770, col. 9:12-11:30). But Spry does not explicitly disclose the use of “harden”. In the same field of endeavor, Subramaniam discloses multiple ports configured to interface with respective chiplets, wherein at least two…ports have respective different types of [PHY] interfaces. The bridge chiplet is the adaptive die; the chiplets it connects to are hardened/fixed-PHY dies (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Subramaniam discloses Claim 1 + col. 3:59-4:23: “multiple ports configured to interface with respective chiplets, wherein at least two…ports have respective different types of [PHY] interfaces.” The bridge chiplet is the adaptive die; the chiplets it connects to are hardened/fixed-PHY dies. Claim 6: “in response to determining that the first chiplet and the second chiplet support a same communication protocol, [data is] route[d]…without converting” thus the adaptive bridge configures itself at boot time to match the fixed-protocol die).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Subramaniam with the teaching of Spry to enable interoperability between a cost-optimized hardened interface on one die and a flexible adaptive interface on another die in a multi-die system, as such a combination amounts to no more than the application of a known technique (a hardened, single-protocol chiplet interface, as taught by Subramaniam) to a known device (Spry's adaptive, multi-protocol IC die) ready for improvement to yield the predictable result of reduced silicon area and power on the fixed-protocol die while retaining compatibility and flexibility when integrating dies from different sources or process nodes. See MPEP 2143(A); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
In regard to claim 35, Spry discloses wherein the second circuitry corresponding to one of the plurality of different C2C protocols not selected during boot time remains unused during runtime (in Spry, Col. 10:62-11:30: “the other unselected set of circuitry may be excluded from a protocol stack by being disabled (e.g. where Glue logic 720 and/or LP AFE 730 (or alternatively, Phy logic 740 and/or AFE 760)) is fusedly, switchedly or otherwise disconnected from one or more supply voltage lines”. Disabled/disconnected = unused during runtime. Expressly disclosed).
In regard to claim 36, Subramaniam discloses further an interposer, wherein the hardened C2C interface and the adaptive C2C interface communicate with each other via the interposer (in Subramaniam, Claim 2: PHY type Advanced Interface Bus (AIB), AIB is implemented via silicon interposer (EMIB) in standard practice). A POSITA would understand that placing the adaptive bridge and hardened chiplets on a common interposer is the standard chiplet integration technique, making an interposer obvious for the system of claim 34).
In regard to claim 37, Spry discloses wherein the second circuitry supporting the plurality of different C2C protocols includes at least a mux coupled to the data paths and the de-mux, for the reasons given above with respect to claim 22 (MUX logic 770 and configuration logic 650, col. 10:62-11:30).
In regard to claim 38, Spry discloses wherein the de-mux is configured to route data to the data paths corresponding to the first C2C protocol configured during boot time and to select only one of the data paths corresponding to the first C2C protocol as an output during runtime, for the reasons given above with respect to claims 23 and 24; and wherein the mux is coupled to the data paths as inputs and configured to select the data path corresponding to the first C2C protocol for output to the second IC die, for the reasons given above with respect to claim 25 (see col. 9:12-11:30).
In regard to claim 39, Spry discloses wherein the adaptive C2C interface further comprises options circuitry disposed between the mux and the de-mux; coarse registers storing coarse grain configurations to control the mux and the de-mux; and fine registers storing fine grain configurations to control the options circuitry to customize the first C2C protocol configured during boot time, for the reasons given above with respect to claims 26-29 (see glue logic 720/730 and associated configuration/link-layer registers, col. 9:12-11:30).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Closest issues/potential allowable subject matter: the clearest path to allowance remains a limitation genuinely absent from Spry's disclosure - for example, a de-mux that exposes simultaneous, concurrently-active outputs to more than one protocol-specific data path (rather than Spry's mutually exclusive, one-of-two stack selection with the unselected stack disabled), or fine-grain register control of link-layer sub-features tied to a specific data path structure not present in Spry's link-layer configuration registers (col. 9:12-col. 10:45). Applicant is encouraged to consider claim language directed to the specification's disclosure of concurrent multi-protocol operation, if supported, as a basis for allowable subject matter.
Response to Amendment
8. Applicant's amendment and remarks filed July 28, 2026, with respect to the rejection of claims 32 and 39 under 35 U.S.C. 112(b), have been fully considered and are persuasive. Claim 32 has been amended to depend from claim 31 (rather than claim 22), and claim 31 properly introduces "streaming C2C protocols," thereby providing antecedent basis for the "streaming C2C protocol" language subsequently recited in claim 32. Claim 39 has been amended to complete the sentence that previously terminated after "coarse registers storing coarse grain configurations to control the mux and the de-mux; and" by adding the missing "fine registers" clause, so that the claim now particularly points out and distinctly claims the subject matter regarded as the invention. Accordingly, the rejections of claims 32 and 39 under 35 U.S.C. 112(b) set forth in the Final Office Action mailed June 3, 2026 are hereby WITHDRAWN.
9. Applicant's amendment and remarks filed July 28, 2026, with respect to (i) the rejection of claims 21, 22, 30, 31, 34, and 35 under the judicially created doctrine of obviousness-type double patenting, (ii) the rejection of claims 21-33 under 35 U.S.C. 102(a)(2) as anticipated by Spry, and (iii) the rejection of claims 34-39 under 35 U.S.C. 103 as unpatentable over Spry in view of Subramaniam, have been fully considered but are not persuasive, for the reasons given above. The amendment to independent claims 21, 34, and 40 does not place the claims in condition for allowance; the rejections are maintained and are reapplied above to the claims as currently amended, and are extended to newly amended claims 22, 23, 25, 29, 37, 38, and 39 and to claim 40.
Conclusion
10. Claims 21-40 are rejected. Claims 1-20 are cancelled.
This action is a first Office Action following entry of a Request for Continued Examination and reapplies art and reasoning of record, revised only to address claims as amended and to correct the citation noted above; accordingly, THIS ACTION IS MADE FINAL. See MPEP 706.07(b), 706.07(h). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for response to this final action is set to expire THREE MONTHS from the date of this action. In the event a first response is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event will the statutory period for response expire later than SIX MONTHS from the date of this final action.
11. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Das Sharma et al., US 2022/0327084, teach a die-to-die interconnect protocol layer disclosing ARB/MUX logic and adapter blocks mapping multiple protocols (PCIe, CXL, raw) onto a common link; potential secondary reference if the de-mux/data-path mapping to Spry is contested.
Seshan et al., US 2022/0327276, teach a lane repair and lane reversal for die-to-die (D2D) interconnects; relevant to interposer/data-path routing but not separately relied upon.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
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