Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: amendment filed on May 14, 2026.
This application has been examined. Claims 21-39 are pending. Claims 1-20 are cancelling.
Double Patenting
3. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claims 21, 22, 30, 31, 34, 35 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1, 1, 1, 2, 10, 6 in Patent No. 12,066,969 respectively. Although the conflicting claims are not identical, they are not patentably distinct from each other because the pending claims are either verbatim or broader than the patented claims thus breadth alone does not confer patentable distinction under ODP when the broader claims cover the same inventive concept.
Present Application
Pat No. 12,066,969
21. A integrated circuit (IC) die, comprising: an adaptive chip-to-chip (C2C) interface comprising circuitry for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection,
wherein, during boot time, configure the adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with the external IC die; and
processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die, wherein the IC die and the external IC die are components of a chip-to-chip configuration.
22. (New) The IC die of claim 21, wherein the circuitry supporting the plurality of different C2C protocols includes at least a mux and a de-mux.
23. (New) The IC die of claim 22, wherein the de-mux comprises outputs coupled to data paths corresponding to the plurality of different C2C protocols.
24. (New) The IC die of claim 23, wherein the de-mux is configured to select only one of the data paths as an output during runtime.
25. (New) The IC die of claim 24, wherein the mux is coupled to the data paths as inputs and configured to select between one of the data paths to output to one of the external IC die or the processing circuitry.
26. (New) The IC die of claim 22, wherein the adaptive C2C interface further comprises options circuitry disposed between the mux and the de-mux.
27. (New) The IC die of claim 26, wherein the options circuitry permits the adaptive C2C interface to customize the plurality of different C2C protocols.
28. (New) The IC die of claim 27, wherein the adaptive C2C interface further comprises coarse registers storing coarse grain configurations to control the mux and the de-mux.
29. (New) The IC die of claim 28, wherein the adaptive C2C interface further comprises fine registers storing fine grain configurations to control the options circuitry to customize the one of the plurality of different C2C protocols.
30. (New) The IC die of claim 21, wherein each of the plurality of different C2C protocols corresponds to a different data path of a plurality of data paths.
31. (New) The IC die of claim 21, wherein the plurality of different C2C protocols are streaming C2C protocols.
32. (New) The IC die of claim 22, wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol.
33. (New) The IC die of claim 22, wherein the circuitry corresponding to one of the plurality of different C2C protocols not selected during boot time remains unused during runtime.
34. (New) A system, comprising:
a first IC die comprising a hardened C2C interface comprising first circuitry supporting a first C2C protocol; and
a second IC die connected to the first IC die, wherein the second IC die includes an adaptive C2C interface comprising second circuitry supporting a plurality of different C2C protocols, wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform the first C2C protocol to communicate with the hardened C2C interface in the first IC die.
35. (New) The system of claim 34, wherein the second circuitry corresponding to one of the plurality of different C2C protocols not selected during boot time remains unused during runtime.
36. (New) The system of claim 34, further comprising an interposer, wherein the hardened C2C interface and the adaptive C2C interface communicate with each other via the interposer.
37. (New) The system of claim 34, wherein the second circuitry supporting the plurality of different C2C protocols includes at least a mux and a de-mux.
38. (New) The system of claim 37
wherein the de-mux comprises outputs coupled to data paths corresponding to the plurality of different C2C protocols and wherein the de-mux is configured to select only one of the data paths as an output during runtime; and
wherein the mux is coupled to the data paths as inputs and configured to select between one of the data paths to output to the second IC die.
39. (New) The system of claim 38, wherein the adaptive C2C interface further comprises:
options circuitry disposed between the mux and the de-mux;
coarse registers storing coarse grain configurations to control the mux and the de-mux; and
1. An integrated circuit (IC) die, comprising: an adaptive chip-to-chip (C2C) interface comprising a [mux and a de-mux] (i.e. as circuitry) for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection,
wherein, during boot time, the adaptive C2C interface is configured to perform only one of the plurality of different C2C protocols that is in common with the external IC die to communicate with the external IC die; and
processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die, wherein the IC die and the external IC die are components of a chip-to-chip configuration.
Claim 1
Claim 1
2. The IC die of claim 1, wherein the plurality of different C2C protocols are streaming C2C protocols.
10. A system, comprising: a first IC die comprising a hardened C2C interface comprising circuitry for supporting only a first C2C protocol; and
a second IC die connected to the first IC die, wherein one of the first and second IC dies is an anchor and the other is a chiplet, wherein the second IC die comprising an adaptive C2C interface comprising a mux and a de-mux for supporting a plurality of different C2C protocols, wherein each of the plurality of different C2C protocols corresponds to a different data path of a plurality of data paths and wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform only the first C2C protocol to communicate with the hardened C2C interface in the first IC die.
Claim 6
In re Karlson, 136 USPQ 189 (ccPA 1963).
Claim Rejections - 35 USC § 112
The following is a quotation of the second paragraph of 35 U.S.C. 112:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 32 depends from claim 22 and recites “a first streaming C2C protocol of the streaming C2C protocols”. However, 'streaming C2C protocols' is not introduced in claim 21 or 22, however the term first appears in claim 31.
Claim 39 terminates after “coarse registers storing coarse grain configurations to control the mux and the de-mux; and” thus the claim is unfinished mid-sentence. The fine registers element (and any other intended limitations) are absent. A claim that does not conclude with a complete sentence reciting the intended limitations fails to particularly point out the metes and bounds of the invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 21-33 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by Spry et al. (“Spry”) (US No. 9,734,116).
In regard to claim 1, Spry discloses an integrated circuit (IC) die, comprising:
an adaptive chip-to-chip (C2C) interface comprising circuitry for supporting a plurality of different C2C protocols to communicate with an external IC die using a C2C connection (as shown in Fig. 7, which is reproduced below for ease of reference and convenience, Spry discloses Claim 1: A first integrated circuit (IC) chip comprising… that IC chip = IC die; same preamble in substance. Claim 1: The IC chip comprises “a first physical layer and a second physical layer' each corresponding to a different C2C protocol stack (single-ended OPIO protocol vs. PCIe differential protocol). MUX logic (col. 10:62 thru col. 11:30) is “operable to select a particular one (e.g. only one) of the first set of circuitry and the second set of circuitry” thus this is circuitry supporting a plurality of different C2C protocols. The OPIO and PCIe stacks each define a different data path between dies),
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wherein the semiconductor chip is configured to, during boot time, configure the adaptive C2C interface to perform only one of the plurality of different C2C protocols to communicate with the external IC die (in Spry, Claim 1: configuration circuitry “provides for configuration of a first protocol stack or “an alternative configuration of a second protocol stack”. Claim 2: a system comprises a packaged device including the first IC chip, an interconnect and a second IC chip, wherein operation of the first transaction layer, the first link layer and the first physical layer as the first protocol stack is enabled” thus protocol stack is selected/configured before runtime communication, i.e., at initialization/boot time. Col. 10:62 thru col. 11:30: 'MUX logic…is operable to select a particular one…only one' of the circuitry sets during initialization);
and processing circuitry coupled to the adaptive C2C interface and configured, during runtime, to use the adaptive C2C interface to communicate with the external IC die (in Spry, Claim 7: “…the first IC chip further comprising a plurality of processor cores and a bus fabric coupling the plurality of cores to the first transaction layer”. The transaction/link/physical layers form the adaptive C2C interface; processor cores = processing circuitry; “bus fabric coupling the cores to the transaction layer” = coupled to the adaptive C2C interface. During runtime the protocol stack selected at initialization is used by the processor cores to communicate with the second IC chip), wherein the IC die and the external IC die are components of a chip-to-chip configuration (in Spry, Claim 2: “a system comprises a packaged device including the first IC chip, an interconnect and a second IC chip” that two IC chips (dies) connected chip-to-chip. Claim 6: “…the system comprises a first packaged device including the first IC chip and a second packaged device including a second IC chip” that explicit C2C configuration).
In regard to claim 22, Spry discloses wherein the circuitry supporting the plurality of different C2C protocols includes at least a mux and a de-mux (in Spry, Col. 10:62 thru col. 11:305: “MUX logic 770…is operable to select a particular one (e.g. only one) of the first set of circuitry and the second set of circuitry. MUX logic 770 may forward signal[s] from the selected set of circuitry to the one or more signal lines”. MUX logic = mux; the unselected path circuitry that demultiplexes/directs incoming data to the selected protocol path = de-mux function. Spry expressly recites MUX logic performing selection among protocol data paths.
In regard to claim 23, Spry discloses wherein the de-mux comprises outputs coupled to data paths corresponding to the plurality of different C2C protocols (in Spry, Spec col. 6: The first physical layer (OPIO) and second physical layer (PCIe) each define a separate data path. The configuration/selection circuitry (de-mux) has outputs coupled to each respective protocol data path. When one protocol is selected, the de-mux output routes data to that protocol's data path).
In regard to claim 24, Spry discloses wherein the de-mux is configured to select only one of the data paths as an output during runtime (in Spry, Col. 10:62 thru col. 11:30: MUX logic “is operable to select a particular one (e.g. only one) of the first set of circuitry and the second set of circuitry”. Once configured, only one data path is active during runtime. “The other unselected set of circuitry may be excluded…by being disabled”).
In regard to claim 25, Spry discloses wherein the mux is coupled to the data paths as inputs and configured to select between one of the data paths to output to one of the external IC die or the processing circuitry (in Spry, Col. 10:62 thru col. 11:30: MUX logic 770 is “coupled to configuration logic which is operable to select a particular one…of the first set of circuitry and the second set of circuitry. MUX logic 770 may forward signal[s] from the selected set of circuitry to the one or more signal lines [780]” thus signal lines 780 couple to the external IC chip (second die) or the processing cores. The mux takes the data paths (OPIO path vs. PCIe path) as inputs and outputs the selected one).
In regard to claim 26, Spry discloses wherein the adaptive C2C interface further comprises options circuitry disposed between the mux and the de-mux (in Spry, Col. 10:62 thru col. 11:30 + Fig. 7: “Glue logic 720' is disposed in each protocol data path between the incoming data (de-mux side) and the outgoing selection (mux side). Glue logic provides protocol-specific adaptation between the protocol paths and the mux/de-mux which directly analogous to 'options circuitry between mux and de-mux”).
In regard to claim 27, Spry discloses wherein the options circuitry permits the adaptive C2C interface to customize the plurality of different C2C protocols (in Spry, Col. 10:62 thru col. 11:30: Glue logic 720 is specifically designed to interface and customize operation of each protocol stack (OPIO vs. PCIe). “Glue logic 730 may include…link layer circuitry and/or physical layer circuitry which facilitates single-ended communications via AFE 730” (i.e., options/glue circuitry customizes how each protocol operates within the interface)).
In regard to claim 28, Spry discloses wherein the adaptive C2C interface further comprises coarse registers storing coarse grain configurations to control the mux and the de-mux (in Spry, col. 9:12 thru col. 10:45 + Fig. 6: Configuration circuitry includes registers that store protocol stack selection. Claim 1: “configuration circuitry to select from among: a first configuration…and a second configuration…” thus these selection registers are coarse-grain controls directing the MUX logic to choose one entire protocol path over another. Spry does not use the label “coarse,” but the function is identical: a register-stored selection that steers the mux/de-mux to one data path).
In regard to claim 29, Spry discloses wherein the adaptive C2C interface further comprises fine registers storing fine grain configurations to control the options circuitry to customize the one of the plurality of different C2C protocols (in Spry, col. 9:12 thru col. 10:45: Beyond coarse protocol-stack selection, Spry discloses fine-grained link layer configuration (Claim 3: independence from ACK messages; Claim 4: independence from CRC; Claim 5: simplified link training) thus these represent fine-grain configurations of the selected protocol stack. Link layer configuration registers that control specific sub-features of the chosen protocol = fine registers controlling options circuitry).
In regard to claim 30, Spry discloses wherein each of the plurality of different C2C protocols corresponds to a different data path of a plurality of data paths (in Spry, Col. 10:62 thru col. 11:30, Fig. 7: First protocol stack (OPIO) uses a first data path through single-ended Phy 652 and AFE 730. Second protocol stack (PCIe) uses a second data path through PCIe Phy 654 and AFE 760. Each protocol = its own distinct data path. Expressly disclosed).
In regard to claim 31, Spry discloses wherein the plurality of different C2C protocols are streaming C2C protocols (in Spry, col. 4:50 thru col. 5:32: The OPIO protocol and PCIe protocol are both chip-to-chip streaming protocols used for high-bandwidth data streaming between IC dies on an interconnect. “OPIO architecture…to run at high bandwidth” for streaming data between dies. PCIe is a standard high-speed streaming serial protocol. Both are streaming C2C protocols in the chip-to-chip context).
In regard to claim 32, Spry discloses wherein a first streaming C2C protocol of the streaming C2C protocols is a standard-defined protocol and a second streaming C2C protocol of the streaming C2C protocols is a proprietary protocol (in Spry, Spec col. 2:38-60: Second protocol stack uses PCIe™ specification - a standard-defined protocol (IEEE/PCI-SIG standard). First protocol stack uses OPIO (Intel proprietary on-package I/O) that a proprietary protocol. Thus Spry expressly discloses one standard-defined (PCIe) and one proprietary (OPIO) C2C protocol in the same adaptive interface).
In regard to claim 33, Spry discloses wherein the circuitry corresponding to one of the plurality of different C2C protocols not selected during boot time remains unused during runtime (in Spry, Col. 10:62 thru col. 11:30: “the other unselected set of circuitry may be excluded from a protocol stack by being disabled (e.g. where Glue logic 720 and/or LP AFE 730 (or alternatively, Phy logic 740 and/or AFE 760)) is fusedly, switchedly or otherwise disconnected from one or more supply voltage lines”. Disabled/disconnected = unused during runtime. Expressly disclosed).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 34-39 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Spry in view of Subramaniam et al. (“Subramaniam”) (US No. 11,100,028).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Spry and Subramaniam references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 34, Spry discloses a system, comprising:
a first IC die comprising a hardened C2C interface comprising first circuitry supporting a first C2C protocol (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Spry discloses Claim 2 + col. 5:46 thru col. 6:40: “a system comprises a packaged device including the first IC chip, an interconnect and a second IC chip, wherein operation of the first…protocol stack is enabled”);
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and a second IC die connected to the first IC die, wherein the second IC die includes an adaptive C2C interface comprising second circuitry supporting a plurality of different C2C protocols, wherein the second IC die is configured to, during boot time, configure the adaptive C2C interface to perform the first C2C protocol to communicate with the C2C interface in the first IC die (in Spry, Claim 2 + col. 5:46 thru col. 6:40: the second IC chip (like a fixed-protocol die) couples to the first IC chip. Teaches an IC chip (first IC) configured with a specific protocol stack to communicate with another IC chip that providing a two-IC-die system where protocol selection happens at initialization). But Spry does not explicitly disclose the use of “harden”. In the same field of endeavor, Subramaniam discloses multiple ports configured to interface with respective chiplets, wherein at least two…ports have respective different types of [PHY] interfaces. The bridge chiplet is the adaptive die; the chiplets it connects to are hardened/fixed-PHY dies (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Subramaniam discloses Claim 1 + col. 3:59 thru col. 4:23: “multiple ports configured to interface with respective chiplets, wherein at least two…ports have respective different types of [PHY] interfaces.” The bridge chiplet is the adaptive die; the chiplets it connects to are hardened/fixed-PHY dies. Claim 6: “in response to determining that the first chiplet and the second chiplet support a same communication protocol, [data is] route[d]…without converting” thus the adaptive bridge configures itself at boot time to match the fixed-protocol die).
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It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to combine the teaching of Subramaniam with the teaching of Spry to enable interoperability between the cost-optimized hardened interface on one die and a flexible adaptive interface on another die in a multi-die system. This combination would provide the benefit of reduced silicon area and power on the first die while maintaining compatibility and flexibility when integrating dies from different sources or process nodes.
In regard to claim 35, Spry discloses wherein the second circuitry corresponding to one of the plurality of different C2C protocols not selected during boot time remains unused during runtime (in Spry, Col. 10:62 thru col. 11:30: “the other unselected set of circuitry may be excluded from a protocol stack by being disabled (e.g. where Glue logic 720 and/or LP AFE 730 (or alternatively, Phy logic 740 and/or AFE 760)) is fusedly, switchedly or otherwise disconnected from one or more supply voltage lines”. Disabled/disconnected = unused during runtime. Expressly disclosed).
In regard to claim 36, Subramaniam discloses further an interposer, wherein the hardened C2C interface and the adaptive C2C interface communicate with each other via the interposer (in Subramaniam, Claim 2: PHY type Advanced Interface Bus (AIB), AIB is implemented via silicon interposer (EMIB) in standard practice). A POSITA would understand that placing the adaptive bridge and hardened chiplets on a common interposer is the standard chiplet integration technique, making an interposer obvious for the system of claim 34.
In regard to claim 37, Spry discloses wherein the second circuitry supporting the plurality of different C2C protocols includes at least a mux and a de-mux (in Spry, Col. 10:62 thru col. 11:305: “MUX logic 770…is operable to select a particular one (e.g. only one) of the first set of circuitry and the second set of circuitry. MUX logic 770 may forward signal[s] from the selected set of circuitry to the one or more signal lines”. MUX logic = mux; the unselected path circuitry that demultiplexes/directs incoming data to the selected protocol path = de-mux function. Spry expressly recites MUX logic performing selection among protocol data paths).
In regard to claim 38, Spry discloses wherein the de-mux comprises outputs coupled to data paths corresponding to the plurality of different C2C protocols and wherein the de-mux is configured to select only one of the data paths as an output during runtime (in Spry, Col. 10:62 thru col. 11:30: MUX logic “is operable to select a particular one (e.g. only one) of the first set of circuitry and the second set of circuitry”. Once configured, only one data path is active during runtime. “The other unselected set of circuitry may be excluded…by being disabled”);
and wherein the mux is coupled to the data paths as inputs and configured to select between one of the data paths to output to the second IC die (in Spry, Col. 10:62 thru col. 11:30: MUX logic 770 is “coupled to configuration logic which is operable to select a particular one…of the first set of circuitry and the second set of circuitry. MUX logic 770 may forward signal[s] from the selected set of circuitry to the one or more signal lines [780]” thus signal lines 780 couple to the external IC chip (second die) or the processing cores. The mux takes the data paths (OPIO path vs. PCIe path) as inputs and outputs the selected one).
In regard to claim 39, Spry discloses wherein the adaptive C2C interface further comprises: options circuitry disposed between the mux and the de-mux;
coarse registers storing coarse grain configurations to control the mux and the de-mux (in Spry, Col. 10:62 thru col. 11:30 + Fig. 7: Glue logic 720/730 is options circuitry between protocol paths (between de-mux input and mux output). Configuration circuitry stores coarse protocol-stack selection (controls MUX). Link-layer feature registers = fine-grain configuration).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Response to Amendment
8. Applicant’s new amendment of claims and arguments, see pages 3-8, filed on May 14, 2026, with respect to the rejection of claims 1-3, 7-8, 10-14, 17-20 under 35USC102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon new set of claims submitted, a new grounds of rejection is made in view of Spry and Subramaniam.
Conclusion
9. All claims are rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for response to this final action is set to expire THREE MONTHS from the date of this action. In the event a first response is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event will the statutory period for response expire later than SIX MONTHS from the date of this final action.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
Prosecution Insights