Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated August 16, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed October 15, 2024 and May 22, 2025 have been
considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 8 and 11, the phrases “while the data value is evaluated” is unclear. It is unclear as to whether or not the phrases are the same, or whether they are for two different processes – the first occurrence referring to the generation of the first leakage compensation current; while the second occurrence referring to the generation of the second leakage compensation current.
In claims 15 and 19, the phrases “while the data value is evaluated” is unclear. It is unclear as to whether or not the phrases are the same, or whether they are for two different processes – the first occurrence referring to the generation of the first leakage compensation current; while the second occurrence referring to the generation of the second leakage compensation current.
The dependent claims, claims 9, 10, 12-14, 16-18 and 20, are rejected because they depend on the indefiniteness of the claims from which they depend.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10, 14 and 20 of U.S. Patent No. 12087368 [‘368] in view of US Patent 9,384,815 and US Patent Application # 20090251979. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘368
1. (Currently Amended) A method, comprising: precharging a sensing bitline for a read operation of a memory cell coupled to the sensing bitline; sensing a first leakage current on the sensing bitline while precharging the sensing bitline; evaluating, with a sense amplifier after precharging the sensing bitline, a data value of the selected memory cell based on a sensing current on the sensing bitline; and compensating for the first leakage current while evaluating the data value by generating a first leakage compensation current with a leakage current compensation circuit.
10. A method, comprising: passing a first leakage current from a memory array through a sensing bitline coupled to a selected memory cell of the memory array; sensing a value of the first leakage current; adding, to a reference bitline during a read operation of a selected memory cell of the memory array, a leakage compensation current based on the value of the first leakage current; and sensing a data value stored in the selected memory cell by comparing a reference current in the reference bitline to a sensing current in the sensing bitline.
2. (Currently Amended) The method of claim 1, further comprising adding the first leakage compensation current to a reference bitline coupled to the sense amplifier.
See claim 10. “…adding, to a reference bitline during a read operation of a selected memory cell of the memory array, a leakage compensation current …”
3. (Original) The method of claim 1, wherein generating the first leakage compensation current includes drawing the first leakage compensation current from the sensing bitline.
14. The method of claim 10, further comprising: sensing a second leakage current on the reference bitline; and adding, to the reference bitline during the read operation, a second leakage compensation current based on the second leakage current.
4. (Original) The method of claim 3, further comprising: precharging a reference bitline for the read operation of the memory cell coupled to the sensing bitline; sensing a second leakage current on the reference bitline while precharging the reference bitline; and compensating for the second leakage current while evaluating the data value by generating a second leakage compensation current with the leakage current compensation circuit.
14. The method of claim 10, further comprising: sensing a second leakage current on the reference bitline; and adding, to the reference bitline during the read operation, a second leakage compensation current based on the second leakage current.
5. (Original) The method of claim 4, further comprising adding the second leakage compensation current to the reference bitline while evaluating the data value.
14. The method of claim 10, further comprising: sensing a second leakage current on the reference bitline; and adding, to the reference bitline during the read operation, a second leakage compensation current based on the second leakage current.
6. (New) The method of claim 1, wherein the first leakage current flows from a plurality of memory cells that are not selected for the read operation.
See claim 10 and US Patent 9,384,815, to Chen et al. Chen et al. indicated that leakage current is inherent to non-selected memory cells – col. 2, lines 24-36.
7. (New) The method of claim 1, wherein a complimentary memory cell stores a data value opposite to the data value stored by the memory cell, wherein a reference bitline is coupled to the complimentary memory cell during the read operation.
20. The integrated circuit of claim 16, further comprising a complimentary memory cell that stores a data value opposite to the data value stored by the selected memory cell, wherein the reference bitline is coupled to the complimentary memory cell during the read operation.
As can be seen from the above table, similar to claim 10 of the patent '368, claim 1 of the application recites sensing a leakage current, compensating for the leakage current and determine the value of a selected memory cell. Unlike the patent, the application states that the step of sensing the leakage current is done while precharging the sensing bitline; while the patent is silent about this step. However, this process is inherent as is shown in the prior art. For example, patent US patent application 20090251979, of Chang, discusses methods for suppressing leakage during precharge, which inherently implies the ability to detect/sense that leakage in high-density memory [par. 0011]. Thus, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 2-7 are rejected over claims 10, 14 and 20 of patent ‘368 in view of US Patent 9,384,815 and US Patent Application # 20090251979.
Claims 8-10, 13 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 and 20 of U.S. Patent No. 12087368 [‘368] in view of US Patent 9,384,815 and US Patent 11,114,160. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘368
8. (New) An integrated circuit, comprising: a memory cell; a sensing bitline coupled to the memory cell, wherein the sensing bitline is precharged for a read operation of the memory cell; a leakage current compensation circuit coupled to the sensing bitline, wherein the leakage current compensation circuit is configured to sense a first leakage current on the sensing bitline while the sensing bitline is precharged; and a sense amplifier configured to evaluate, after precharging the sensing bitline, a data value of the memory cell based on a sensing current on the sensing bitline, and wherein the leakage current compensation circuit configured to generate a first leakage compensation current for compensating the first leakage current while the data value is evaluated.
16. An integrated circuit, comprising: a memory array including a plurality of memory cells; a sensing bitline coupled to the memory array; a reference bitline; a leakage detector coupled to the sensing bitline and configured to sense a first leakage current on the sensing bitline; a leakage adder coupled to the leakage detector and the reference bitline and configured to add a first leakage compensation current to the reference bitline during a read operation of a selected memory cell of the plurality of memory cells; and a sense amplifier coupled to the sensing bitline and the reference bitline and configured to sense a data value stored in the selected memory based on a sensing current in the sensing bitline and a reference current in the reference bitline.
9. (New) The integrated circuit of claim 8, wherein the first leakage compensation current is added to a reference bitline coupled to the sense amplifier.
See claim 16. “…add a first leakage compensation current to the reference bitline …”
10. (New) The integrated circuit of claim 8, wherein the leakage current compensation circuit is configured to generate the first leakage compensation current by drawing the first leakage compensation current from the sensing bitline.
See claim 16. “…a leakage detector coupled to the sensing bitline and configured to sense a first leakage current on the sensing bitline; a leakage adder coupled to the leakage detector and the reference bitline and configured to add a first leakage compensation current to the reference bitline during a read operation…”
13. (New) The integrated circuit of claim 8, wherein the first leakage current flows from a plurality of memory cells that are not selected for the read operation.
See claim 16 and US Patent 9,384,815, to Chen et al. Chen et al. indicated that leakage current is inherent to non-selected memory cells – col. 2, lines 24-36.
14. (New) The integrated circuit of claim 8, wherein a complimentary memory cell stores a data value opposite to the data value stored by the memory cell, wherein a reference bitline is coupled to the complimentary memory cell during the read operation.
20. The integrated circuit of claim 16, further comprising a complimentary memory cell that stores a data value opposite to the data value stored by the selected memory cell, wherein the reference bitline is coupled to the complimentary memory cell during the read operation.
As can be seen from the above table, similar to claim 16 of the patent '368, claim 8 of the application recites sensing a leakage current, compensating for the leakage current and determine the value of a selected memory cell. Unlike the patent, the application states that the step of precharging the sensing bitline for read operation. However, this process is inherent as is shown in the prior art. For example, patent US 11,114,160, to Gangasani et al., discusses methods for precharging the selected bit line coupled to the selected memory cell during a read operation [col. 5, lines 55-65].
For similar reasons, claims 9, 10, 13 and 14 are rejected over claims 16 and 20 of patent ‘368 in view of US Patent 9,384,815 and US Patent 11,114,160.
Claims 15-17 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16 and 20 of U.S. Patent No. 12087368 [‘368] in view of US Patent 9,384,815 and US Patent 11,114,160. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘368
15. (New) A system, comprising: a memory array including a plurality of memory cells; a sensing bitline coupled to a memory cell of the plurality of memory cells, wherein the sensing bitline is precharged for a read operation of the memory cell; a leakage current compensation circuit coupled to the sensing bitline, wherein the leakage current compensation circuit is configured to sense a first leakage current on the sensing bitline while the sensing bitline is precharged; and a sense amplifier configured to evaluate, after precharging the sensing bitline, a data value of the memory cell based on a sensing current on the sensing bitline and output the data value, andwherein the leakage current compensation circuit configured to generate a first leakage compensation current for compensating the first leakage current while the data value is evaluated.
16. An integrated circuit, comprising: a memory array including a plurality of memory cells; a sensing bitline coupled to the memory array; a reference bitline; a leakage detector coupled to the sensing bitline and configured to sense a first leakage current on the sensing bitline; a leakage adder coupled to the leakage detector and the reference bitline and configured to add a first leakage compensation current to the reference bitline during a read operation of a selected memory cell of the plurality of memory cells; and a sense amplifier coupled to the sensing bitline and the reference bitline and configured to sense a data value stored in the selected memory based on a sensing current in the sensing bitline and a reference current in the reference bitline.
16. (New) The system of claim 15, wherein the first leakage compensation current is added to a reference bitline coupled to the sense amplifier.
See claim 16. “…add a first leakage compensation current to the reference bitline …”
17. (New) The system of claim 15, wherein the leakage current compensation circuit is configured to generate the first leakage compensation current by drawing the first leakage compensation current from the sensing bitline.
See claim 16. “…a leakage detector coupled to the sensing bitline and configured to sense a first leakage current on the sensing bitline; a leakage adder coupled to the leakage detector and the reference bitline and configured to add a first leakage compensation current to the reference bitline during a read operation…”
20. (New) The system of claim 15, wherein the first leakage current flows from a plurality of memory cells that are not selected for the read operation.
See claim 16 and US Patent 9,384,815, to Chen et al. Chen et al. indicated that leakage current is inherent to non-selected memory cells – col. 2, lines 24-36.
As can be seen from the above table, similar to claim 16 of the patent '368, claim 15 of the application recites sensing a leakage current, compensating for the leakage current and determine the value of a selected memory cell. Unlike the patent, the application states that the step of precharging the sensing bitline for read operation. However, this process is inherent as is shown in the prior art. For example, patent US 11,114,160, to Gangasani et al., discusses methods for precharging the selected bit line coupled to the selected memory cell during a read operation [col. 5, lines 55-65].
For similar reasons, claims 16, 17 and 20 are rejected over claims 16 and 20 of patent ‘368 in view of US Patent 9,384,815 and US Patent 11,114,160.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bedarida et al. [US Patent Application # 20080170442].
With respect to claim 1, Bedarida et al. disclose a method, comprising: precharging a sensing bitline for a read operation of a memory cell coupled to the sensing bitline [“In order to correctly read the data item from a memory cell, two phases are involved. The first phase is referred to as a precharge phase. During the precharge phase, a selected memory cell is precharged (e.g., driven to its correct polarization point). The memory cell is polarized at its gate, which, as described above, is connected to a rowline, and is also polarized at its drain, which is connected to a column/bitline” – par. 0003]; sensing a first leakage current on the sensing bitline while precharging the sensing bitline [“ Leakage currents adversely affect the bitline current, which may result in erroneous readings of the memory cells associated with the bitline.” – par. 0004]; evaluating, with a sense amplifier after precharging the sensing bitline, a data value of the memory cell based on a sensing current on the sensing bitline [“…he sense amplifier is reading a programmed bit (i.e., a zero bit), the addressed bitline after the precharge phase…” – par. 0033]; and compensating for the first leakage current while evaluating the data value by generating a first leakage compensation current with a leakage current compensation circuit [“The compensation device is operative to compensate the leakage current of the memory circuit through a current based on the leakage current of the compensation circuit. “ – par. 0018].
With respect to claim 2, Bedarida et al. disclose adding the first leakage compensation current to a reference bitline coupled to the sense amplifier [“…the sensing circuit includes a memory circuit including a bitline that may also sink a leakage current, and includes a compensation circuit that includes a dummy bitline that sinks a generic leakage current that matches the leakage current of the bitline of the memory circuit. “ – par. 0018 and fig. 5].
With respect to claim 3, Bedarida et al. disclose generating the first leakage compensation current includes drawing the first leakage compensation current from the sensing bitline [“…the sensing circuit includes a memory circuit including a bitline that may also sink a leakage current, and includes a compensation circuit that includes a dummy bitline that sinks a generic leakage current that matches the leakage current of the bitline of the memory circuit. “ – par. 0018 and fig. 5]. It is noted that "sinks a generic leakage current" is interpreted as being the dummy circuit draws a current equal in magnitude to the estimated leakage of the main bitline.
With respect to claim 6, Bedarida et al. disclose the first leakage current flows from a plurality of memory cells that are not selected for the read operation [“…The leakage current Ileak is present even if no memory cell is selected, as long as the bitline is being polarized.” – par. 0030].
Claim(s) 8-10 and 13 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Bedarida et al. [US Patent Application # 20080170442].
With respect to claim 8, Bedarida et al. disclose an integrated circuit, comprising: a memory cell [abstract]; a sensing bitline coupled to the memory cell, wherein the sensing bitline is precharged for a read operation of the memory cell [“In order to correctly read the data item from a memory cell, two phases are involved. The first phase is referred to as a precharge phase. During the precharge phase, a selected memory cell is precharged (e.g., driven to its correct polarization point). The memory cell is polarized at its gate, which, as described above, is connected to a rowline, and is also polarized at its drain, which is connected to a column/bitline” – par. 0003]; a leakage current compensation circuit coupled to the sensing bitline [par. 0018], wherein the leakage current compensation circuit is configured to sense a first leakage current on the sensing bitline while the sensing bitline is precharged [“ Leakage currents adversely affect the bitline current, which may result in erroneous readings of the memory cells associated with the bitline.” – par. 0004]; and a sense amplifier configured to evaluate, after precharging the sensing bitline, a data value of the memory cell based on a sensing current on the sensing bitline [“…he sense amplifier is reading a programmed bit (i.e., a zero bit), the addressed bitline after the precharge phase…” – par. 0033], and wherein the leakage current compensation circuit configured to generate a first leakage compensation current for compensating the first leakage current while the data value is evaluated [“The compensation device is operative to compensate the leakage current of the memory circuit through a current based on the leakage current of the compensation circuit. “ – par. 0018].
With respect to claim 9, Bedarida et al. disclose the first leakage compensation current is added to a reference bitline coupled to the sense amplifier [“…the sensing circuit includes a memory circuit including a bitline that may also sink a leakage current, and includes a compensation circuit that includes a dummy bitline that sinks a generic leakage current that matches the leakage current of the bitline of the memory circuit. “ – par. 0018 and fig. 5].
With respect to claim 10, Bedarida et al. disclose the leakage current compensation circuit is configured to generate the first leakage compensation current by drawing the first leakage compensation current from the sensing bitline [“…the sensing circuit includes a memory circuit including a bitline that may also sink a leakage current, and includes a compensation circuit that includes a dummy bitline that sinks a generic leakage current that matches the leakage current of the bitline of the memory circuit. “ – par. 0018 and fig. 5]. It is noted that "sinks a generic leakage current" is interpreted as being the dummy circuit draws a current equal in magnitude to the estimated leakage of the main bitline.
With respect to claim 13, Bedarida et al. disclose the first leakage current flows from a plurality of memory cells that are not selected for the read operation [“…The leakage current Ileak is present even if no memory cell is selected, as long as the bitline is being polarized.” – par. 0030].
Claim(s) 15-17 and 20 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Bedarida et al. [US Patent Application # 20080170442].
With respect to claim 15, Bedarida et al. disclose a system, comprising: a memory array including a plurality of memory cells [abstract]; a sensing bitline coupled to a memory cell of the plurality of memory cells, wherein the sensing bitline is precharged for a read operation of the memory cell [“In order to correctly read the data item from a memory cell, two phases are involved. The first phase is referred to as a precharge phase. During the precharge phase, a selected memory cell is precharged (e.g., driven to its correct polarization point). The memory cell is polarized at its gate, which, as described above, is connected to a rowline, and is also polarized at its drain, which is connected to a column/bitline” – par. 0003]; a leakage current compensation circuit [par. 0018] coupled to the sensing bitline, wherein the leakage current compensation circuit is configured to sense a first leakage current on the sensing bitline while the sensing bitline is precharged [“ Leakage currents adversely affect the bitline current, which may result in erroneous readings of the memory cells associated with the bitline.” – par. 0004]; and a sense amplifier configured to evaluate, after precharging the sensing bitline, a data value of the memory cell based on a sensing current on the sensing bitline and output the data value [“…he sense amplifier is reading a programmed bit (i.e., a zero bit), the addressed bitline after the precharge phase…” – par. 0033], and wherein the leakage current compensation circuit configured to generate a first leakage compensation current for compensating the first leakage current while the data value is evaluated [“The compensation device is operative to compensate the leakage current of the memory circuit through a current based on the leakage current of the compensation circuit. “ – par. 0018].
With respect to claim 16, Bedarida et al. disclose the first leakage compensation current is added to a reference bitline coupled to the sense amplifier [“…the sensing circuit includes a memory circuit including a bitline that may also sink a leakage current, and includes a compensation circuit that includes a dummy bitline that sinks a generic leakage current that matches the leakage current of the bitline of the memory circuit. “ – par. 0018 and fig. 5].
With respect to claim 17, Bedarida et al. disclose the leakage current compensation circuit is configured to generate the first leakage compensation current by drawing the first leakage compensation current from the sensing bitline [“…the sensing circuit includes a memory circuit including a bitline that may also sink a leakage current, and includes a compensation circuit that includes a dummy bitline that sinks a generic leakage current that matches the leakage current of the bitline of the memory circuit. “ – par. 0018 and fig. 5]. It is noted that "sinks a generic leakage current" is interpreted as being the dummy circuit draws a current equal in magnitude to the estimated leakage of the main bitline.
With respect to claim 20, Bedarida et al. disclose the first leakage current flows from a plurality of memory cells that are not selected for the read operation [“…The leakage current Ileak is present even if no memory cell is selected, as long as the bitline is being polarized.” – par. 0030].
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 26, 2026