Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1, 4-14, 17, 18, 19, and 20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 06/20/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/10/2023 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-14, 17, 18, 19, and 20 are rejected 35 U.S.C. 103 as being unpatentable over CHOUDHARY et al. (USPGPUB No. 2022/0318111 A1, hereinafter referred to as Choudhary) in view of Das Sharma et al. (USPGPUB No. 2024/0311330 A1, hereinafter referred to as Das Sharma) and further in view of Pappu et al. (US Pat No. 2023/0114271 A1, hereinafter referred to as Pappu) and further in view of Chen et al. (USPGPUB No. 2021/0373867 A1, hereinafter referred to as Chen).
Referring to claim 1, Choudhary discloses an electronic device comprising a plurality of chiplets {“connect multiple chiplets or dies on a single [electronic device] package”, see Fig. 1 [0020], 1st sentence}, comprising:
a first chiplet that generates a transaction {“accelerator 120 and/or I/O tile 130 can be connected to CPU(s) 110 using CXL transactions running on UCIe interconnects 150”, see Fig. 1, [0026], 1st sentence};
a second chiplet that receives the transaction {“state in which transactions are sent and received [per chiplet]”, see Figs. 1 and 8, Table 1 “ACTIVE” description after [0061]}; and at least one third chiplet that relays the transaction {third chiplet “mirror port”, see Fig. 11 [0087]}, wherein the first chiplet determines a route path for the transaction {first chiplet “1130”, see Fig. 1 [0087]} that passes through the at least one third chiplet {third chiplet relay route path “through mirror port 1160.sub.A to D2D adapter 1120.sub”, see Fig. 11 [0087]}, and transmits the transaction through the determined route path for the transaction {“this data can be sent out through port one circuitry to a debug fabric and/or on-die tracing component 1150.sub.1”, see Fig. 11 [0087] last sentence};
However, Das Sharma discloses wherein the at least one third chiplet includes a chiplet (3-1) connected {“UCIe may expand to three-dimensional interconnects”, see Figs. 8 or 9 [0084]} to the first chiplet through a first communication module {“aggregating multiple devices behind a given set of UCIe links”, see Table 3 Figs. 8 or 9, [0085], 3rd sentence} in a first direction of the first chiplet {“rows corresponding to transmit (Tx) only or receive”, see Figs. 8 or 9 [0085], 2nd sentence}, and a chiplet (3-2) connected to the first chiplet through a second communication module {“rows corresponding to transmit (Tx) only or receive”, see Figs. 8 or 9 [0085], 2nd sentence} in a second direction of the first chiplet {“RX” a second direction distinguishing from “TX transmit”, see Figs. 8 or 9 [0085], 2nd sentence}, the route path for the transaction includes a first route path that passes through the chiplet (3-1) and a second route path that passes through the chiplet (3-2) {“interface 706 maps the received UCIe signals to memory signals, and encodes the memory signals for transmission over the SoC fabric 104 via the memory interface”, see Fig. 7, [0089] last two sentences}, and the first chiplet determines the route path {“The SoC fabric 804 may perform address-based hash to determine to which UCIe link transactions should be transmitted”, see Figs. 8 or 9 [0094] 4th sentence} for the transaction based on a number of transactions {“Only update flow control (FC) (UpdateFC) data link layer packets (DLLPs) (UpdateFC DLLPs) may be allowed,”, see Fig. 8, [0093], 4th sentence} associated with the first route path and a number of transactions associated {“ Each UCIe sideband packet may carry 64b or 2 data words (DWords or DW) of data. However, some embodiments may introduce operational codes (opcodes) that can carry up to 8 DWs of data, allowing for 4DW TLP header and 4DW TLP data to be sent with a [transaction] single UCIe VDM.”, [0093] 2nd sentence} with the second route path {“they may be tunneled using a similar mechanism as TLPs [transaction layer packet associated with another route]”, see Fig. 8, [0093], 4th sentence}.
Choudhary and Das Sharma are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Choudhary’s electronic device incorporating Das Sharma’s “UCIe may expand to three-dimensional interconnects” (see Figs. 8 or 9 [0084]).
The suggestion/motivation for doing so would have been to implement SoC and the memory chips each instantiate UCIe interfaces and associated interface logic to allow the SoC and the memory chips to communicate standard memory signals as UCIe signals transported over the UCIe interconnect which facilitates a unified solution to scale on-package memory to support various applications ranging from applications suitable for hand-held computers to high-performance computing (HPC) applications (Das Sharma [0026], last two sentences).
Therefore, it would have been obvious to combine Das Sharma with Choudhary to obtain the invention as specified in the instant claim(s).
Neither Choudhary or Das Sharma appears to explicitly disclose third chiplet and a fourth chiplet that are capable of relaying the transaction, wherein the first chiplet determines a route path for the transaction between a first route path and a second route path, and transmits the transaction through the determined first route path or second route path for the transaction.
However, Pappu discloses third chiplet and a fourth chiplet that are capable of relaying the transaction {“A diverse set of chiplets with different IP core logic”, see Fig. 24c, [0347]; transactions “cause transactions to [relay] travel through the interconnect fabric while avoiding the processing resources 2750.”, see Figs. 24c and 7, [0376] }, wherein the first chiplet determines a route path {“bridge 2482 may be a dense interconnect structure that provides a route for electrical signals.”, see Figs. 24b and 24c, [0345], 2nd sentence} for the transaction between a first route path and a second route path {“where the architecture sends tuned transactions through various [route paths] channels to the memory”, see Figs. 26 and 27, [0368]}, and transmits the transaction through the determined first route path or second route path for the transaction {“alternate low power state path 2705 is utilized to transfer data in and out of memory 2760 during the low power state, without waking up the processing resources 2750”, see Fig. 27, [0376] last sentence}.
Choudhary/Das Sharma and Pappu are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Choudhary/Das Sharma’s system incorporating Pappu’s route paths “various channels to the memory” (see Figs. 26 and 27 [0368]).
The suggestion/motivation for doing so would have been to implement parallel rendering graphics architectures utilize a low power state or low power mode to save and conserve energy (Pappu [0004] 1st sentence) which among other things to further increase performance, graphics processors typically implement processing techniques such as pipelining that attempt to process, in parallel, as much graphics data as possible throughout the different parts of the graphics pipeline (Pappu [0003], 1st sentence).
Therefore, it would have been obvious to combine Pappu with Choudhary/Das Sharma to obtain the invention as specified in the instant claim(s).
Neither one of the group consisting of Choudhary, Das Sharma, and Pappu appears to explicitly disclose wherein the electronic device comprising a plurality of chiplets arranged in a chiplet matrix; wherein the first chiplet determines the route path for the transaction based on monitored congestion state information of the first communication module and the second communication module, the congestion state information including a number of transactions associated with the first route path and a number of transactions associated with the second route path, and
the first chiplet determines, as the route path for the transaction, one of the first route path or the second route path based on the monitored congestion state information.
However, Chen discloses wherein the electronic device {“CGRA (coarse-grained reconfigurable architecture) processor”, see Fig. 12, [0171]} comprising a plurality of chiplets arranged in a chiplet matrix {“tile and an array level network”, see Fig. 13a, [0179]};
the first chiplet determines the route path for the transaction {“The barrier connections control transmission of the read ready token and the write done token from the two or more of the consumers to the producers in the set of the producers. After the control connections are established in the dataflow graph 400, it becomes a control and dataflow graph 800 [for the respective claimed transaction(s)”, see Figs. 5 and 8a, [0144] last two sentences} based on monitored congestion state information {“A zero write credit means that the consumer is still collecting the result from a previous sample and the processing of the previous sample is not yet finished” thereby busy or “congested”, see Fig. 3, [0125]} of the first communication module {“using the control connections to [communication module] control writing of the data by the producers into the consumers.”, see Fig. 2, [0107], 1st sentence} and the second communication module {“create [second communication modules] barrier connections that extend from the”, see Fig. 2, [0109], 2nd sentence}, the congestion state information including a number of transactions associated with the first route path {“the producers are stage buffers A, B, C (502, 512, 522) and the consumer is stage buffer L (520)” illustrating a first route path, see Figs. 5 and 8a, [0142]} and a number of transactions associated with the second route path {“stage 1.0, the producers are stage buffers D, E (503, 513), and the consumer is stage buffer F (514), and therefore [second route path] two control connections extend from the stage buffer F (514) to the stage buffers D and E (503, 513)”, see Fig. 8a, [0142] last sentence}, and
the first chiplet determines, as the route path for the transaction {“Each AGCU contains a reconfigurable scalar [route path] data path to”, see Fig. 13b, [0198], 3rd sentence}, one of the first route path or the second route path {“A data path in a configurable unit can be organized as a [second route] multi-stage (Stage 1… . . . Stage N), reconfigurable SIMD (Single Instruction, Multiple Data) pipeline”, see Fig. 14, [0201], 2nd sentence} based on the monitored congestion state information {“circuit including the anti-congestion logic 232 can be implemented”, see Fig. 15, [0202], 3rd sentence}.
Choudhary/Das Sharma/Pappu and Chen are analogous because they are from the same field of endeavor, routing packet stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Choudhary/Das Sharma/Pappu’s system incorporating Chen’s “coarse-grained reconfigurable architectures CGRAs” (see Fig. 1 [0087]).
The suggestion/motivation for doing so would have been to implement CGRAs, computation can be executed as deep, nested dataflow pipelines that exploit nested parallelism and data locality very efficiently. These dataflow pipelines contain several stages of computation, where each stage reads data from one or more input buffers with an irregular memory access pattern, performs computations on the data while using one or more internal buffers to store and retrieve intermediate results (Chen [0087]) in order to maximize operating efficiency, and to be able to coordinate among processing units on a processing system, a means of efficiently managing control signaling is needed ([0026]).
Therefore, it would have been obvious to combine Chen with Choudhary/Das Sharma/Pappu to obtain the invention as specified in the instant claim(s).
As per claim 4, the rejection of claim 1 is incorporated and Choudhary discloses wherein the number of transactions associated with the first route path corresponds {“For example, on RDI, credits are advertised from physical layer to adapter for sideband packets transmitted from the adapter to the physical layer [respective route path]”, see Fig. 7 [0060]} to a number of multiple outstandings (MOs) {“determine the number of credits advertised by the receiver, with a maximum of 32 credits” per port , see Fig. 7 [0060], 3rd sentence} of a first port associated with the first communication module {communication module(s) coupled to “across FDI, RDI or the UCIe sideband link”, see Fig. 7 [0060]}, and the number of transactions associated with the second route path {“For example, on RDI, credits are advertised from physical layer to adapter for sideband packets transmitted from the adapter to the physical layer [respective route path]”, see Fig. 7 [0060]} corresponds to a number of MOs of a second port associated {“determine the number of credits advertised by the receiver, with a maximum of 32 credits” per port , see Fig. 7 [0060], 3rd sentence} with the second communication module {communication module(s) coupled to “across FDI, RDI or the UCIe sideband link”, see Fig. 7 [0060].
As per claim 5, the rejection of claim 1 is incorporated and Choudhary discloses wherein the first chiplet includes a first function module {“When a [first function mode] requests an active”, see Fig. 8 [0067], 5th sentence} that generates an instruction associated {“requests an active [instruction] on the RDI”, see Fig. 8 [0067], 5th sentence} with the transmission of the transaction {“active [instruction] on the RDI or a remote link partner requests l1 exit [per transmission control”, see Fig. 8 [0067], 5th sentence} or controls the transmission of the transaction based on a received instruction {Examiner’s interpretation: recitation “or” in this portion of the claim renders the claim as a Markush claim, thus the reference only needs to disclose one element in the group to address the claim}, and the first function module is configured to determine the route path for the transaction {“die can enter the PHYRETRAIN state for a number of reasons. The trigger may be by an adapter-directed PHY retrain or a PHY-initiated PHY retrain [for a given path].”, see Fig. 8 [0069], 1st two sentences} based on the number and size of the transactions associated with the first route path {“Based on the defined and available registers [associated with the claimed transactions],”, see Fig. 11 [0094], last sentence} and the number and size of the transactions associated with the second route path {“link state machine logger may be configured to monitor state progression” per route path, see Fig. 11 [0094], last sentence}.
As per claim 6, the rejection of claim 5 is incorporated and Choudhary discloses wherein the first chiplet further includes a second function module {“When a [function mode] requests an active” per direction “tx” or “rx” receiver, see Fig. 8 [0067], 5th sentence} that generates the transaction {“requests an active [instruction] on the RDI”, see Fig. 8 [0067], 5th sentence}, the first function module is an upper level module {“packets from upper layer [modules]”, see Fig. 8 [0066]} of the second function module, the first function module determines the route path for the transaction in consideration of an expected transaction congestion situation {“time spent in each state, and sub-state and/or stuck state”, see Fig. 11 [0094] last sentence}, and the first function module modifies the route path {“enables exercising [/modifying] different arcs of a flit format negotiation tree”, see Fig. 11 [0093]} for the transaction generated by the second function module {“[respective function module] reference design can monitor state progressions and parameters of the DUT”, see Fig. 11 [0093]} according to the determined route path for the transaction {“ensure that mandatory flit formats are supported for a [determined route path] given protocol”, see Fig. 11 [0093]}.
As per claim 7, the rejection of claim 1 is incorporated and Choudhary discloses wherein the first chiplet includes a monitoring module {“training progression and monitoring”, see Fig. 11 [0093], 1st sentence} that detects a congestion state {“Based on the defined and available registers, a link state machine logger may [detect a congestion state”, see Fig. 11 [0094] last sentence} of at least one of a first interface for data transmission between the plurality of chiplets {“status registers for PHY logical and adapter [interface] elements”, see Fig. 11 [0094], 3rd sentence}, or a second interface for data transmission in the second chiplet {Examiner’s interpretation: recitation “or” in this portion of the claim renders the claim as a Markush claim, thus the reference only needs to disclose one element in the group to address the claim}, the third chiplet, and the fourth chiplet {“interface 706 maps the received UCIe signals to memory signals, and encodes the memory signals for transmission over the SoC fabric 104 via the memory interface”, see Fig. 7, [0089] last two sentences}, and the monitoring module is configured to determine the route path for the transaction {“The SoC fabric 804 may perform address-based hash to determine to which UCIe link transactions should be transmitted”, see Figs. 8 or 9 [0094] 4th sentence} based on the congestion state of at least one of the first interface or the second interface {“Based on the defined and available registers, a link state machine logger may be configured to monitor state progression, time spent in each state, and sub-state and/or stuck state”, see Fig. 11 [0094] last sentence}.
As per claim 8, the rejection of claim 7 is incorporated and Choudhary discloses wherein the monitoring module is connected to the second chiplet, the third chiplet, and the fourth chiplet {“on-die tracing component 1150 may be configured to capture real time functional traffic [of the respective claimed chiplets].”, see Fig. 11 [0091]}, and the monitoring module receives at least one of congestion information associated with the first interface {“die may access [receives at least one congestion among other types of] information present in link status and control registers and/or a UCIe test/compliance register block”, see Fig. 12 [0102], 2nd sentence} or congestion information associated with the second interface {Examiner’s interpretation: recitation “or” in this portion of the claim renders the claim as a Markush claim, thus the reference only needs to disclose one element in the group to address the claim} from each of the second chiplet, the third chiplet, and the fourth chiplet {“when detected, may cause a receive die to capture a (e.g., programmable) number of flits or specific portion of them.”, see Fig. 11 [0091], 3rd sentence}.
As per claim 9, the rejection of claim 7 is incorporated and Choudhary discloses wherein the monitoring module receives at least one of congestion information associated with the first interface {“die may access [receives at least one congestion among other types of] information present in link status and control registers and/or a UCIe test/compliance register block”, see Fig. 12 [0102], 2nd sentence} or congestion information associated with the second interface [receives at least one congestion among other types of] information present in link status and control registers and/or a UCIe test/compliance register block”, see Fig. 12 [0102], 2nd sentence}, from another chiplet through a third interface different from the first interface {“when detected, may cause a receive die to capture a (e.g., programmable) number of flits or specific portion of them.” Any given interface via Die to Die Adapter or “electrical/AFE” (see Fig. 11 [0091], 3rd sentence)}.
As per claim 10, the rejection of claim 1 is incorporated and Das Sharma discloses wherein the first chiplet includes, in the transaction, information {“transactions may be packetized by sending their transaction layer packets (TLPs) inside the data payload of UCIe vendor defined messages”, see Fig. 8 [0093]} on the determined first route path or second route path for the transaction {“Because there may be no sideband for off-package SERDES, embodiments may still use CXL.io FLITs to send the TLPs [on determined route path],”, see Fig. 8, [0095]}.
Referring to claim 11-13 are apparatus claims reciting claim functionality corresponding to the device claim of claims 1, 4-10, respectively, thereby rejected under the same rationale as claims 1, 4-10 recited above.
Referring to claim 14, 17, 18, 19, and 20 are method claims reciting claim functionality corresponding to the device claim of claims 1, and 4-10, respectively, thereby rejected under the same rationale as claims 1, 4-10 recited above.
Response to Arguments
Applicant’s arguments, filed on 08/19/2025, have been considered however rendered moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references indicative of the current state of the art: US 20190227753 A1, US 20200192839 A1, US 20210311897 A1, US 20210326277 A1, and US 20220198117 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.B./
Examiner
Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184