Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 07/03/25. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statements filed on 07/03/25, 08/19/24 have been received and are being considered.
Claim Rejections under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. §102(a)(1) and §102(a)(2) as being unpatentable over Peng (US 20230243888 A1).
Regarding claim 1, Peng (see Figs.2 and 17, and [0041-0168]) discloses:
A device 1 comprising: a first layer 10 including at least one transistor 11, 12; a second layer 21 on a first side of the first layer 10, the second layer 21 including a signal network 211,212 (see D1, [0041] "The conductive structure 21 includes a plurality of landing portions 211 and a plurality of conductive vias 212" and [0057] "the output signal (e.g., an electrical signal, such as a voltage or current) of the output terminal 111 of the cell 11 is transmitted to the topmost conductive layer 233 through the conductive structure 21");
a third layer 50 on a second side of the first layer 10, the second side opposite the first side (see D1, Fig.2), the third layer 50 including a backside power delivery network (see D1, [0062] "a backside power delivery network 50"); and
a memory module coupled to the signal network (see D1, [0166] "Fig.17 is a block diagram of IC design system 1700, in accordance with some embodiments" and [0168] "processor 1702 is electrically coupled to computer readable memory 1704 via a bus 1708."It is understood that the device 1 of Fig. 2 is the processor 1702 in Fig. 17 and the processor 1702 is connected to the memory 1704).
Regarding claim 2, Peng discloses the device of claim 1, wherein the memory module comprises at least one dynamic random-access memory die (see para [0144]).
Regarding claim 3, Peng discloses the device of claim 2, wherein the at least one dynamic random-access memory die comprises at least one core memory die (see para [0144] disclosing memory, para [0034] disclosing chip).
Regarding claim 4, Peng discloses the device of claim 1, wherein the signal network is between the first layer and the memory module, and wherein the signal network communicatively couples the first layer and the memory module (see fig 2, where module is connected from top to bottom).
Regarding claim 5, Peng discloses the device of claim 1, further comprising a redistribution layer between the signal network and the memory module (see fig 2, element 10 disclosing redistribution).
Regarding claim 6, Peng discloses the device of claim 5, wherein the redistribution layer includes at least one through-bonding via (see para [0041] disclosing through ILD/via bonding).
Regarding claim 7, Peng discloses the device of claim 1, wherein the backside power delivery network is configured to provide power to the memory module (see para [0062] disclosing backside power delivery, 50).
Regarding claim 8, Peng discloses the device of claim 1, wherein the signal network is configured to provide packet routing signals to the memory module (signals are inherent in memory modules, see i.e. para [0145]).
Regarding claim 9. The device of claim 1, wherein the backside power delivery network, the at least one transistor, and the signal network are configured to provide a logic circuit for the memory module(signals are inherent in memory modules, see i.e. para [0145] disclosing design rules).
Regarding claim 10, Peng discloses a system comprising:
a substrate having a first side and a second side opposite the first side (10 top and bottom);
a transistor layer on the first side of the substrate, the transistor layer including at least one transistor(see para [0033] disclosing transistors);
a signal network on the transistor layer, the signal network communicatively coupled to the transistor layer (211,212 (see Peng, [0041]); and
a backside power delivery network on the second side of the substrate, the backside power delivery network electrically coupled to the transistor layer(see Peng, [0062] "a backside power delivery network 50");
wherein the backside power delivery network, the transistor layer, and the signal network are configured to provide a logic circuit for a memory module (see Peng, [0166] "Fig.17 is a block diagram of IC design system 1700, in accordance with some embodiments" and [0168] "processor 1702 is electrically coupled to computer readable memory 1704 via a bus 1708."It is understood that the device 1 of Fig. 2 is the processor 1702 in Fig. 17 and the processor 1702 is connected to the memory 1704).
Regarding claim 11, Peng discloses the system of claim 10, wherein the memory module comprises at least one high bandwidth memory die (see para [0144] disclosing high bandwidth memory, DRAM).
Regarding claim 12, Peng discloses the system of claim 11, wherein the at least one high bandwidth memory die comprises at least one core memory die(see para [00144] disclosing different types of memory).
Regarding claim 13, Peng discloses the system of claim 11, wherein the memory module is mounted on the substrate (see para [0144] disclosing memory module).
Regarding claim 14, Peng discloses the system of claim 10, further comprising a redistribution layer between the signal network and the memory module (see fig 2, element 10).
Regarding claim 15, Peng discloses the system of claim 14, wherein the redistribution layer includes at least one through-bonding via(see para [0041] disclosing through ILD/via bonding).
Regarding claim 16, Peng discloses a method comprising:
forming a transistor layer on a first side of a first substrate, the transistor layer including at least one transistor(see para [0033] disclosing transistors, see element 10);
forming a signal network layer on the transistor layer, the signal network layer communicatively coupled to the transistor layer 211,212 (see D1, [0041] "The conductive structure 21 includes a plurality of landing portions 211 and a plurality of conductive vias 212" and [0057] "the output signal (e.g., an electrical signal, such as a voltage or current) of the output terminal 111 of the cell 11 is transmitted to the topmost conductive layer 233 through the conductive structure 21");
forming a backside power delivery network layer on a second side of the first substrate, the second side opposite the first side(see Peng, [0062] "a backside power delivery network 50"), the backside power delivery network layer electrically coupled to the transistor layer (see fig 10, 40);
bonding a memory module to the signal network layer (see Peng, [0166] "Fig.17 is a block diagram of IC design system 1700, in accordance with some embodiments" and [0168] "processor 1702 is electrically coupled to computer readable memory 1704 via a bus 1708."It is understood that the device 1 of Fig. 2 is the processor 1702 in Fig. 17 and the processor 1702 is connected to the memory 1704); and
attaching the backside power delivery network layer to a second substrate(see Peng, [0062] "a backside power delivery network 50").
Regarding claim 17, Peng discloses the method of claim 16, wherein the memory module is at least one high bandwidth memory die (see para [0144] disclosing different memory dies).
Regarding claim 18, Peng discloses the method of claim 16, wherein bonding a memory module to the signal network layer includes forming a redistribution layer on the signal network layer, and bonding the memory module to the redistribution layer (see fig 2, disclosing elements 10, 40, etc.).
Regarding claim 19, Peng discloses the method of claim 18, wherein bonding the memory module to the redistribution layer includes a hybrid bonding process (see para [0149]-[0150] describing layout and formation rules involving bonding and deposition).
Regarding claim 20, Peng discloses the method of claim 16, wherein prior to forming the backside power delivery network layer, the second side of the first substrate is partially removed (see element 10 in fig 2 where the layer is partially removed).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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