DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 22 and 25-44 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 22 and 25-44 are rejected under 35 U.S.C. 103 as being unpatentable over WO2017039948A1 (hereinafter D1) and further in view of US20070113121A1 (hereinafter D2).
Claim 22: D1 teaches a memory controller (120, 734, 864) including:
circuitry (170, 226) configured to issue an error scrub command (e.g. Figs. 4A, 4B, 6/622, [0020], [0040]), the error scrub command causing a memory device to perform a scrub operation in response to the error scrub command, wherein the scrub operation includes: reading, from memory cells, data preexisting the scrub operation and an error correction code and performing an error correction operation on the read data using the ECC to generate error-corrected data (e.g. [0025], [0054]); wherein the memory device counts error information (e.g., rows with errors) and stores it in registers, which the memory controller can receive/read (Abstract, [0027], [0040], Figs. 4C, 4D).
D1 fails to teach:
computing a new ECC based on the error-corrected data; and writing the error-corrected data and the new ECC back to the memory cells from where the data preexisting the scrub operation and the ECC was read; the circuitry further configured to: receive error information corresponding to at least one row of memory cells of the memory device, wherein the error information is based on the scrub operation; send a repair command to the memory device that causes the memory device to back up repair-requiring data and an ECC from a failing row of memory cells of the memory device to a redundant row of memory cells of the memory device; send a read command to read the repair-requiring data: receive the repair-requiring data from the redundant row of the memory device in response to the read command; and upon receipt of the repair-requiring data store the repair-requiring data in a temporary memory.
However, D2 teaches that a memory controller (implied in the system context) can send a repair command to the memory device (e.g. [0014], [0019]). This command initiates a process where data from failing memory elements is read, error-corrected, stored temporarily, and then written back to dedicated redundant memory elements (e.g., redundant rows) after repair [[0023]]. And The failure information used for repair is derived from error correction logs, which are a form of error information received by the controller (Abstract, [0004]).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, confronted with the problem of improving memory subsystem reliability, would have been motivated to combine D1 and D2 in order to create an automated "detect-and-repair" system. The specific sequence of sending a read command to access the repaired data from the redundant row and storing it in a temporary memory is a routine step inherent to verifying or utilizing the repair outcome, as suggested by the data handling in D2 (e.g. [0023]).
As per claims 31 and 38, the claimed features are rejected similarly to claim 22 above.
Claim 25: D1 and D2 teach the memory controller of claim 22, but fail to teach that the circuitry is further configured to: send, to the memory device, a request for the error information; and receive, from the memory device, the error information in response to the request. However, it is an obvious and routine communication protocol for a controller to poll a device for status or log information, especially when such information is stored in registers (as in D1).
As per claims 32 and 39, the claimed features are rejected similarly to claim 25 above.
Claim 26: D1 and D2 teach the memory controller of claim 22, wherein the new ECC is computed without the memory controller having sent a write command to write new data (e.g. This is an inherent feature of the autonomous scrub operation in D1, where the memory device internally performs the ECC cycle and write-back without needing a specific data write command from the controller [0025], [0054]).
As per claims 33 and 40, the claimed features are rejected similarly to claim 26 above.
Claim 27: D1 and D2 teach the memory controller of claim 22, wherein the error scrub command causes the memory device to correct errors in at least the data preexisting the scrub operation using at least one ECC independently of the memory controller (e.g. This is the express purpose of the ECS mode in D1, where the memory device "performs internal ECC" independently of the controller [0020], [0025]).
As per claims 34 and 41, the claimed features are rejected similarly to claim 27 above.
Claim 28: D1 and D2 teach the memory controller of claim 22, but fail to teach that the repair command causes the memory device to perform a hard repair that permanently repairs the failing row using one or more e-fuses. However, D1 explicitly teaches transferring failure information to on-chip e-fuses for permanent storage and repair [[0021]]. Therefore, implementing the repair command to trigger this known, permanent repair mechanism would have been obvious.
As per claims 35 and 42, the claimed features are rejected similarly to claim 28 above
Claim 29: D1 and D2 teach the memory controller of claim 22, wherein the repair command causes the memory device to perform a soft repair that temporarily repairs the failing row only while the memory device remains powered. However, D1 describes repairs using externally supplied information stored in latches, which is volatile and lost without power (e.g., [[0017]]). Therefore, implementing the repair command to trigger this known, temporary repair mechanism would have been obvious.
As per claims 36 and 43, the claimed features are rejected similarly to claim 29 above.
Claim 30: D1 and D2 teach the memory controller of claim 22, but fail to teach that the circuitry is further configured to: send a second read command directed to an address on the memory device that contains data that has a single-bit error; and receive, from the memory device in response to the second read command, a corrected version of the data that has the single-bit error, the corrected version of the data having no errors, wherein the corrected version of the data that has the single-bit error is based on the data that had the single-bit error and also based on an associated ECC. However, the use of ECC to correct single-bit errors is foundational in both references (D1: [0025]; D2: [0002], [0023]). It would be an obvious and inherent function of a memory system using ECC to return corrected data upon a read request.
As per claims 37 and 44, the claimed features are rejected similarly to claim 30 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 2/10/2026