DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “seventh metal layer disposed between the sixth metal layer and the first insulating layer” recited by claims 6 and 15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6-7, and 15-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 6 and 15, both claims recite the limitation “a second via disposed in the second insulating layer, connected to the pad, and having a sixth metal layer and a seventh metal layer disposed between the sixth metal layer and the first insulating layer” (emphasis added) in lines 7-10 which does not have support in the disclosure. The specification discloses, in ¶ 0216], that “the conductive layer 21cv is an example of a sixth metal layer, and the conductive layer 23cv is an example of a seventh metal layer”. Conductive layer 23cv is shown in Fig. 12B as being between conductive layer 21cv and the second insulating layer 40, rather than the conductive layer 21cv and the first insulating layer 50 as required by the claim.
Claims 7 and 16 depends upon claims 6 and 15 respectively, and do not rectify the problem. There, claims 7 and 16 are rejected on at least the same basis as claims 6 and 15.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7, and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 6 and 15, both claims recite the limitation “a second via disposed in the second insulating layer, connected to the pad, and having a sixth metal layer and a seventh metal layer disposed between the sixth metal layer and the first insulating layer” (emphasis added) in lines 7-10. It is indefinite how the seventh metal layer can be both disposed in the second insulating layer and between the sixth metal layer and the first insulating layer.
Claims 7 and 16 depends upon claims 6 and 15 respectively, and do not rectify the problem. There, claims 7 and 16 are rejected on at least the same basis as claims 6 and 15.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, and 8-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sawada et al. (US 20220189905 A1) herein after “Sawada”.
Regarding claim 1, Figs. 4-5 of Sawada disclose a semiconductor device (Fig. 4, semiconductor device, ¶ [0030]), comprising:
a first chip (Fig. 4, array wafer W1, ¶ [0031]) including a first insulating layer (Fig. 4, inter layer dielectric 13, ¶ [0034]);
a second chip (Fig. 4, circuit wafer W2, ¶ [0031]) bonded to the first chip (W1) and including a second insulating layer (Fig. 4, inter layer dielectric 14, ¶ [0034]); and
a pad (Fig. 4, metal pads 38, metal pads 41, ¶ [0034]) provided around a bonded surface between the first chip (W1) and the second chip (W2),
wherein the pad (38, 41) includes a first metal layer (Fig. 5, pad material layer 38b, pad material layer 41b, ¶ [0041]) including a first metal (“the pad material layers 38b and 41b is a metal layer including Cu”, ¶ [0045]),
a second metal layer (Fig. 5, barrier metal layer 41a, ¶ [0041]) disposed between the first metal layer (38b, 41b) and the first insulating layer (13), and a third metal layer (Fig. 5, barrier metal layer 38a, ¶ [0041]) disposed between the first metal layer (38b, 41b) and the second insulating layer (14),
at least one of the second metal layer (41a) or the third metal layer (38a) include a second metal having oxidation energy lower than oxidation energy of the first metal (“the barrier metal layers 38a and 41a are Ti layers”, ¶ [0049]), and
the first metal layer (38b, 41b) further includes the second metal (The instant application discloses, in ¶ [0088], that the metal from the second metal layer (titanium) diffuses easily into the first metal layer (copper). Sawada discloses the same materials for the first, second and third metal layers. Therefore, there would inherently be some of the second metal in the first metal layer in the structure disclosed by Sawada due to the diffusion of titanium into the copper).
Regarding claim 2, Figs. 4-5 of Sawada disclose the semiconductor device according to claim 1 as applied above, and Fig. 10 of Sawada further discloses wherein at least a portion of the second metal in the first metal layer (38b, 41b) is unevenly distributed at a crystal grain boundary of the first metal layer (38b, 41b) (Fig. 10, “shows grain boundaries α between crystal grains in the pad material layers 38b and 41b, and Ti atom groups β diffusing along the grain boundaries α and the bonding face S”, ¶ [0066]).
Regarding claim 3, Figs. 4-5 of Sawada disclose the semiconductor device according to claim 1 as applied above, and Fig. 5 of Sawada further discloses wherein the first metal is copper (“the pad material layers 38b and 41b is a metal layer including Cu”, ¶ [0045]), and
the second metal includes at least one of titanium, manganese, aluminum, or magnesium titanium (“the barrier metal layers 38a and 41a are Ti layers”, ¶ [0049]).
Regarding claim 4, Fig. 5 of Sawada disclose the semiconductor device according to claim 3 as applied above, and Fig. 5 of Sawada further discloses wherein the second metal is contained in at least the second metal layer (41a),
the second metal includes at least titanium (“the barrier metal layers 38a and 41a are Ti layers”, ¶ [0049]), and
the second metal layer (41a) is a barrier metal layer (“the metal pad 38 includes a barrier metal layer 38a…, and the metal pad 41 includes a barrier metal layer 41a”, ¶ [0041]).
Regarding claim 8, Figs. 4-5 of Sawada disclose the semiconductor device according to claim 1 as applied above, and Fig. 4 of Sawada further discloses comprising:
in the first insulating layer (13),
a stacked body including a plurality of conductive layers (Fig. 4, word lines WL, ¶ [0022]) stacked on top of one another with a distance between adjacent ones of the conductive layers (WL); and
a pillar (Fig. 4, columnar portion CL, ¶ [0022]) having a semiconductor layer (Fig. 4, channel semiconductor layer 55, ¶ [0029]) that penetrates through the stacked body (WL),
wherein the pillar (CL) is electrically connected to the pad (38, 41).
Regarding claim 9, Fig. 4 of Sawada disclose the semiconductor device according to claim 1 as applied above, and Fig. 4 of Sawada further discloses comprising:
a plurality of transistors (Fig. 4, plurality of transistors 31, ¶ [0023]) disposed in the second insulating layer (14),
wherein the plurality of transistors (31) are electrically connected to the pad (38, 41).
Regarding claim 10, Figs. 4-5 of Sawada disclose a semiconductor device, comprising:
a first chip (W1) including a first insulating layer (13);
a second chip (W2) bonded to the first chip (W1) and including a second insulating layer (14);
a first pad (38, 41) provided around a first bonded surface of the first chip (W1) with the second chip (W2); and
a second pad (38, 41) provided around a second bonded surface of the second chip (W2) with the first chip (W1),
wherein the first and second pads (38, 41) each have a first metal layer (38b, 41b) including a first metal (“the pad material layers 38b and 41b is a metal layer including Cu”, ¶ [0045]),
the first pad (38, 41) further includes a second metal layer (41a) disposed between the first metal layer (38b, 41b) and the first insulating layer (13),
the second pad (38, 41) further includes a third metal layer (38a) disposed between the first metal layer (38b, 41b) and the second insulating layer (14),
at least one of the second metal layer (41a) or the third metal layer (38a) include a second metal having oxidation energy lower than oxidation energy of the first metal (“the barrier metal layers 38a and 41a are Ti layers”, ¶ [0049]), and
the first metal layer (38b, 41b) further includes the second metal (The instant application discloses, in ¶ [0088], that the metal from the second metal layer (titanium) diffuses easily into the first metal layer (copper). Sawada discloses the same materials for the first, second and third metal layers. Therefore, there would inherently be some of the second metal in the first metal layer in the structure disclosed by Sawada due to the diffusion of titanium into the copper).
Regarding claim 11, Figs. 4-5 of Sawada disclose the semiconductor device according to claim 10 as applied above, and Fig. 10 of Sawada further discloses wherein at least a portion of the second metal in the first metal layer (38b, 41b) is unevenly distributed at a crystal grain boundary of the first metal layer (38b, 41b) (Fig. 10, “shows grain boundaries α between crystal grains in the pad material layers 38b and 41b, and Ti atom groups β diffusing along the grain boundaries α and the bonding face S”, ¶ [0066]).
Regarding claim 12, Figs. 4-5 of Sawada disclose the semiconductor device according to claim 10 as applied above, and Fig. 5 of Sawada further discloses wherein the first metal is copper (“the pad material layers 38b and 41b is a metal layer including Cu”, ¶ [0045]), and
the second metal includes at least one of titanium, manganese, aluminum, or magnesium titanium (“the barrier metal layers 38a and 41a are Ti layers”, ¶ [0049]).
Regarding claim 13, Fig. 5 of Sawada disclose the semiconductor device according to claim 12 as applied above, and Fig. 5 of Sawada further discloses wherein the second metal is contained in at least the second metal layer (41a),
the second metal includes at least titanium (“the barrier metal layers 38a and 41a are Ti layers”, ¶ [0049]), and
the second metal layer (41a) is a barrier metal layer (“the metal pad 38 includes a barrier metal layer 38a…, and the metal pad 41 includes a barrier metal layer 41a”, ¶ [0041]).
Claims 1, 3, 6-7, 10, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20220130855 A1).
Regarding claim 1, Figs. 1A-1B of Lee disclose a semiconductor device (Fig. 1A, semiconductor device, ¶ [0019]), comprising:
a first chip (Fig. 1A, first connection structure CNS1, ¶ [0022]) including a first insulating layer (Fig. 1A, second insulating layer 120, ¶ [0022]);
a second chip (Fig. 1A, second connection structure CNS2, first semiconductor structure SEM1, ¶ [0033]) bonded to the first chip (CNS1) and including a second insulating layer (Fig. 1A, third insulating layer 130, ¶ [0032]); and
a pad (Fig. 1B, first bonding pad BP1, second bonding pads BP2, ¶ [0032]) provided around a bonded surface between the first chip (CNS1) and the second chip (CNS2),
wherein the pad (BP1, BP2) includes a first metal layer (Fig. 1B, first conductive layer CO1, second conductive layer CO2, ¶ [0082-0083]) including a first metal (“the first conductive layer CO1 may include copper”, ¶ [0085]),
a second metal layer (Fig. 1B, first barrier layer BR1, ¶ [0082]) disposed between the first metal layer (CO1, CO2) and the first insulating layer (120), and a third metal layer (Fig. 1B, second barrier layer BR2, ¶ [0083]) disposed between the first metal layer (CO1, CO2) and the second insulating layer (130),
at least one of the second metal layer (BR1) or the third metal layer (BR2) include a second metal having oxidation energy lower than oxidation energy of the first metal (“the first conductive layer CO1 may include copper… the first and second barrier layers BR1 and BR2 may include titanium”, ¶ [0085]), and
the first metal layer (CO1, CO2) further includes the second metal (The instant application discloses, in ¶ [0088], that the metal from the second metal layer (titanium) diffuses easily into the first metal layer (copper). Lee discloses the same materials for the first, second and third metal layers. Therefore, there would inherently be some of the second metal in the first metal layer in the structure disclosed by Lee due to the diffusion of titanium into the copper).
Regarding claim 3, Figs. 1A-1B of Lee disclose the semiconductor device according to claim 1 as applied above, and Fig. 1B of Lee further discloses wherein the first metal is copper (“the first conductive layer CO1 may include copper”, ¶ [0085]), and
the second metal includes at least one of titanium, manganese, aluminum, or magnesium (“the first and second barrier layers BR1 and BR2 may include titanium”, ¶ [0085]).
Regarding claim 6, Figs. 1A-1B of Lee disclose the semiconductor device according to claim 1 as applied above, and Fig. 1B of Lee further discloses comprising:
a first via (Fig. 1B, first contact CT1, ¶ [0089]) disposed in the first insulating layer (120), connected to the pad (BP1, BP2), and having a fourth metal layer (Fig. 1B, third conductive layer CO3, ¶ [0089]) and a fifth metal layer (Fig. 1B, third barrier layer BR3, ¶ [0084]) disposed between the fourth metal layer (CO3) and the first insulating layer (120); and
a second via (Fig. 1B, second contacts CT2, ¶ [0048]) disposed in the second insulating layer (130), connected to the pad (BP1, BP2), and having a sixth metal layer (Fig. 1B, fourth conductive layer CO4, ¶ [0084]) and a seventh metal layer (Fig. 1B, fourth barrier layer BR4, ¶ [0084]) disposed between the sixth metal layer (CO4) and the first insulating layer (120).
Regarding claim 7, Fig. 1B of Lee disclose the semiconductor device according to claim 6 as applied above, and Fig. 1B of Lee further discloses wherein the second metal layer (BR1) is also interposed between the pad (BP1, BP2) and the first via (CT1).
Regarding claim 10, Figs. 1A-1B of Lee disclose a semiconductor device, comprising:
a first chip (CNS1) including a first insulating layer (120);
a second chip (CNS2) bonded to the first chip (CNS1) and including a second insulating layer (130);
a first pad (BP1, BP2) provided around a first bonded surface of the first chip (CNS1) with the second chip (CNS2); and
a second pad (BP1, BP2) provided around a second bonded surface of the second chip (CNS2) with the first chip (CNS1),
wherein the first and second pads (BP1, BP2) each have a first metal layer (CO1, CO2) including a first metal,
the first pad (BP1, BP2) further includes a second metal layer (BR1) disposed between the first metal layer (CO1, CO2) and the first insulating layer (120),
the second pad (BP1, BP2) further includes a third metal layer (BR2) disposed between the first metal layer (CO1, CO2) and the second insulating layer (130),
at least one of the second metal layer (BR1) or the third metal layer (BR2) include a second metal having oxidation energy lower than oxidation energy of the first metal (“the first conductive layer CO1 may include copper… the first and second barrier layers BR1 and BR2 may include titanium”, ¶ [0085]), and
the first metal layer (CO1, CO2) further includes the second metal (The instant application discloses, in ¶ [0088], that the metal from the second metal layer (titanium) diffuses easily into the first metal layer (copper). Lee discloses the same materials for the first, second and third metal layers. Therefore, there would inherently be some of the second metal in the first metal layer in the structure disclosed by Lee due to the diffusion of titanium into the copper).
Regarding claim 12, Figs. 1A-1B of Lee disclose the semiconductor device according to claim 10 as applied above, and Fig. 1B of Lee further discloses wherein the first metal is copper (“the first conductive layer CO1 may include copper”, ¶ [0085]), and
the second metal includes at least one of titanium, manganese, aluminum, or magnesium (“the first and second barrier layers BR1 and BR2 may include titanium”, ¶ [0085]).
Regarding claim 15, Figs. 1A-1B of Lee disclose the semiconductor device according to claim 10 as applied above, and Fig. 1B of Lee further discloses comprising:
a first via (CT1) disposed in the first insulating layer (120), connected to the pad (BP1, BP2), and having a fourth metal layer (CO3) and a fifth metal layer (BR3) disposed between the fourth metal layer (CO3) and the first insulating layer (120); and
a second via (CT2) disposed in the second insulating layer (130), connected to the pad (BP1, BP2), and having a sixth metal layer (CO4) and a seventh metal layer (BR4) disposed between the sixth metal layer (CO4) and the first insulating layer (120).
Regarding claim 16, Fig. 1B of Lee disclose the semiconductor device according to claim 15 as applied above, and Fig. 1B of Lee further discloses wherein the second metal layer (BR1) is also interposed between the pad (BP1, BP2) and the first via (CT1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220130855 A1) in view of Ishikawa et al. (US 20230361069 A1) herein after “Ishikawa”.
Regarding claim 5, Fig. 1B of Lee disclose the semiconductor device according to claim 3 as applied above, and Fig. 1B of Lee further discloses wherein the second metal is contained in at least the second metal layer (“the first and second barrier layers BR1 and BR2 may include titanium”, ¶ [0085]).
Lee fails to disclose the pad includes a barrier metal layer interposed between the second metal layer and the first insulating layer.
In the similar field of endeavor of bonded assemblies, Fig. 17D of Ishikawa discloses the pad (Fig. 17D, copper portions 774, 974, ¶ [0224-0225]) includes a barrier metal layer (Fig. 17D, metallic barrier liner 781, ¶ [0225]) interposed between the second metal layer (Fig. 17D, alloy portion 783, ¶ [0225]) and the first insulating layer (Fig. 17D, dielectric layer 770, ¶ [0092]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the pad of Lee by incorporating the barrier metal layer as disclosed by Ishikawa. The claimed barrier metal layer was known in the prior art and one skilled in the art could have combined the structure of Lee with that of Ishikawa as claimed with no change in their respective functions, and the combination would have yielded the predictable result of preventing diffusion between the metal interconnect structure and the dielectric layers. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 14, Fig. 1B of Lee disclose the semiconductor device according to claim 12 as applied above, and Fig. 1B of Lee further discloses wherein the second metal is contained in at least the second metal layer (“the first and second barrier layers BR1 and BR2 may include titanium”, ¶ [0085]).
Lee fails to disclose the pad includes a barrier metal layer interposed between the second metal layer and the first insulating layer.
In the similar field of endeavor of bonded assemblies, Fig. 17D of Ishikawa discloses the pad (774, 974) includes a barrier metal layer (781) interposed between the second metal layer (783) and the first insulating layer (770).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the pad of Lee by incorporating the barrier metal layer as disclosed by Ishikawa. The claimed barrier metal layer was known in the prior art and one skilled in the art could have combined the structure of Lee with that of Ishikawa as claimed with no change in their respective functions, and the combination would have yielded the predictable result of preventing diffusion between the metal interconnect structure and the dielectric layers. See KSR International Co. V. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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