DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,068,050. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, claim 10 of Pat. ‘050 discloses an apparatus, comprising: a plurality of processing units; a plurality of glitch detectors that are configured to detect an indication of a glitch attack on the apparatus; and a connection matrix configured to provide respective signals from the plurality of glitch detectors to at least two of the plurality of processing units.
Regarding claim 2, claim 11 of Pat. ‘050 discloses wherein the plurality of processing units each include at least one local glitch detector corresponding thereto.
Regarding claims 3 and 4, claim 12 of Pat. ‘050 discloses wherein the at least one local glitch detector comprises a voltage glitch detector, and wherein the at least one local glitch detector comprises an electromagnetic (EM) glitch detector.
Regarding claim 5, claim 13 of Pat. ‘050 discloses wherein the plurality of processing units each include at least two local glitch detectors corresponding thereto.
Regarding claim 6, claim 12 of Pat. ‘050 discloses wherein the at least two local glitch detectors include at least one voltage glitch detector configured to monitor voltage signal changes and at least one electromagnetic glitch detector configured to monitor clock signal changes.
Regarding claim 7, claim 10 of Pat. ‘050 discloses wherein the connection matrix is configured to provide respective signals from the plurality of glitch detectors to all of the plurality of processing units.
Regarding claim 8, claim 16 of Pat. 050 discloses wherein the connection matrix is configured to provide respective signals from the plurality of glitch detectors to all of the plurality of processing units.
Regarding claim 9, claim 1 of Pat. ‘050 discloses a method, comprising: detecting, by one of a plurality of glitch detectors within a memory system, an indication of a glitch attack on the memory system, wherein the memory system comprises a plurality of processing units each having at least one of the plurality of glitch detectors corresponding thereto; transmitting, via a connection matrix, the indication of the glitch attack to at least one of the plurality of processing units in addition to the processing unit to which the one of the plurality of glitch detectors corresponds; and subsequent to transmitting the indication of the glitch attack to the at least one of the plurality of processing units in addition to the processing unit to which the one of the plurality of glitch detectors corresponds, transmitting, via the at least one processing unit in addition to the processing unit to which the one of the plurality of glitch detectors corresponds, a glitch attack confirmation signal.
Regarding claim 10, claim 2 of Pat. ‘050 discloses wherein detecting the indication of the glitch attack further comprises detecting a deviation in a clock signal, a deviation in a supply voltage signal, or both.
Regarding claim 11, claim 3 of Pat. ‘050 discloses wherein the indication of the glitch attack is an interrupt signal.
Regarding claim 12, claim 4 of Pat. ‘050 discloses wherein the method includes, responsive to detecting the indication of the glitch attack, updating a status register, wherein the status register comprises a plurality of bits corresponding to respective statuses of the plurality of glitch detectors.
Regarding claim 13, claim 5 of Pat. ‘050 discloses wherein the method includes transmitting, via the connection matrix, the indication of the glitch attack to all of the plurality of processing units.
Regarding claim 14, claim 6 of Pat. 050 discloses wherein transmitting, via the connection matrix, the indication of the glitch attack comprises transmitting an interrupt signal.
Regarding claim 15, claim 6 of Pat. ‘050 discloses wherein the method includes transmitting, via the connection matrix, respective interrupt signals substantially contemporaneously to: the at least one of the plurality of processing units in addition to the processing unit to which the one of the plurality of glitch detectors corresponds; and to the processing unit to which the glitch detector corresponds.
Regarding claim 16, claim 18 of Pat. ‘050 discloses an apparatus, comprising: a plurality of processing units; a plurality of glitch detectors; and a connection matrix coupled to the plurality of glitch detectors and to at least two of the plurality of processing units, wherein the connection matrix is configured to: receive, from a particular one of the plurality of glitch detectors, an indication of a detected glitch attack; and responsive to receiving the indication of the detected glitch attack, transmit signaling indicative of the detected glitch attack to the at least two of the plurality of processing units.
Regarding claim 17, claim 13 of Pat. ‘050 discloses wherein the particular one of the glitch detectors is local to one of the at least two of the plurality of processing units.
Regarding claim 18, claim 2 of Pat. ‘050 discloses wherein the particular one of the glitch detectors is local to one of the at least two of the plurality of processing units.
Regarding claim 19, claim 19 of Pat. ‘050 discloses comprising alarm circuitry coupled to the at least two of the plurality of processing units.
Regarding claim 20, claim 10 of Pat. ‘050 discloses comprising alarm circuitry coupled to the at least two of the plurality of processing units.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 9, 11, 13, 14, 16, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lyon et al. (US Pat. 4,545,013).
Regarding claim 1, Fig. 1 and Fig. 2 of Lyon discloses an apparatus, comprising:
a plurality of processing units [12, 22a to 22n, Fig. 1];
a plurality of glitch detectors [within 138, Fig. 2] that are configured to detect an indication of a glitch attack on the apparatus [col. 11, lines 28 to 37]; and
a connection matrix configured to provide respective signals from the plurality of glitch detectors to at least two of the plurality of processing units [as discloses in col. 11, lines 28 to 37, signals from glitch detectors are sent to the processing units. Therefore, a connection matrix is inherent].
Regarding claim 3, Fig. 2 of Lyon discloses wherein the at least one local glitch detector comprises a voltage glitch detector [col. 11, lines 28 to 37].
Regarding claims 9 and 16, Fig. 1 and Fig. 2 of Lyon discloses a comprising:
detecting, by one of a plurality of glitch detectors [138, Fig. 2] within a memory system, an indication of a glitch attack on the memory system [col. 11, lines 28 to 37], wherein the memory system comprises a plurality of processing units [100, Fig. 2 and 12, 22a, and 22n in Fig. 1] each having at least one of the plurality of glitch detectors corresponding thereto;
transmitting, via a connection matrix, the indication of the glitch attack to at least one of the plurality of processing units in addition to the processing unit to which the one of the plurality of glitch detectors corresponds [as discloses in col. 11, lines 28 to 37, signals from glitch detectors are sent to the processing units. Therefore, a connection matrix is inherent]; and
subsequent to transmitting the indication of the glitch attack to the at least one of the plurality of processing units in addition to the processing unit to which the one of the plurality of glitch detectors corresponds, transmitting, via the at least one processing unit in addition to the processing unit to which the one of the plurality of glitch detectors corresponds, a glitch attack confirmation signal [as discloses in col. 11, lines 28 to 37, the glitch signals are sent into two processors [100 and 104]. Therefore, glitch signal is sent to additional processor].
Regarding claim 11, Fig. 2 of Lyon discloses wherein the indication of the glitch attack is an interrupt signal [152].
Regarding claim 13, Fig. 2 of Lyon discloses wherein the method includes transmitting, via the connection matrix, the indication of the glitch attack to all of the plurality of processing units [100 and 104A].
Regarding claim 14, Fig. 2 of Lyon discloses wherein transmitting, via the connection matrix, the indication of the glitch attack comprises transmitting an interrupt signal [col. 11, lines 27 to 38].
Regarding claim 17, Fig. 2 of Lyon discloses wherein the particular one of the glitch detectors [138] is local to one of the at least two of the plurality of processing units [100 and 104A, col. 11, lines 28 to 37].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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