Prosecution Insights
Last updated: October 02, 2026
Application No. 18/808,560

VOLTAGE SUPPLY CIRCUITS, THREE-DIMENSIONAL MEMORY DEVICES, PERIPHERAL CIRCUIT, AND METHODS FOR ADJUSTING VOLTAGE SUPPLY CIRCUIT

Non-Final OA §102§103
Filed
Aug 19, 2024
Priority
Apr 20, 2022 — continuation of 12/100,457
Examiner
KING, DOUGLAS
Art Unit
Tech Center
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
598 granted / 746 resolved
+20.2% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
19 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
45.2%
+5.2% vs TC avg
§102
27.6%
-12.4% vs TC avg
§112
20.6%
-19.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 746 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered. Election/Restrictions Applicant’s election without traverse of invention ‘I’ (claims 1-18) in the reply filed on 8/21/26 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 11-15 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (US 2008/0018377). Regarding claim 1, Chung discloses a voltage supply circuit, comprising: a temperature compensation circuit comprising: a comparator circuit (150); and a compensation controller circuit (155, 158) coupled to a comparator output terminal of the comparator circuit; and a voltage regulation circuit comprising: an amplifier (142); and a voltage divider (141), wherein the voltage divider coupled to the compensation controller circuit and the amplifier. Regarding claim 2, Chung discloses the voltage supply circuit of claim 1, wherein the comparator circuit comprises: a first comparator input terminal receiving a device temperature value (VL for example); and a second comparator input terminal receiving a reference value (Vref), wherein when the device temperature value is lower than the reference value, a comparison result output by the comparator output terminal of the comparator circuit comprises a comparison flag (output of 157 to 158) to the compensation controller circuit. Regarding claim 11, Chung discloses the voltage supply circuit of claim 1, wherein the voltage divider comprises: a resistor string comprising a first resistor (R13 for example) and a second resistor (R15 for example) in a series connection; a first switch (T12) coupled to two ends of the first resistor; and a second switch (T14) coupled to two ends of the second resistor. Regarding claim 12, Chung discloses the voltage supply circuit of claim 11, wherein a voltage level output by the voltage regulation circuit is adjustable by switching on/off of at least one of the first switch or the second switch (see paragraphs 0029-0034). Regarding claim 13, Chung discloses a memory device, comprising: a memory cell array (see Figure 1, 110) for storing data; and a peripheral circuit (120) coupled to the memory cell array and comprising a voltage supply circuit, the voltage supply circuit comprising: a temperature compensation circuit comprising: a comparator circuit; and a compensation controller circuit coupled to a comparator output terminal of the comparator circuit; and a voltage regulation circuit comprising: an amplifier; and a voltage divider, wherein the voltage divider coupled to the compensation controller circuit and the amplifier (see rejection of claim 1 above, Figures 1-3). Regarding claim 14, Chung discloses the memory device of claim 13, wherein the comparator circuit comprises: a first comparator input terminal receiving a device temperature value; and a second comparator input terminal receiving a reference value, wherein when the device temperature value is lower than the reference value, a comparison result output by the comparator output terminal of the comparator circuit comprises a comparison flag to the compensation controller circuit (see rejection of claim 2 above). Regarding claim 17, Chung discloses the memory device of claim 13, wherein the voltage divider comprises: a resistor string comprising a first resistor and a second resistor in a series connection; a first switch coupled to two ends of the first resistor; and a second switch coupled to two ends of the second resistor (see rejection of claim 11 above). Regarding claim 18, Chung discloses the memory device of claim 17, wherein a voltage level output by the voltage regulation circuit is adjustable by switching on/off of at least one of the first switch or the second switch (see rejection of claim 12 above). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 3 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung. Regarding claims 3 and 15, Chung discloses the voltage supply circuit of claim 2, wherein the compensation controller circuit comprises: a first compensation input terminal receiving the comparison result (input to inverter); but fails to teach a second compensation input terminal receiving a compensation enable signal, wherein the comparison result and the compensation enable signal jointly enable the compensation controller circuit. However, this describes an enable gating circuit. Such configurations were common and well-known at the time of filing and, it would have been obvious to one having ordinary skill at the time of filing to provide such a logic gate in order to be able to disable the compensation signal for example to test the circuitry, enter a lower power mode, etc. Regarding claim 15, Chung discloses the memory device of claim 14, wherein the compensation controller circuit comprises: a first compensation input terminal receiving the comparison result; a second compensation input terminal receiving a compensation enable signal; and a third compensation input terminal receiving a compensation value control signal, wherein the compensation controller circuit generates a voltage control signal to the voltage regulation circuit jointly according to the comparison result, the compensation enable signal, and the compensation value control signal. Allowable Subject Matter Claims 4-10 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claims 4 and 16, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including a third compensation input terminal receiving a compensation value control signal; and wherein the compensation controller circuit generates a voltage control signal to the voltage regulation circuit jointly according to the comparison result, the compensation enable signal, and the compensation value control signal. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The remaining cited and attached references teach various embodiments of compensated voltage regulators. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS KING/Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Aug 19, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
84%
With Interview (+4.3%)
2y 6m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 746 resolved cases by this examiner. Grant probability derived from career allowance rate.

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