Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated September 10, 2026, claims 1-20 are active in
this application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 12073899 [‘899]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘899
1. A device, comprising: memory cells; and a logic circuit configured to: receive data representative of signal and noise characteristics of the memory cells, the data representative of signal and noise characteristics determined during reading the memory cells and before data stored in the memory cell is determined via the reading; determine, based on the signal and noise characteristics, a read voltage to read the memory cells; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.
1. A device, comprising: memory cells; and a logic circuit configured to: receive data representative of signal and noise characteristics of the memory cells; determine, based on the signal and noise characteristics, a read voltage to read the memory cells; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells; and a read circuit configured to apply voltages to the memory cells to determine states of the memory cells under the voltages applied to the memory cells; and an integrated circuit package configured to enclose the memory cells, the logic circuit, and the read circuit.
2. The device of claim 1, wherein the logic circuit is further configured to: measure, using the read circuit, the signal and noise characteristics of the memory cells; and determine, based on the signal and noise characteristics, a bit error rate in data retrievable from the memory cells using the read voltage, wherein the amount of charge loss is determined based at least in part on the bit error rate.
2. The device of claim 1, further comprising: a read circuit configured to apply voltages to the memory cells to determine states of the memory cells under the voltages applied to the memory cells; and an integrated circuit package configured to enclose the memory cells, the logic circuit, and the read circuit.
See claim 1. “…a read circuit configured to apply voltages to the memory cells to determine states of the memory cells under the voltages applied to the memory cells; and an integrated circuit package configured to enclose the memory cells, the logic circuit, and the read circuit.”
3. The device of claim 2, wherein the logic circuit is further configured to: measure, using the read circuit, the signal and noise characteristics of the memory cells; and determine, based on the signal and noise characteristics, a bit error rate in data retrievable from the memory cells using the read voltage, wherein the amount of charge loss is determined based at least in part on the bit error rate.
2. The device of claim 1, wherein the logic circuit is further configured to: measure, using the read circuit, the signal and noise characteristics of the memory cells; and determine, based on the signal and noise characteristics, a bit error rate in data retrievable from the memory cells using the read voltage, wherein the amount of charge loss is determined based at least in part on the bit error rate.
4. The device of claim 3, wherein the logic circuit is further configured to track the read voltage in relation with the amount of charge loss.
3. The device of claim 2, wherein the logic circuit is further configured to track the read voltage in relation with the amount of charge loss.
5. The device of claim 3, wherein the logic circuit is further configured to track, based at least in part on the read voltage and the amount of charge loss, changes in read voltage in relation with charge loss.
4. The device of claim 2, wherein the logic circuit is further configured to track, based at least in part on the read voltage and the amount of charge loss, changes in read voltage in relation with charge loss.
6. The device of claim 3, wherein the signal and noise characteristics are configured to count differences over a plurality of test voltages, each count difference over two adjacent test voltages being a difference between: a first count of a subset of the memory cells having a predetermined state when a first one of the adjacent test voltages is applied on the memory cells, and a second count of a subset of the memory cells having the predetermined state when a second one of the adjacent test voltages is applied on the memory cells.
5. The device of claim 2, wherein the signal and noise characteristics are configured to count differences over a plurality of test voltages, each count difference over two adjacent test voltages being a difference between: a first count of a subset of the memory cells having a predetermined state when a first one of the adjacent test voltages is applied on the memory cells, and a second count of a subset of the memory cells having the predetermined state when a second one of the adjacent test voltages is applied on the memory cells.
7. The device of claim 6, wherein the logic circuit is configured to determine the read voltage based on a local minimum of a distribution of count difference over the plurality of test voltages.
6. The device of claim 5, wherein the logic circuit is configured to determine the read voltage based on a local minimum of a distribution of count difference over the plurality of test voltages.
8. The device of claim 7, wherein the logic circuit is configured to calculate the amount of charge loss based on the read voltage.
7. The device of claim 6, wherein the logic circuit is configured to calculate the amount of charge loss based on the read voltage.
9. The device of claim 8, wherein the logic circuit is further configured to: generate, using the read circuit, first data retrieved from the memory cells using the read voltage; decode, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and count bit errors in the first data identified using the error detection and recovery technique.
8. The device of claim 7, wherein the logic circuit is further configured to: generate, using the read circuit, first data retrieved from the memory cells using the read voltage; decode, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and count bit errors in the first data identified using the error detection and recovery technique.
10. The device of claim 8, wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.
9. The device of claim 7, wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.
As can be seen from the above table, similar to claim 1 of the present application, claim 1
of patent ‘899 recites “A device, comprising: memory cells; and a logic circuit configured to: receive data representative of signal and noise characteristics of the memory cells; determine, based on the signal and noise characteristics, a read voltage to read the memory cells; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells…” Unlike claim 1 of the patent, claim 1 of the application specifies when the metrics are determined (during reading, prior to extracting the final data). Claim 1 of the patent does not explicitly state this timing. However, this is considered an inherent or obvious variation, as the characteristics must necessarily be measured to evaluate the read voltage. Although the claim languages are not identical, claim 1 of the patent is more limited and thus would encompass all limitations of claim 1 of the application. Thus, the patent protections have been granted to the earlier filed patent application.
It is noted that the application recites, “The signal and noise characteristics must be determined "during reading the memory cells."; while claim 2 of patent ‘899 states that the logic circuit is configured to "measure, using the read circuit, the signal and noise characteristics of the memory cells." Activating and utilizing the "read circuit" to measure characteristics of the memory cells is, by definition, an act of reading or a component of the reading process. A read circuit cannot measure the characteristics of a memory cell without performing a read operation on that cell. Therefore, measuring characteristics "using the read circuit" satisfies the limitation of doing so "during reading."
Additionally, it is noted that the application recites, “The characteristics must be determined "before data stored in the memory cell is determined via the reading.", while claim 2 of the patent ‘899 states that the system will "determine, based on the signal and noise characteristics, a bit error rate in data retrievable from the memory cells..." The patent specifically uses the term “retrievable” rather than “retrieved” or “determined”. By evaluating a BER on data that is retrievable means the system is analyzing the quality of the physical signal (the signal-to-noise ratio) to predict errors prior to finalizing or outputting the actual underlying data bits. Since the data is still classified as “retrievable,” the final determination of the data stored in the memory cell has not yet occurred at the time the signal and noise characteristics are being measured and processed.
Therefore, Applicant’s arguments regarding the patent ‘899 fails to recite determining signal and noise characteristics during reading but before stored data is determined is unpersuasive.
Again, the patent ‘899 specifically discloses measuring signal and noise characteristics “using the reading circuit,” which inherently occurs during a reading operation. Further, the patent ‘899 utilizes these measurements to determine a bit error rate in data that is “retrievable” from the memory cells. Because the data is identified as retrievable rather than finalized (retrieved), the read circuit’s measurement of signal and noise characteristics logically and temporally precedes the final determination of the stored data bits. Accordingly, patent 899 teaches all the claimed recitations.
For similar reasons, claims 2-10 are rejected over claims 1-9 of patent ‘899.
Claims 11-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-16 of U.S. Patent No. 12073899 [‘899]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘899
11. A method, comprising: receiving, in a memory device, data representative of signal and noise characteristics of memory cells in the memory device, the data representative of signal and noise characteristics determined during reading the memory cells and before data stored in the memory cell is determined via the reading; determining, by the memory device based on the signal and noise characteristics, a read voltage; determining data stored in the memory device from states of the memory cells subjected to the read voltage; and calculating, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.
10. A method, comprising: receiving, in a memory device, data representative of signal and noise characteristics of memory cells in the memory device; determining, by the memory device based on the signal and noise characteristics, a read voltage; determining data stored in the memory device from states of the memory cells subjected to the read voltage; calculating, based at least in part on the characteristics, an amount of charge loss in the memory cells; and applying a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively.
11. The method of claim 10, further comprising: determining a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and computing count differences between the counts for adjacent ones of the plurality of test voltages, wherein the signal and noise characteristics are configured to identify the count differences.
12. The method of claim 11, further comprising: applying a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively; determining a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and computing count differences between the counts for adjacent ones of the plurality of test voltages, wherein the signal and noise characteristics are configured to identify the count differences.
See claim 10 and claim 11. In claim 10, “… applying a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively.”
11. The method of claim 10, further comprising: determining a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and computing count differences between the counts for adjacent ones of the plurality of test voltages, wherein the signal and noise characteristics are configured to identify the count differences.
13. The method of claim 12, further comprising: generating first data represented by states of the memory cells when subjected to at least the read voltage; decoding, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and determine, based on the decoding, a bit error rate in the first data to calculate the amount of charge loss.
12. The method of claim 11, further comprising: generating first data represented by states of the memory cells when subjected to at least the read voltage; decoding, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and determine, based on the decoding, a bit error rate in the first data to calculate the amount of charge loss.
14. The method of claim 13, further comprising: tracking the read voltage in relation with the amount of charge loss.
13. The method of claim 12, further comprising: tracking the read voltage in relation with the amount of charge loss.
15. The method of claim 13, further comprising: tracking, based at least in part on the read voltage and the amount of charge loss, changes in read voltages of the memory cells.
14. The method of claim 12, further comprising: tracking, based at least in part on the read voltage and the amount of charge loss, changes in read voltages of the memory cells.
16. The method of claim 13, wherein the read voltage is determines based on an estimate of local minimum of the count differences over the plurality of test voltages.
15. The method of claim 12, wherein the read voltage is determines based on an estimate of local minimum of the count differences over the plurality of test voltages.
17. The method of claim 16, wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.
16. The method of claim 15, wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.
As can be seen from the above table, similar to claim 11 of the present application, claim 10 of patent ‘899 recites “A method, comprising: receiving, in a memory device, data representative of signal and noise characteristics of memory cells in the memory device; determining, by the memory device based on the signal and noise characteristics, a read voltage; determining data stored in the memory device from states of the memory cells subjected to the read voltage; and calculating, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.…” Unlike claim 10 of the patent, claim 11 of the application specifies when the metrics are determined (during reading, prior to extracting the final data). Claim 10 of the patent does not explicitly state this timing. However, this is considered an inherent or obvious variation, as the characteristics must necessarily be measured to evaluate the read voltage. Although the claim languages are not identical, claim 10 of the patent is more limited and thus would encompass all limitations of claim 11 of the application. Thus, the patent protections have been granted to the earlier filed patent application.
Patent ‘899 recites, "determining a plurality of counts for the plurality of test voltages... when the memory cells are subjected to the respective test voltage." Subjecting memory cells to test voltages to see if they meet a predetermined state is a memory read operation. Therefore, this step occurs "during reading the memory cells." Additionally, patent ‘899 states that you "compute count differences" and that "the signal and noise characteristics are configured to identify the count differences." You cannot compute these differences or identify these characteristics until after you have gathered the raw voltage counts (the read phase). Because patent ‘899 is calculating these count differences to map out the signal and noise characteristics first, it is functionally doing so before the final data values stored in those cells are determined and output via the reading process.
For similar reasons, claims 12-17 are rejected over claims 10-16 of patent ‘899.
Allowable Subject Matter
Claims 18-20 are allowable over the prior art of record.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 18, determine a bit error rate in second data retrievable from the memory cells using the read voltage; and calculate, based at least in part on the signal and noise characteristics and based at least in part on the bit error rate, an amount of charge loss in the memory cells.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 September 21, 2026
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