Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated May 8, 2026, claims 1-20 are active in
this application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 12073899 [‘899]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘899
1. A device, comprising: memory cells; and a logic circuit configured to: receive data representative of signal and noise characteristics of the memory cells, the data representative of signal and noise characteristics determined during reading the memory cells and before data stored in the memory cell is determined via the reading; determine, based on the signal and noise characteristics, a read voltage to read the memory cells; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.
1. A device, comprising: memory cells; and a logic circuit configured to: receive data representative of signal and noise characteristics of the memory cells; determine, based on the signal and noise characteristics, a read voltage to read the memory cells; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells; and a read circuit configured to apply voltages to the memory cells to determine states of the memory cells under the voltages applied to the memory cells; and an integrated circuit package configured to enclose the memory cells, the logic circuit, and the read circuit.
2. The device of claim 1, further comprising: a read circuit configured to apply voltages to the memory cells to determine states of the memory cells under the voltages applied to the memory cells; and an integrated circuit package configured to enclose the memory cells, the logic circuit, and the read circuit.
See claim 1. “…a read circuit configured to apply voltages to the memory cells to determine states of the memory cells under the voltages applied to the memory cells; and an integrated circuit package configured to enclose the memory cells, the logic circuit, and the read circuit.”
3. The device of claim 2, wherein the logic circuit is further configured to: measure, using the read circuit, the signal and noise characteristics of the memory cells; and determine, based on the signal and noise characteristics, a bit error rate in data retrievable from the memory cells using the read voltage, wherein the amount of charge loss is determined based at least in part on the bit error rate.
2. The device of claim 1, wherein the logic circuit is further configured to: measure, using the read circuit, the signal and noise characteristics of the memory cells; and determine, based on the signal and noise characteristics, a bit error rate in data retrievable from the memory cells using the read voltage, wherein the amount of charge loss is determined based at least in part on the bit error rate.
4. The device of claim 3, wherein the logic circuit is further configured to track the read voltage in relation with the amount of charge loss.
3. The device of claim 2, wherein the logic circuit is further configured to track the read voltage in relation with the amount of charge loss.
5. The device of claim 3, wherein the logic circuit is further configured to track, based at least in part on the read voltage and the amount of charge loss, changes in read voltage in relation with charge loss.
4. The device of claim 2, wherein the logic circuit is further configured to track, based at least in part on the read voltage and the amount of charge loss, changes in read voltage in relation with charge loss.
6. The device of claim 3, wherein the signal and noise characteristics are configured to count differences over a plurality of test voltages, each count difference over two adjacent test voltages being a difference between: a first count of a subset of the memory cells having a predetermined state when a first one of the adjacent test voltages is applied on the memory cells, and a second count of a subset of the memory cells having the predetermined state when a second one of the adjacent test voltages is applied on the memory cells.
5. The device of claim 2, wherein the signal and noise characteristics are configured to count differences over a plurality of test voltages, each count difference over two adjacent test voltages being a difference between: a first count of a subset of the memory cells having a predetermined state when a first one of the adjacent test voltages is applied on the memory cells, and a second count of a subset of the memory cells having the predetermined state when a second one of the adjacent test voltages is applied on the memory cells.
7. The device of claim 6, wherein the logic circuit is configured to determine the read voltage based on a local minimum of a distribution of count difference over the plurality of test voltages.
6. The device of claim 5, wherein the logic circuit is configured to determine the read voltage based on a local minimum of a distribution of count difference over the plurality of test voltages.
8. The device of claim 7, wherein the logic circuit is configured to calculate the amount of charge loss based on the read voltage.
7. The device of claim 6, wherein the logic circuit is configured to calculate the amount of charge loss based on the read voltage.
9. The device of claim 8, wherein the logic circuit is further configured to: generate, using the read circuit, first data retrieved from the memory cells using the read voltage; decode, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and count bit errors in the first data identified using the error detection and recovery technique.
8. The device of claim 7, wherein the logic circuit is further configured to: generate, using the read circuit, first data retrieved from the memory cells using the read voltage; decode, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and count bit errors in the first data identified using the error detection and recovery technique.
10. The device of claim 8, wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.
9. The device of claim 7, wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.
As can be seen from the above table, similar to claim 1 of the present application, claim 1 of patent ‘899 recites “A device, comprising: memory cells; and a logic circuit configured to: receive data representative of signal and noise characteristics of the memory cells; determine, based on the signal and noise characteristics, a read voltage to read the memory cells; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells…” Unlike claim 1 of the patent, claim 1 of the application specifies when the metrics are determined (during reading, prior to extracting the final data). Claim 1 of the patent does not explicitly state this timing. However, this is considered an inherent or obvious variation, as the characteristics must necessarily be measured to evaluate the read voltage. Although the claim languages are not identical, claim 1 of the patent is more limited and thus would encompass all limitations of claim 1 of the application. Thus, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 2-10 are rejected over claims 1-9 of patent ‘899.
Claims 11-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10-16 of U.S. Patent No. 12073899 [‘899]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘899
11. A method, comprising: receiving, in a memory device, data representative of signal and noise characteristics of memory cells in the memory device, the data representative of signal and noise characteristics determined during reading the memory cells and before data stored in the memory cell is determined via the reading; determining, by the memory device based on the signal and noise characteristics, a read voltage; determining data stored in the memory device from states of the memory cells subjected to the read voltage; and calculating, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.
10. A method, comprising: receiving, in a memory device, data representative of signal and noise characteristics of memory cells in the memory device; determining, by the memory device based on the signal and noise characteristics, a read voltage; determining data stored in the memory device from states of the memory cells subjected to the read voltage; calculating, based at least in part on the characteristics, an amount of charge loss in the memory cells; and applying a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively.
12. The method of claim 11, further comprising: applying a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively; determining a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and computing count differences between the counts for adjacent ones of the plurality of test voltages, wherein the signal and noise characteristics are configured to identify the count differences.
See claim 10 and claim 11. In claim 10, “… applying a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively.”
11. The method of claim 10, further comprising: determining a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and computing count differences between the counts for adjacent ones of the plurality of test voltages, wherein the signal and noise characteristics are configured to identify the count differences.
13. The method of claim 12, further comprising: generating first data represented by states of the memory cells when subjected to at least the read voltage; decoding, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and determine, based on the decoding, a bit error rate in the first data to calculate the amount of charge loss.
12. The method of claim 11, further comprising: generating first data represented by states of the memory cells when subjected to at least the read voltage; decoding, using an error detection and recovery technique, the first data, to identify second data stored in the memory cells; and determine, based on the decoding, a bit error rate in the first data to calculate the amount of charge loss.
14. The method of claim 13, further comprising: tracking the read voltage in relation with the amount of charge loss.
13. The method of claim 12, further comprising: tracking the read voltage in relation with the amount of charge loss.
15. The method of claim 13, further comprising: tracking, based at least in part on the read voltage and the amount of charge loss, changes in read voltages of the memory cells.
14. The method of claim 12, further comprising: tracking, based at least in part on the read voltage and the amount of charge loss, changes in read voltages of the memory cells.
16. The method of claim 13, wherein the read voltage is determines based on an estimate of local minimum of the count differences over the plurality of test voltages.
15. The method of claim 12, wherein the read voltage is determines based on an estimate of local minimum of the count differences over the plurality of test voltages.
17. The method of claim 16, wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.
16. The method of claim 15, wherein the memory cells are configured to store multiple bits per memory cell and have a plurality of voltage levels for reading; and the read voltage is at a highest level among the plurality of voltage levels.
As can be seen from the above table, similar to claim 11 of the present application, claim 10 of patent ‘899 recites “A method, comprising: receiving, in a memory device, data representative of signal and noise characteristics of memory cells in the memory device; determining, by the memory device based on the signal and noise characteristics, a read voltage; determining data stored in the memory device from states of the memory cells subjected to the read voltage; and calculating, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.…” Unlike claim 10 of the patent, claim 11 of the application specifies when the metrics are determined (during reading, prior to extracting the final data). Claim 10 of the patent does not explicitly state this timing. However, this is considered an inherent or obvious variation, as the characteristics must necessarily be measured to evaluate the read voltage. Although the claim languages are not identical, claim 10 of the patent is more limited and thus would encompass all limitations of claim 11 of the application. Thus, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 12-17 are rejected over claims 10-16 of patent ‘899.
Claims 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17-19 of U.S. Patent No. 12073899 [‘899]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘899
18. An apparatus, comprising: a memory device enclosed within an integrated circuit package, the memory device having: memory cells; a first circuit operable to apply voltages to the memory cells to determine states of the memory cells subjected to the voltages; and a second circuit configured to: generate, using the first circuit, data representative of signal and noise characteristics of the memory cells; determine, based on the signal and noise characteristics, a read voltage of the memory cells; and generate, using the first circuit, first data representative states of the memory cells subject to voltages including the read voltage; wherein the apparatus is further configured to: determine second data stored in the memory cells based on the first data; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.
17. An apparatus, comprising: a processing device; and a memory device enclosed within an integrated circuit package and connected to the processing device, the memory device having: memory cells; a first circuit operable to apply voltages to the memory cells to determine states of the memory cells subjected to the voltages; a second circuit configured to: generate, using the first circuit, data representative of signal and noise characteristics of the memory cells; determine, based on the signal and noise characteristics, a read voltage of the memory cells; and generate, using the first circuit, first data representative states of the memory cells subject to voltages including the read voltage wherein the apparatus is further configured to: determine second data stored in the memory cells based on the first data; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.
19. The apparatus of claim 18, wherein the first circuit is further configured to: apply a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively; determine a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and compute count differences between the counts for adjacent ones of the plurality of test voltages; wherein the signal and noise characteristics are configured to identify the count differences; and wherein the memory device is configured to determine the read voltage based on an estimate of local minimum of the count differences over the plurality of test voltages.
18. The apparatus of claim 17, wherein the first circuit is further configured to: apply a plurality of test voltages to the memory cells to determine states of the memory cells subjected to the test voltages respectively; determine a plurality of counts for the plurality of test voltages respectively, wherein each count in the plurality of counts for a respective test voltage is a number of a subset of the memory cells having a predetermined state when the memory cells are subjected to the respective test voltage; and compute count differences between the counts for adjacent ones of the plurality of test voltages; wherein the signal and noise characteristics are configured to identify the count differences; and wherein the memory device is configured to determine the read voltage based on an estimate of local minimum of the count differences over the plurality of test voltages.
20. The apparatus of claim 19, further configured to track, based at least in part on the read voltage and the amount of charge loss, changes in read voltages of the memory cells.
19. The apparatus of claim 18, is further configured to track, based at least in part on the read voltage and the amount of charge loss, changes in read voltages of the memory cells.
As can be seen from the above table, similar to claim 18 of the present application, claim 19 of patent ‘899 recites “An apparatus, comprising: a memory device enclosed within an integrated circuit package, the memory device having: memory cells; a first circuit operable to apply voltages to the memory cells to determine states of the memory cells subjected to the voltages; and a second circuit configured to: generate, using the first circuit, data representative of signal and noise characteristics of the memory cells; determine, based on the signal and noise characteristics, a read voltage of the memory cells; and generate, using the first circuit, first data representative states of the memory cells subject to voltages including the read voltage; wherein the apparatus is further configured to: determine second data stored in the memory cells based on the first data; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells.” Unlike claim 18 of the application, claim 19 of the patent further recites additional limitations. Although the claim languages are not identical, claim 19 of the patent is more limited and thus would encompass all limitations of claim 18 of the application. Thus, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 19-20 are rejected over claims 17-19 of patent ‘899.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parthasarathy et al. [US Patent # 11,227,666].
With respect to claim 1, Parthasarathy et al. disclose a device, comprising: memory cells; and a logic circuit configured to ["A memory sub-system to track charge loss..." – abstract (Both, the application and the patent, establish the fundamental architecture. The "memory sub-system" inherently includes the "memory cells" and the processing "logic circuit" necessary to evaluate them.)]: receive data representative of signal and noise characteristics of the memory cells ["measure signal and noise characteristics of a group of memory cells" -abstract (Both, the application and the patent, describe capturing signal/noise telemetry.)], the data representative of signal and noise characteristics determined during reading the memory cells and before data stored in the memory cell is determined via the reading ["determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage." – abstract (Both, the application and the patent, require reading the memory array to capture the analog characteristics.; describes evaluating the signal/noise characteristics dynamically during the pre-computation stages of a read operation (before resolving the actual hard/soft bit value). The patent mirrors this by utilizing the bit error rate and data read via the optimized voltage, which functionally requires assessing the cell's analog state (noise/margin) prior to or during the final hard-decision data extraction. The assessment of "signal and noise characteristics" during a read cycle intrinsically involves reading the cell's state to evaluate its health before finalizing the stored data value.)] ; determine, based on the signal and noise characteristics, a read voltage to read the memory cells ["calculate an optimized read voltage of the group of memory cells” – abstract (Both, the application and the patent, reflect the exact same closed-loop feedback mechanism: processing signal and noise characteristics to figure out the most effective read voltage.)]; and calculate, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells ["determine an amount of charge loss in the group of memory cells" – abstract (These are identical functions. Both, the application and the patent, utilize the evaluated characteristics to mathematically quantify the charge degradation.)].
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parthasarathy et al. [US Patent # 11,227,666].
With respect to claim 11, Parthasarathy et al. disclose a method, comprising: receiving, in a memory device, data representative of signal and noise characteristics of memory cells ["measure signal and noise characteristics of a group of memory cells" -abstract (Both, the application and the patent, describe capturing signal/noise telemetry.)] in the memory device ["A memory sub-system to track charge loss..." – abstract (Both, the application and the patent, establish the fundamental architecture. The "memory sub-system" inherently includes the "memory cells" and the processing "logic circuit" necessary to evaluate them.)], the data representative of signal and noise characteristics determined during reading the memory cells and before data stored in the memory cell is determined via the reading ["determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage." – abstract (Both, the application and the patent, require reading the memory array to capture the analog characteristics.; describes evaluating the signal/noise characteristics dynamically during the pre-computation stages of a read operation (before resolving the actual hard/soft bit value). The patent mirrors this by utilizing the bit error rate and data read via the optimized voltage, which functionally requires assessing the cell's analog state (noise/margin) prior to or during the final hard-decision data extraction. The assessment of "signal and noise characteristics" during a read cycle intrinsically involves reading the cell's state to evaluate its health before finalizing the stored data value.)]; determining, by the memory device based on the signal and noise characteristics, a read voltage ["calculate an optimized read voltage of the group of memory cells” – abstract (Both, the application and the patent, reflect the exact same closed-loop feedback mechanism: processing signal and noise characteristics to figure out the most effective read voltage.)]; determining data stored in the memory device from states of the memory cells subjected to the read voltage [This is standard, inherent operation for any memory device. Once a read voltage is applied to the cell, the device senses the cell's threshold state and resolves it into stored 1s or 0s.]; and calculating, based at least in part on the signal and noise characteristics, an amount of charge loss in the memory cells ["determine an amount of charge loss in the group of memory cells" – abstract (These are identical functions. Both, the application and the patent, utilize the evaluated characteristics to mathematically quantify the charge degradation.)].
Remarks
Applicant's amendment necessitated the new ground(s) of rejection
presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 June 7, 2026
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