DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/16/2026 has been entered.
Response to Arguments
Applicant's arguments filed on 04/16/2026 have been fully considered but they are not persuasive.
Applicant argues: “In this response, claims 1, 11, and 20 are amended for clarification purposes and not for overcoming the cited art.”
Examiner agrees, the amendments do not overcome the cited art.
Applicant argues: “The Office has failed to perform the required analysis of each and every limitation in Applicant's claims and further has failed provide any evidence that the cited art discloses or suggests each and every limitation in Applicant's claims …”
Examiner notes that these arguments are unfounded because the reasons for rejection provide a lengthy analysis of each claim element and cumulative reasons for rejection found on the record in order to provide compact prosecution.
Examiner also notes that in the priority application, Applicant’s representative relied on Examiner’s thorough analysis and suggestions to arrive at the allowed claim language. Examiner suggests thoroughly reviewing the record to identify potentially allowable subject matter.
Applicant argues: “Notably, the Office has failed to properly consider that Applicant's claims recite, inter alia, a multi-sensitivity target "formed with at least two sub-targets having periodic patterns arranged orthogonal to each other and having different sensitivities to a characteristic of interest."”
Examiner notes that Applicant’s representative failed to thoroughly read the cumulative reasons for rejection of this claim element. For purposes of compact prosecution, multiple reasons for rejection may be provided for a claim or a part of the claim. The rejection reasons are cumulative, and Applicant should review all the stated reasons as guides to improving the claim language and advancing the prosecution toward an allowance.
Applicant argues: “In rejecting the claims, the Office disregards the above claim language because, according to the Office, "this element limits how the metrology target is formed, however the method claim is not a method of forming a metrology target" and does not affect the claimed method. Office Action at 6. The Office's analysis is legally deficient because claim 1 affirmatively requires that the input image to be used for training the neural network possesses the recited structural and functional properties ("an input image of a metrology target. ... formed with at least two subtargets having periodic patterns arranged orthogonal to each other and having different sensitivities to a characteristic of interest").”
Examiner notes that Applicant fails to address the specific and cumulative reasons for rejection provided for this claim element. As noted in the reasons for rejection below, the methods of the prior art train a neural network on substantively similar lithography elements having substantively similar characteristics of interest that exhibit substantively similar sensitivities.
Applicant argues: “Yet, the Office neither does not contend that claims 2-7 and 9 are "not a method of forming a metrology target" nor does the Office give claims 2-7 and 9 any patentable weight for reciting a "forming" step, despite the Office alleging that claim 1 is not a method of forming a metrology target. As such, the Office's assertion that "the method claim is not a method of forming a metrology target" is inconsistent with Applicant's claims.”
Examiner notes that this argument is not clear. Claim 1 does not recite “forming” and thus it is not limited to it; Claim 2 recites “forming” and it is rejected accordingly. See reasons for rejection below.
Applicant argues: “Thus, a claim limitation cannot be disregarded or treated as non-limiting simply because the Office deems it non-essential. Applicant's claims define a required input to the method and thus provide further meaning to the claims. Indeed, claim 1 expressly requires that the input image be of a multi-sensitivity metrology target formed with at least two sub-targets having specified periodic arrangements and different sensitivities, and then trains a neural network based on these features having different sensitivities.”
Examiner notes that most semiconductor devices can be characterized as formed with at least two sub-targets having periodic patterns arranged orthogonal to each other and having different sensitivities to a characteristic of interest. Training the neural network on common lithography features does not differentiate the claim from the prior art.
Applicant argues: “As such, the Office alleges that the semiconductor features "naturally [have] multiple sensitivities to inspection and manufacturing settings as well as sensitivities to directions and manner of illumination." Id. at 7. Applicant respectfully submits that Office's reasoning incorrectly equates the claimed "multi-sensitivity metrology target" having specific features and characteristics to generic device structures.”
Examiner notes that simply stating that the Examiner is incorrect does not address the specific reasons for rejection. Also, the arguments of counsel cannot take the place of evidence in the record. In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997) (“An assertion of what seems to follow from common experience is just attorney argument and not the kind of factual evidence that is required to rebut a prima facie case of obviousness.”).
The evidence on the record indicates that the metrology target as claimed has features that are similar to common devices and metrology targets in the prior art. See reasons for rejection below.
Applicant argues: “Office does not identify any disclosure in the cited art pertaining to a metrology target having at least two orthogonal sub-targets that have different sensitivities to the same characteristic of interest. Instead, the Office generally alleges that any device fabricated by lithography will read on Applicant's claims.”
Examiner notes that the reasons for rejection (below) cite Zhang, Paragraph 3, Middlebrooks, Paragraphs 3-4, 55, and Figs, 5, 7, 8; AAPA Specification, Paragraphs 2-4, 6 as well as In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), and MPEP 2113(I). Applicant’s opinion that prior art is not cited is not persuasive of patentability.
Applicant argues: “Moreover, Applicant's specification details how a multi-sensitivity metrology target as claimed is fabricated to have at least two sub-targets arranged orthogonally and having different sensitivities to a characteristic of interest. See, e.g., Applicant's specification at paragraph [0109] and Figure 11. Applicant's specific multisensitivity metrology target is not the result of simply "performing lithography" to form a logic device as alleged by the Office. Instead, the multi-sensitivity metrology is fabricated according to varying conditions (e.g., different pitch, critical dimension, biases, target types, thickness, side wall angles, etc.) to achieve specific structural requirements for distinct sub-targets.”
Examiner notes that the claims do not recite this level of detail as limitations. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant argues: “The cited art also fails to teach or suggest "training a neural network ... the training being limited to the different sensitivities to the characteristic of interest of the at least two sub-targets of the multi-sensitivity metrology target," as recited in Applicant's claims.”
Examiner notes that the claim is directed to “training a neural network to infer values of the characteristic of interest related to the multi-sensitivity metrology target from the input image” which does not limit the training to any particular method or dataset. There is no limitation on the methods of training or how the characteristics of interests can be inferred. Since prior art teaches substantively identical methods of training and substantively identical target lithography, prior art renders the claim obvious. See reasons for rejection below.
Applicant argues: “Zhang's training method is not equivalent to training a neural network that is expressly limited to sensitivity differences between defined sub-targets that each have different sensitivities to a characteristic of interest.”
Examiner notes that the claims are not rejected as equivalent to the prior art, they are rejected as obvious. The claimed method does not limit the training to using any specific data such that the neural network be able to infer sensitivities. Prior art teaches substantively the same methods of training and substantively similar lithographic subject matter, thus rendering the claims obvious.
Applicant argues: “Absent a teaching or reasoned suggestion in the cited references to impose such a constraint, the Office relies on impermissible hindsight reconstruction of Applicant's claimed approach rather than on a disclosure-based obviousness analysis.”
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). The claims are rejected over the features and motivations cited to the prior art and not knowledge gleaned only from the applicant's disclosure. See reasons for rejection below.
Claim Construction
Note that, for purposes of compact prosecution, multiple reasons for rejection may be provided for a claim or a part of the claim. The rejection reasons are cumulative, and Applicant should review all the stated reasons as guides to improving the claim language and advancing the prosecution toward an allowance.
Claim scope is not limited by claim language that suggests or makes optional but does not require steps to be performed by a method claim, or by claim language that does not limit an apparatus claim to a particular structure. However, examples of claim language, although not exhaustive, that may raise a question as to the limiting effect of the language in a claim are: (A) “adapted to” or “adapted for” clauses; (B) “wherein” clauses; and (C) “whereby” clauses. M.P.E.P. 2111.04. Other examples are where the claim passively indicates that a function is performed or a structure is used without requiring that the function or structure is a limitation on the claim itself. The clause may be given some weight to the extent it provides "meaning and purpose” to the claimed invention but not when “it simply expresses the intended result” of the invention. In Hoffer v. Microsoft Corp., 405 F.3d 1326, 1329, 74 USPQ2d 1481, 1483 (Fed. Cir. 2005). Further, during prosecution, claim language that may or may not be limiting should be considered non-limiting under the standard of the broadest reasonable interpretation. See M.P.E.P. 904.01(a); In re Morris, 127 F.3d 1048, 44 USPQ2d 1023 (Fed. Cir. 1997).
"[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113(I).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This paragraph describes the treatment of admitted prior art. In describing an invention, Applicant must inevitably reference that which is known in the art as the basis for the invention, however it is important that the claims particularly point out and distinctly claim that which Applicant regards to be his own invention. See 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. A statement by an applicant in the specification or made during prosecution identifying the work of another as prior art is an admission which can be relied upon for both anticipation and obviousness determinations, regardless of whether the admitted prior art would otherwise qualify as prior art under the statutory categories of 35 U.S.C. 102. Riverwood Int ’l Corp. v. R.A. Jones & Co., 324 F.3d 1346, 1354, 66 USPQ2d 1331, 1337 (Fed. Cir. 2003); Constant v. Advanced Micro-Devices Inc., 848 F.2d 1560, 1570, 7 USPQ2d 1057, 1063 (Fed. Cir. 1988). The examiner must determine whether the subject matter identified as prior art is applicant’s own work, or the work of another. In the absence of another credible explanation, examiners should treat such subject matter as the work of another. MPEP 2129.
Claims 1-7, 9, 11-16, 18-23 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over US 20170351952 to Zhang (“Zhang “) in view of US 20130059240 to Van Der Schaar (“Van Der Schaar”) in view of US 20170345138 to Middlebrooks (“Middlebrooks”).
Regarding Claim 1: “A method for training a neural network, the method comprising:
obtaining an input image (“The computer subsystem(s) are, in this embodiment, configured for acquiring the images” Zhang, Paragraphs 15 and 4-5. See similarly in Middlebrooks, Paragraph 55.)
of a multi-sensitivity metrology target formed on a substrate by a lithographic process, (“For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Metrology processes are also used at various steps during a semiconductor manufacturing process” Zhang, Paragraphs 3, 6. See similarly in Middlebrooks, Paragraph 55.)
the multi-sensitivity metrology target formed with at least two sub-targets having periodic patterns arranged orthogonal to each other and having different sensitivities to a characteristic of interest; (First, note that this element describes the metrology target by the method of making it, however determination of patentability of a product does not depend on its method of production. See Claim Construction section above. The method of making the metrology target is recited to be external to the limitations of the present method of imaging the metrology target. Therefore, this element is rejected for reasons stated above.
Cumulatively, note that Specification indicates that the multiple features, periodic patterns, and different sensitivities are produced “when the structures have been formed using EUV lithography” in the process of fabricating the semiconductor products on a wafer. See Specification, Paragraphs 105-106.
Zhang teaches manufacturing of such features: “Fabricating semiconductor devices such as logic and memory devices [a repetitive collection of orthogonally patterned features] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer.” Zhang, Paragraph 3.
Further, Van Der Schaar teaches specific examples of such lithography in the context of “metrology usable, for example, in the manufacture of devices by lithographic techniques and to methods of manufacturing devices using lithographic techniques … In general, a single substrate will contain a network of adjacent target portions that are successively patterned.” Van Der Schaar, Paragraphs 3, 5. For example, “FIG. 6 shows an example of a larger overlay metrology target 50, which is intended for measurement” Van Der Schaar, Paragraph 72. See similar embodiments in Middlebrooks, Paragraph 55, and Figs, 5, 7, 8.
Therefore, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to supplement the teachings of Zhang to use lithography to produce a large number of different semiconductor features on a multiple number of layers and using different fabrication processes and thus naturally having multiple sensitives to inspection and manufacturing settings as well as sensitivities to directions and manner of illumination as taught in Van Der Schaar, in order to manufacture the variety of features required for a semiconductor product. Van Der Schaar, Paragraphs 3, 5.
Finally, in reviewing the present application, there does not seem to be objective evidence that the claim limitations are particularly directed to: addressing a particular problem which was recognized but unsolved in the art, producing unexpected results at the level of the ordinary skill in the art, or any other objective indicators of non-obviousness. In particularly because all semiconductor devices formed by lithography exhibit parallel and perpendicular features subject to sensitivities.
training a neural network to infer values of the characteristic of interest related to the multi-sensitivity metrology target from the input image, (“One embodiment relates to a system configured to train a neural network. As described further herein, the embodiments may include an inversion neural network (INN) to solve the inverse problem for semiconductor applications such as inspection, defect review, metrology, and others described herein.” Zhang, Paragraphs 28, 10.)
the training being limited to the different sensitivities to the characteristic of interest of the at least two sub-targets of the multi-sensitivity metrology target; (Note that while this element is limited to the characteristic of interest, the characteristic of interest is not limited to one particular characteristic of interest in the claim. For example, all characteristics except for dose are optical effects of lithography. Zhang teaches “Conventional approaches in general involve two steps: (1) restoring or inversing the undesired optical effects (e.g., diffraction, interference, partial coherence, etc.); and (2) using the restored/processed imaging data as the input to train an application-specific neural network … a training dataset can be obtained from tool measurements and/or through simulation,” of the optical effect. Zhang, Paragraph 10. This corresponds to the embodiments in Paragraphs 14-15 of the Specification. Thus, it is known to train a neural network to detect a particular characteristic of interest embodying an effect of the lithography process on the target based on reference images of such an effect.)
wherein the trained neural network is configured to determine the characteristic of interest based on the input image.” (“the embodiments may include an inversion neural network (INN) [configured] to solve the inverse problem for semiconductor applications such as inspection, defect review, metrology, and others described herein,” which determine characteristics based on “the input images are generated by an optical based imaging system.” Zhang, Paragraph 28.)
wherein the characteristic of interest comprises overlay, focus, an energetic illumination characteristic, a geometric non-telecentricity illumination characteristic, dose, or an aberration; (Again, this characteristic describes a preferred manufacturing process of the metrology target, but the claim is not limited to either the manufacturing process or the structure of the target. See discussion above.
Cumulatively, under the broadest reasonable interpretation consistent with the specification and ordinary skill in the art, these characteristics of interests are characteristics of a lithographic system, in which, features that are formed by the lithographic system are sensitive to such characteristics of interest. In an example, periodic features exhibit sensitivities. See Specification, Paragraphs 106-107. As noted above, Zhang teaches “to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process …” Zhang, Paragraph 3. Such semiconductor devices are thus sensitive to characteristics and defects of the lithography process. However, Zhang does not enumerate the characteristics of the lithographic system that can be measured.
Middlebooks teaches the claimed characteristics in the context of a lithographic process: “a metrology target, or a portion thereof ( e.g., a grating of the metrology target), that is used to measure a parameter (e.g., overlay, focus, dose, etc.) of the lithographic process.” Middlebrooks, Paragraph 55.
Therefore, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to supplement the teachings of Zhang and Van Der Schaar to measure the above characteristics of a lithographic process as taught in Middlebrooks, “for making measurements of the microscopic structures formed in a lithographic process.” Middlebrooks, Paragraph 4.
Finally, in reviewing the present application, there does not seem to be objective evidence that the claim limitations are particularly directed to: addressing a particular problem which was recognized but unsolved in the art, producing unexpected results at the level of the ordinary skill in the art, or any other objective indicators of non-obviousness.
Regarding Claim 2: “The method of claim 1, further comprising forming the multi-sensitivity metrology target with at least five sub-targets having periodic patterns arranged in two orthogonal orientations to each other and having different sensitivities to the characteristic of interest.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 3: “The method of claim 2, further comprising forming the periodic patterns of the at least five sub-targets with variation in pitch and critical dimension corresponding to the different sensitivities.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 4: “The method of claim 1, further comprising forming the multi-sensitivity metrology target with at least ten sub-targets having periodic patterns arranged in two orthogonal orientations to each other and having different sensitivities to the characteristic of interest.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 5: “The method of claim 4, further comprising forming the periodic patterns of the at least ten sub-targets with variation in pitch and critical dimension corresponding to the different sensitivities.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 6: “The method of claim 1, further comprising forming the periodic patterns of the at least two sub-targets with sub-resolution features varying in pitch or critical dimension corresponding to the different sensitivities.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 7: “The method of claim 6, wherein
the sub-resolution features provide a measurable variation in the different sensitivities of the multi-sensitivity metrology target (For example, the sub-resolution features can embody “the low resolution image is not generated at a resolution that renders all patterned features in the image resolvable. In this manner, a "low resolution image," as that term is used herein, does not contain information about patterned features on the specimen that is sufficient for the low resolution image to be used for applications such as defect review, …” Zhang, Paragraph 100.)
that are dependent on focus or dose during formation of the multi-sensitivity metrology target.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 9: “The method of claim 6, further comprising forming the sub-resolution features with pairs of mirrored sub-resolution features in opposing orientation.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features repeated/mirrored in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Claim 11: “A metrology system” is rejected for reasons stated for Claim 1, and because prior art teaches:
an illumination branch comprising a radiation source and configured to direct illumination radiation at a substrate; (“the embodiment of the system shown in FIG. 1, optical based imaging system 10 includes an illumination subsystem configured to direct light to specimen 14.” Zhang, Paragraph 31.)
a detection branch comprising a detector and configured to detect scattered radiation from a multi-sensitivity metrology target formed on the substrate by a lithographic process; and (“The imaging system may be configured to direct the light to the specimen at different angles of incidence at different times … The one or more detection channels may include any suitable detectors known in the art. For example, the detectors may include photo-multiplier tubes (PMTs), charge coupled devices (CCDs), time delay integration (TOI) cameras, and any other suitable detectors” Zhang, Paragraphs 31-33, 42. See treatment of metrology targets in Claim 1.)
a processor configured to perform operations comprising: …” (“the term "computer system" may be broadly defined to encompass any device having one or more processors” Zhang, Paragraph 45.)
Claim 12 is rejected for reasons stated for Claim 2 in view of Claim 11 rejection. Cumulatively, the claim is rejected for reasons stated for Claim 11 because the present claim is not limited to forming the target by the system (as in the previously rejected claim), but rather provides an example of the target that can be used with the claimed system without modifying the structures of method steps executed by the processor.
Claim 13 is rejected for reasons stated for Claim 3 in view of Claim 11 rejection. Cumulatively, the claim is rejected for reasons stated for Claim 11 because the present claim is not limited to forming the target by the system (as in the previously rejected claim), but rather provides an example of the target that can be used with the claimed system without modifying the structures of method steps executed by the processor.
Claim 14 is rejected for reasons stated for Claim 3 in view of Claim 11 rejection. Cumulatively, the claim is rejected for reasons stated for Claim 11 because the present claim is not limited to forming the target by the system (as in the previously rejected claim), but rather provides an example of the target that can be used with the claimed system without modifying the structures of method steps executed by the processor.
Claim 15 is rejected for reasons stated for Claim 7 in view of Claim 11 rejection.
Claim 16 is rejected for reasons stated for Claim 9 in view of Claim 11 rejection. Cumulatively, the claim is rejected for reasons stated for Claim 11 because the present claim is not limited to forming the target by the system (as in the previously rejected claim), but rather provides an example of the target that can be used with the claimed system without modifying the structures of method steps executed by the processor.
Regarding Claim 18: “The metrology system of claim 11, wherein
the trained neural network comprises a coarse trained neural network (Under the broadest reasonable interpretation consistent with the specification and ordinary skill in the art, a coarse trained neural network can be trained to operate on low resolution images and a fine trained neural network can be trained to operate on high resolution images. See Specification, Paragraph 128.
Prior art teaches, “For example, in some embodiments, the neural network may be configured to generate one or more high resolution images from a low resolution input image,” and thus correspond to a coarse trained neural network that operates on low resolution images. Zhang, Paragraph 98.)
and a fine trained neural network.” (“A "high resolution image" as that term is used herein can be generally defined as an image in which all patterned features of the specimen are resolved with relatively high accuracy. … input a runtime image for the specimen or another specimen into the trained neural network such that the trained neural network determines [resolves] the inverted features for the runtime image, and the inverted features are features of an amplitude and phase version of the runtime image” Zhang, Paragraphs 101- 102.)
Regarding Claim 19: “The metrology system of claim 11, wherein the input image comprises a low-quality input image obtained by a sensor comprising low-quality optics having high aberrations.” (“a "low resolution image" as that term is used herein generally refers to images generated by inspection systems, which typically have relatively lower resolution ( e.g., lower than defect review and/or metrology systems)” Zhang, Paragraph 100.)
Regarding Claim 20: “A non-transitory computer readable storage medium storing instructions which, when executed by at least one processor, cause the at least one processor to perform operations,” is rejected for reasons stated for Claim 1, and because prior art teaches: “Program instructions 502 implementing methods such as those described herein may be stored on computer-readable medium 500.” Zhang, Paragraphs 126-127.)
Regarding Claim 21: “The method of claim 1, wherein: the characteristic of interest comprises focus, and the different sensitivities of the at least two sub-targets comprise different focus values.” (See “a metrology target, or a portion thereof ( e.g., a grating of the metrology target), that is used to measure a parameter (e.g., overlay, focus, dose, etc.) of the lithographic process.” Middlebrooks, Paragraph 55. See statement of motivation in Claim 1.)
Regarding Claim 22: “The method of claim 21, wherein:
the characteristic of interest further comprises dose, and (See “a metrology target, or a portion thereof ( e.g., a grating of the metrology target), that is used to measure a parameter (e.g., overlay, focus, dose, etc.) of the lithographic process.” Middlebrooks, Paragraph 55. See statement of motivation in Claim 1.)
the multi-sensitivity metrology target is formed in a focus-exposure matrix (FEM) such that the different sensitivities of the at least two sub-targets comprise different dose values.” (Again note that the claim is limited to taking an image of a target, and the process of taking an image is not limited the method of making the target in this element. Thus, this element is rejected for reasons stated in Claim 21, and cumulatively because prior art teaches: “SEM images and mathematical representations of the same structure produced at a nonnominal condition of the parameter, e.g., at focus offset” Middlebrooks. Paragraph 70.)
Regarding Claim 23: “The method of claim 1, wherein: the characteristic of interest comprises overlay, and the different sensitivities of the at least two sub-targets comprise different overlay values.” (See “a metrology target, or a portion thereof ( e.g., a grating of the metrology target), that is used to measure a parameter (e.g., overlay, focus, dose, etc.) of the lithographic process.” Middlebrooks, Paragraph 55. See statement of motivation in Claim 1.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130271595 to Hiroi (“Hiroi”) relevant for exemplifying that complex orthogonal patterns are ordinary features of semiconductor lithography.
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/MIKHAIL ITSKOVICH/Primary Examiner, Art Unit 2483
Prosecution Insights