DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 11/17/2025 have been fully considered but they are not persuasive.
Applicant argues regarding the patentability of the newly amended language.
Examiner notes that the amendments are addressed by the updated reasons for rejection below.
Applicant argues: “But as discussed during the Interview and shown in Figure 9 of the instant Application, reproduced below, Zhang relies on computationally enhanced images (e.g., "optically corrected versions") of a generic "reticle" to produce a training dataset rather than a specialized fabricated multi-sensitivity metrology target to specifically and efficiently train a neural network to determine a specific characteristic of interest.”
Examiner notes that the claims do not limit the claims to training a neural network based on “a specialized fabricated multi-sensitivity metrology target,” or to particular steps of training. Therefore, the claimed training broadly embodies the types of training described in the prior art.
Applicant argues: “Indeed, as discussed during the Interview, the claimed embodiment utilizes a specific multi-sensitivity metrology target with at least two sub-targets having different sensitivities to a characteristic of interest (e.g., overlay, focus, dose, etc.) to generate tailored training images to improve training efficiency and alignment accuracy. See Specification, [0071], [0074], [0076].”
Examiner notes that the claims are not limited to “a specific multi-sensitivity metrology target.” The claimed sub-targets and sensitivities read on most semiconductor devices fabricated using lithography. See reasons for rejection below.
Applicant argues: “Additionally, the Office's proposed combination of Zhang and alleged AAPA, without acquiescing that any aspect of the Specification rises to AAPA, would not have been obvious to a person of ordinary skill in the art ("POSA") because (1) it would not render obvious each and every element of the claims and (2) a POSA would not have been motivated to modify Zhang based on alleged AAPA because Zhang only teaches training of a neural network …”
Examiner notes that this argument seems to be a convolution of different theories which are neither completely stated nor supported by evidence. The Office does not need to acquiesce “that any aspect of the Specification rises to AAPA,” AAPA is cited based on Applicant’s own admission of such art as a basis for the intended improvements. Cumulatively, bodily incorporation of one reference into another is not a required standard of rejection under section 103. See reasons for rejection below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This paragraph describes the treatment of admitted prior art. In describing an invention, Applicant must inevitably reference that which is known in the art as the basis for the invention, however it is important that the claims particularly point out and distinctly claim that which Applicant regards to be his own invention. See 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. A statement by an applicant in the specification or made during prosecution identifying the work of another as prior art is an admission which can be relied upon for both anticipation and obviousness determinations, regardless of whether the admitted prior art would otherwise qualify as prior art under the statutory categories of 35 U.S.C. 102. Riverwood Int ’l Corp. v. R.A. Jones & Co., 324 F.3d 1346, 1354, 66 USPQ2d 1331, 1337 (Fed. Cir. 2003); Constant v. Advanced Micro-Devices Inc., 848 F.2d 1560, 1570, 7 USPQ2d 1057, 1063 (Fed. Cir. 1988). The examiner must determine whether the subject matter identified as prior art is applicant’s own work, or the work of another. In the absence of another credible explanation, examiners should treat such subject matter as the work of another. MPEP 2129.
Claims 1-7, 9, 11-16, 18-23 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over US 20170351952 to Zhang (“Zhang “) in view of Applicant Admitted Prior Art in the Specification (“AAPA”) in view of US 20170345138 to Middlebrooks (“Middlebrooks”).
Regarding Claim 1: “A method comprising:
obtaining an input image (“The computer subsystem(s) are, in this embodiment, configured for acquiring the images” Zhang, Paragraphs 15 and 4-5. See similarly in Middlebrooks, Paragraph 55.)
of a multi-sensitivity metrology target formed on a substrate by a lithographic process, (“For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Metrology processes are also used at various steps during a semiconductor manufacturing process” Zhang, Paragraphs 3, 6. See similarly in Middlebrooks, Paragraph 55.)
the multi-sensitivity metrology target formed with at least two sub-targets having periodic patterns arranged orthogonal to each other and having different sensitivities to a characteristic of interest; (First, note that this element limits how the metrology target is formed, however the method claim is not a method of forming a metrology target, it is a method of imaging and recognizing a metrology target, and the claimed method steps do not appear to change at all based on the method of forming a target of imaging. Therefore, this element is rejected for reasons stated above.
Cumulatively, note that Specification indicates that the multiple features, periodic patterns, and different sensitivities are produced “when the structures have been formed using EUV lithography” in the process of fabricating the semiconductor products on a wafer. See Specification, Paragraphs 105-106.
Zhang teaches this feature “Fabricating semiconductor devices such as logic and memory devices [a repetitive collection of orthogonally patterned features] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer.” Zhang, Paragraph 3. See similarly in Middlebrooks, Paragraph 55, and Figs, 5, 7, 8.)
Further, AAPA indicates that the lithography process for producing the claimed types of semiconductor features is prior art. See Specification, Paragraphs 2-4, 6. See similarly in Middlebrooks, Paragraphs 3-4.
Therefore, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to supplement the teachings of Zhang to use lithography to produce a large number of different semiconductor features on a multiple number of layers and using different fabrication processes and thus naturally having multiple sensitives to inspection and manufacturing settings as well as sensitivities to directions and manner of illumination as taught in AAPA, in order to manufacture the variety of features required for a semiconductor product. AAPA, Specification, Paragraphs 2-4.
Finally, in reviewing the present application, there does not seem to be objective evidence that the claim limitations are particularly directed to: addressing a particular problem which was recognized but unsolved in the art, producing unexpected results at the level of the ordinary skill in the art, or any other objective indicators of non-obviousness.)
training a neural network to infer values of the characteristic of interest related to the multi-sensitivity metrology target from the input image, (“One embodiment relates to a system configured to train a neural network. As described further herein, the embodiments may include an inversion neural network (INN) to solve the inverse problem for semiconductor applications such as inspection, defect review, metrology, and others described herein.” Zhang, Paragraphs 28, 10.)
the training being limited to the different sensitivities to the characteristic of interest of the at least two sub-targets of the multi-sensitivity metrology target; and (Note that while this element is limited to the characteristic of interest, the characteristic of interest is not limited to one particular characteristic of interest in the claim. For example, all characteristics except for dose are optical effects of lithography. Zhang teaches “Conventional approaches in general involve two steps: (1) restoring or inversing the undesired optical effects (e.g., diffraction, interference, partial coherence, etc.); and (2) using the restored/processed imaging data as the input to train an application-specific neural network … a training dataset can be obtained from tool measurements and/or through simulation,” of the optical effect. Zhang, Paragraph 10. This corresponds to the embodiments in Paragraphs 14-15 of the Specification. Thus, it is known to train a neural network to detect a particular characteristic of interest embodying an effect of the lithography process on the target based on reference images of such an effect.)
using the trained neural network to determine the characteristic of interest based on the input image.” (“the embodiments may include an inversion neural network (INN) to solve the inverse problem for semiconductor applications such as inspection, defect review, metrology, and others described herein,” which determine characteristics based on “the input images are generated by an optical based imaging system.” Zhang, Paragraph 28.)
wherein the characteristic of interest comprises overlay, focus, an energetic illumination characteristic, a geometric non-telecentricity illumination characteristic, dose, or an aberration; (Again, this characteristic describes a preferred manufacturing process of the metrology target, but the claim is not limited to either the manufacturing process or the structure of the target. See discussion above.
Cumulatively, under the broadest reasonable interpretation consistent with the specification and ordinary skill in the art, these characteristics of interests are characteristics of a lithographic system, in which, features that are formed by the lithographic system are sensitive to such characteristics of interest. In an example, periodic features exhibit sensitivities. See Specification, Paragraphs 106-107. As noted above, Zhang teaches “to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process …” Zhang, Paragraph 3. Such semiconductor devices are thus sensitive to characteristics and defects of the lithography process. However, Zhang does not enumerate the characteristics of the lithographic system that can be measured.
Middlebooks teaches the claimed characteristics in the context of a lithographic process: “a metrology target, or a portion thereof ( e.g., a grating of the metrology target), that is used to measure a parameter (e.g., overlay, focus, dose, etc.) of the lithographic process.” Middlebrooks, Paragraph 55.
Therefore, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to supplement the teachings of Zhang and AAPA to measure the above characteristics of a lithographic process as taught in Middlebrooks, “for making measurements of the microscopic structures formed in a lithographic process.” Middlebrooks, Paragraph 4.
Finally, in reviewing the present application, there does not seem to be objective evidence that the claim limitations are particularly directed to: addressing a particular problem which was recognized but unsolved in the art, producing unexpected results at the level of the ordinary skill in the art, or any other objective indicators of non-obviousness.)
Regarding Claim 2: “The method of claim 1, further comprising forming the multi-sensitivity metrology target with at least five sub-targets having periodic patterns arranged in two orthogonal orientations to each other and having different sensitivities to the characteristic of interest.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 3: “The method of claim 2, further comprising forming the periodic patterns of the at least five sub-targets with variation in pitch and critical dimension corresponding to the different sensitivities.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 4: “The method of claim 1, further comprising forming the multi-sensitivity metrology target with at least ten sub-targets having periodic patterns arranged in two orthogonal orientations to each other and having different sensitivities to the characteristic of interest.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 5: “The method of claim 4, further comprising forming the periodic patterns of the at least ten sub-targets with variation in pitch and critical dimension corresponding to the different sensitivities.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 6: “The method of claim 1, further comprising forming the periodic patterns of the at least two sub-targets with sub-resolution features varying in pitch or critical dimension corresponding to the different sensitivities.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 7: “The method of claim 6, wherein
the sub-resolution features provide a measurable variation in the different sensitivities of the multi-sensitivity metrology target (For example, the sub-resolution features can embody “the low resolution image is not generated at a resolution that renders all patterned features in the image resolvable. In this manner, a "low resolution image," as that term is used herein, does not contain information about patterned features on the specimen that is sufficient for the low resolution image to be used for applications such as defect review, …” Zhang, Paragraph 100.)
that are dependent on focus or dose during formation of the multi-sensitivity metrology target.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Regarding Claim 9: “The method of claim 6, further comprising forming the sub-resolution features with pairs of mirrored sub-resolution features in opposing orientation.” (Zhang teaches “Fabricating semiconductor devices such as logic and memory devices [a large number of devices each having a large number of parallel and orthogonal features repeated/mirrored in a specified pitch] typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. … Multiple semiconductor devices may be fabricated in an arrangement …” in the context of inspection and metrology. Zhang, Paragraph 3. See statement of motivation in Claim 1.)
Claim 11: “A metrology system” is rejected for reasons stated for Claim 1, and because prior art teaches:
an illumination branch comprising a radiation source and configured to direct illumination radiation at a substrate; (“the embodiment of the system shown in FIG. 1, optical based imaging system 10 includes an illumination subsystem configured to direct light to specimen 14.” Zhang, Paragraph 31.)
a detection branch comprising a detector and configured to detect scattered radiation from a multi-sensitivity metrology target formed on the substrate by a lithographic process; and (“The imaging system may be configured to direct the light to the specimen at different angles of incidence at different times … The one or more detection channels may include any suitable detectors known in the art. For example, the detectors may include photo-multiplier tubes (PMTs), charge coupled devices (CCDs), time delay integration (TOI) cameras, and any other suitable detectors” Zhang, Paragraphs 31-33, 42. See treatment of metrology targets in Claim 1.)
a processor configured to perform operations comprising: …” (“the term "computer system" may be broadly defined to encompass any device having one or more processors” Zhang, Paragraph 45.)
Claim 12 is rejected for reasons stated for Claim 2 in view of Claim 11 rejection. Cumulatively, the claim is rejected for reasons stated for Claim 11 because the present claim is not limited to forming the target by the system (as in the previously rejected claim), but rather provides an example of the target that can be used with the claimed system without modifying the structures of method steps executed by the processor.
Claim 13 is rejected for reasons stated for Claim 3 in view of Claim 11 rejection. Cumulatively, the claim is rejected for reasons stated for Claim 11 because the present claim is not limited to forming the target by the system (as in the previously rejected claim), but rather provides an example of the target that can be used with the claimed system without modifying the structures of method steps executed by the processor.
Claim 14 is rejected for reasons stated for Claim 3 in view of Claim 11 rejection. Cumulatively, the claim is rejected for reasons stated for Claim 11 because the present claim is not limited to forming the target by the system (as in the previously rejected claim), but rather provides an example of the target that can be used with the claimed system without modifying the structures of method steps executed by the processor.
Claim 15 is rejected for reasons stated for Claim 7 in view of Claim 11 rejection.
Claim 16 is rejected for reasons stated for Claim 9 in view of Claim 11 rejection. Cumulatively, the claim is rejected for reasons stated for Claim 11 because the present claim is not limited to forming the target by the system (as in the previously rejected claim), but rather provides an example of the target that can be used with the claimed system without modifying the structures of method steps executed by the processor.
Regarding Claim 18: “The metrology system of claim 11, wherein
the trained neural network comprises a coarse trained neural network (Under the broadest reasonable interpretation consistent with the specification and ordinary skill in the art, a coarse trained neural network can be trained to operate on low resolution images and a fine trained neural network can be trained to operate on high resolution images. See Specification, Paragraph 128.
Prior art teaches, “For example, in some embodiments, the neural network may be configured to generate one or more high resolution images from a low resolution input image,” and thus correspond to a coarse trained neural network that operates on low resolution images. Zhang, Paragraph 98.)
and a fine trained neural network.” (“A "high resolution image" as that term is used herein can be generally defined as an image in which all patterned features of the specimen are resolved with relatively high accuracy. … input a runtime image for the specimen or another specimen into the trained neural network such that the trained neural network determines [resolves] the inverted features for the runtime image, and the inverted features are features of an amplitude and phase version of the runtime image” Zhang, Paragraphs 101- 102.)
Regarding Claim 19: “The metrology system of claim 11, wherein the input image comprises a low-quality input image obtained by a sensor comprising low-quality optics having high aberrations.” (“a "low resolution image" as that term is used herein generally refers to images generated by inspection systems, which typically have relatively lower resolution ( e.g., lower than defect review and/or metrology systems)” Zhang, Paragraph 100.)
Regarding Claim 20: “A non-transitory computer readable storage medium storing instructions which, when executed by at least one processor, cause the at least one processor to perform operations,” is rejected for reasons stated for Claim 1, and because prior art teaches: “Program instructions 502 implementing methods such as those described herein may be stored on computer-readable medium 500.” Zhang, Paragraphs 126-127.)
Regarding Claim 21: “The method of claim 1, wherein: the characteristic of interest comprises focus, and the different sensitivities of the at least two sub-targets comprise different focus values.” (See “a metrology target, or a portion thereof ( e.g., a grating of the metrology target), that is used to measure a parameter (e.g., overlay, focus, dose, etc.) of the lithographic process.” Middlebrooks, Paragraph 55. See statement of motivation in Claim 1.)
Regarding Claim 22: “The method of claim 21, wherein:
the characteristic of interest further comprises dose, and (See “a metrology target, or a portion thereof ( e.g., a grating of the metrology target), that is used to measure a parameter (e.g., overlay, focus, dose, etc.) of the lithographic process.” Middlebrooks, Paragraph 55. See statement of motivation in Claim 1.)
the multi-sensitivity metrology target is formed in a focus-exposure matrix (FEM) such that the different sensitivities of the at least two sub-targets comprise different dose values.” (Again note that the claim is limited to taking an image of a target, and the process of taking an image is not limited the method of making the target in this element. Thus, this element is rejected for reasons stated in Claim 21, and cumulatively because prior art teaches: “SEM images and mathematical representations of the same structure produced at a nonnominal condition of the parameter, e.g., at focus offset” Middlebrooks. Paragraph 70.)
Regarding Claim 23: “The method of claim 1, wherein: the characteristic of interest comprises overlay, and the different sensitivities of the at least two sub-targets comprise different overlay values.” (See “a metrology target, or a portion thereof ( e.g., a grating of the metrology target), that is used to measure a parameter (e.g., overlay, focus, dose, etc.) of the lithographic process.” Middlebrooks, Paragraph 55. See statement of motivation in Claim 1.)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKHAIL ITSKOVICH whose telephone number is (571)270-7940. The examiner can normally be reached Mon. - Thu. 9am - 8pm.
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/MIKHAIL ITSKOVICH/Primary Examiner, Art Unit 2483