DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 4-5, and 7-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,100,762 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1-2, 4-5, and 7-20 are anticipated by claims 1-20 of the patent, and it is not patentably distinct from claims 1-20 of the patent. See the Table as shown below:
Claims of Under Examination
Patented claims
1. An integrated circuit structure, comprising:
a semiconductor body comprising a source or drain region;
a first contact structure over a top, along a first sidewall, and along a second sidewall of the source or drain region;
a second contact structure below and in contact with the first contact structure, the second contact structure extending beneath a bottom of the source or drain region of the semiconductor body, wherein the second contact structure and the first contact structure together completely surround, from a cross-sectional perspective, the top, the first sidewall, the second sidewall, and the bottom of the source or drain region of the semiconductor body; and
a dielectric layer between the first contact structure and a portion of the first sidewall of the source or drain region of the semiconductor body, and between the first contact structure and a portion of the second sidewall of the source or drain region of the semiconductor body.
Anticipated by patented claim 1:
1. An integrated circuit structure, comprising:
a semiconductor body having a top, sides and a bottom, wherein the semiconductor body comprises a source or drain region; a first contact structure on a top, a first sidewall, and a second sidewall of the source or drain region over the top and adjacent to the sides of the semiconductor body, the first contact structure extending below the bottom of the semiconductor body;
a second contact structure below and in contact with the first contact structure, the second contact structure extending beneath the bottom of the semiconductor body, wherein the second contact structure and the first contact structure together completely surround, from a cross-sectional perspective, the top, the first sidewall, the second sidewall, and a bottom of the source or drain region; and
a dielectric layer between the first contact structure and the first sidewall of the source or drain region, and between the first contact structure and the second sidewall of the source or drain region.
2. The integrated circuit structure of claim 1, wherein the dielectric layer is further between the bottom of the source or drain region and the second contact structure.
Anticipated by patented claim 4:
4. The integrated circuit structure of claim 3, wherein the dielectric material is further between the bottom of the semiconductor body and the second contact structure.
4. The integrated circuit structure of claim 1, wherein the first contact structure is spaced apart from the top of the semiconductor body.
Anticipated by patented claim 6:
6. The integrated circuit structure of claim 1, wherein the first contact structure is spaced apart from the top of the semiconductor body.
5. The integrated circuit structure of claim 4, further comprising: an epitaxial material between the top of the semiconductor body and the first contact structure.
Anticipated by patented claim 7:
7. The integrated circuit structure of claim 6, further comprising: an epitaxial material between the top of the semiconductor body and the first contact structure.
7. The integrated circuit structure of claim 1, wherein the semiconductor body is a fin.
Anticipated by patented claim 8:
8. The integrated circuit structure of claim 1, wherein the semiconductor body is a fin.
8. The integrated circuit structure of claim 1, further comprising: a gate structure laterally adjacent to the first contact structure.
Anticipated by patented claim 9:
9. The integrated circuit structure of claim 1, further comprising: a gate structure laterally adjacent to the first contact structure.
9. The integrated circuit structure of claim 8, wherein the gate structure is on a top of the semiconductor body.
Anticipated by patented claim 10:
10. The integrated circuit structure of claim 9, wherein the gate structure is on the top of the semiconductor body.
10. The integrated circuit structure of claim 9, further comprising: a second source or drain region at a side of the gate structure opposite the source or drain region.
Anticipated by patented claim 11:
11. The integrated circuit structure of claim 9, further comprising: a second source or drain region at a side of the gate structure opposite the source or drain region.
11. The integrated circuit structure of claim 8, further comprising: a second source or drain region at a side of the gate structure opposite the source or drain region.
Anticipated by patented claim 11:
11. The integrated circuit structure of claim 9, further comprising: a second source or drain region at a side of the gate structure opposite the source or drain region.
12. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
a semiconductor body comprising a source or drain region;
a first contact structure over a top, along a first sidewall, and along a second sidewall of the source or drain region;
a second contact structure below and in contact with the first contact structure, the second contact structure extending beneath a bottom of the source or drain region of the semiconductor body, wherein the second contact structure and the first contact structure together completely surround, from a cross-sectional perspective, the top, the first sidewall, the second sidewall, and the bottom of the source or drain region of the semiconductor body; and
a dielectric layer between the first contact structure and a portion of the first sidewall of the source or drain region of the semiconductor body, and between the first contact structure and a portion of the second sidewall of the source or drain region of the semiconductor body.
Anticipated by patented claim 12:
12. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
a semiconductor body having a top, sides and a bottom, wherein the semiconductor body comprises a source or drain region;
a first contact structure on a top, a first sidewall, and a second sidewall of the source or drain region over the top and adjacent to the sides of the semiconductor body, the first contact structure extending beneath the bottom of the semiconductor body;
a second contact structure below and in contact with the first contact structure, the second contact structure extending beneath the bottom of the semiconductor body, wherein the second contact structure and the first contact structure together completely surround, from a cross-sectional perspective, the top, the first sidewall, the second sidewall, and a bottom of the source or drain region; and
a dielectric layer between the first contact structure and the first sidewall of the source or drain region, and between the first contact structure and the second sidewall of the source or drain region.
13. The computing device of claim 12, further comprising: a memory coupled to the board.
Anticipated by patented claim 13:
13. The computing device of claim 12, further comprising: a memory coupled to the board.
14. The computing device of claim 12, further comprising: a communication chip coupled to the board.
Anticipated by patented claim 14:
14. The computing device of claim 12, further comprising: a communication chip coupled to the board.
15. The computing device of claim 12, further comprising: a battery coupled to the board.
Anticipated by patented claim 15:
15. The computing device of claim 12, further comprising: a battery coupled to the board.
16. The computing device of claim 12, further comprising: a camera coupled to the board.
Anticipated by patented claim 16:
16. The computing device of claim 12, further comprising: a camera coupled to the board.
17. The computing device of claim 12, further comprising: a speaker coupled to the board.
Anticipated by patented claim 17:
17. The computing device of claim 12, further comprising: a speaker coupled to the board.
18. The computing device of claim 12, further comprising: a GPS coupled to the board.
Anticipated by patented claim 18:
18. The computing device of claim 12, further comprising: a GPS coupled to the board.
19. The computing device of claim 12, further comprising: a motion sensor coupled to the board.
Anticipated by patented claim 19:
19. The computing device of claim 12, further comprising: a motion sensor coupled to the board.
20. The computing device of claim 12, wherein the component is a packaged integrated circuit die.
Anticipated by patented claim 20:
20. The computing device of claim 12, wherein the component is a packaged integrated circuit die.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow et al. (WO 2014/209278 A1, hereinafter refer to Morrow) in view of Yamamoto et al. (U.S. Pat. No. 5,666,002, hereinafter refer to Yamamoto).
Regarding Claim 1: Morrow discloses an integrated circuit structure (see Morrow, Figs. 1A, 2A-2B, 5D, and 6C as shown below and ¶ [001]), comprising:
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a semiconductor body (fins 221/222/223) comprising a source or drain region (225A/226A/227A/228A) (see Morrow, Figs. 1A, 2A, and 5D as shown above, ¶ [035], and ¶ [0038]- ¶ [0039]);
a first contact structure (231/232/233) over a top, along a first sidewall, and along a second sidewall of the source or drain region (225A/226A/227A/228A) (see Morrow, Figs. 1A, 2A, and 5D as shown above and ¶ [0038]- ¶ [0039]);
a second contact structure (142A/130) below and in contact with the first contact structure (231/232/233), the second contact structure (142a/130) extending beneath a bottom of the source or drain region (225A/226A/227A/228A) of the semiconductor body (fins 221/222/223), wherein the second contact structure (142A/130) and the first contact structure (231/232/233) together completely surround, from a cross-sectional perspective, the top, the first sidewall, the second sidewall, and the bottom of the source or drain region (225A/226A/227A/228A) of the semiconductor body (fins 221/222/223) (see Morrow, Figs. 1A, 2A, 2B, and 5D as shown above and ¶ [0038]- ¶ [0039]); and
a dielectric layer (210) between the first contact structure (231/232/233) and a portion of the first sidewall of the source or drain region (225A/226A/227A/228A) of the semiconductor body (fins 221/222/223) (see Morrow, Figs. 1A, 2A, 2B, and 5D as shown above).
Morrow is silent upon explicitly disclosing wherein a dielectric layer between the first contact structure and a portion of the first sidewall of the source or drain region of the semiconductor body, and between the first contact structure and a portion of the second sidewall of the source or drain region of the semiconductor body.
For support see Yamamoto, which teaches wherein a dielectric layer between the first contact structure (9/16) and a portion of the first sidewall of the source or drain region (15) of the semiconductor body, and between the first contact structure (9/16) and a portion of the second sidewall of the source or drain region (15) of the semiconductor body (see Yamamoto, Fig.30 as shown below and col.16, lines 25-35).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Morrow and Yamamoto to enable the dielectric layer between the first contact structure and a portion of the first sidewall of the source or drain region of the semiconductor body, and between the first contact structure and a portion of the second sidewall of the source or drain region of the semiconductor body as taught by Yamamoto in order to ensure sufficient insulation between the semiconductor body and the first contact structure.
Regarding Claim 2: Morrow as modified teaches an integrated circuit structure as set forth in claim 1 as above. The combination of Morrow and Yamamoto further teachers wherein the dielectric layer (210 or 5) is further between the bottom of the source or drain region (225A/226A/227A/228A or 15) and the second contact structure (142A/130 or conductive 9/16 in region 8) (see Morrow, Figs. 1A, 2A, 2B, and 5D as shown above or see Yamamoto, Fig.30 as shown above).
Regarding Claim 3: Morrow as modified teaches an integrated circuit structure as set forth in claim 1 as above. The combination of Morrow and Yamamoto further teachers wherein a dielectric material (210 or 5) between the bottom of the source or drain region (225A/226A/227A/228A or 15) and the second contact structure (142A/130 or conductive 9/16 in region 8) (see Morrow, Figs. 1A, 2A, 2B, and 5D as shown above or see Yamamoto, Fig.30 as shown above).
Regarding Claim 4: Morrow as modified teaches an integrated circuit structure as set forth in claim 1 as above. The combination of Morrow and Yamamoto further teachers wherein the first contact structure (231/232/233) is spaced apart from the top of the semiconductor body (fins 221/222/223) (note: source or drain region (225A/226A/227A/228A) is formed between the first contact structure (231/232/233) the top of the semiconductor body (fins 221/222/223)) (see Morrow, Figs. 1A, 2A, 2B, and 5D as shown above).
Regarding Claim 7: Morrow as modified teaches an integrated circuit structure as set forth in claim 1 as above. The combination of Morrow and Yamamoto further teachers wherein the semiconductor body (fins 221/222/223) is a fin (see Morrow, Figs. 1A, 2A, 2B, and 5D as shown above).
Regarding Claim 8: Morrow as modified teaches an integrated circuit structure as set forth in claim 1 as above. The combination of Morrow and Yamamoto further teachers wherein a gate structure (215) laterally adjacent to the first contact structure (231/232/233) (see Morrow, Fig. 1A as shown above).
Regarding Claim 9: Morrow as modified teaches an integrated circuit structure as set forth in claim 8 as above. The combination of Morrow and Yamamoto further teachers wherein the gate structure (215) is on a top of the semiconductor body (see Morrow, Figs. 1A and 6C as shown above).
Regarding Claim 10: Morrow as modified teaches an integrated circuit structure as set forth in claim 9 as above. The combination of Morrow and Yamamoto further teachers wherein a second source or drain region (225A/226A/227A/228A) at a side of the gate structure (215) opposite the source or drain region (225A/226A/227A/228A) (see Morrow, Figs. 1A and 6C as shown above).
Regarding Claim 11: Morrow as modified teaches an integrated circuit structure as set forth in claim 8 as above. The combination of Morrow and Yamamoto further teachers wherein a second source or drain region (225A/226A/227A/228A) at a side of the gate structure (215) opposite the source or drain region (225A/226A/227A/228A) (see Morrow, Figs. 1A and 6C as shown above).
Regarding Claim 12: Morrow discloses a computing device (see Morrow, Figs. 1A, 2A-2B, 5D, and 6C as shown above and ¶ [001]), comprising:
a board (110) (see Morrow, Fig.1A as shown above); and
a component (100/200) coupled to the board (110), the component (100/200) including an integrated circuit structure (see Morrow, Fig.1A as shown above), the integrated circuit structure (see Morrow, Fig.1A as shown above) comprising:
a semiconductor body (fins 221/222/223) comprising a source or drain region (225A/226A/227A/228A) (see Morrow, Figs. 1A, 2A, and 5D as shown above, ¶ [035], and ¶ [0038]- ¶ [0039]);
a first contact structure (231/232/233) over a top, along a first sidewall, and along a second sidewall of the source or drain region (225A/226A/227A/228A) (see Morrow, Figs. 1A, 2A, and 5D as shown above and ¶ [0038]- ¶ [0039);
a second contact structure (142A/130) below and in contact with the first contact structure (231/232/233), the second contact structure (142a/130) extending beneath a bottom of the source or drain region (225A/226A/227A/228A) of the semiconductor body (fins 221/222/223), wherein the second contact structure (142A/130) and the first contact structure (231/232/233) together completely surround, from a cross-sectional perspective, the top, the first sidewall, the second sidewall, and the bottom of the source or drain region (225A/226A/227A/228A) of the semiconductor body (fins 221/222/223) (see Morrow, Figs. 1A, 2A, 2B, and 5D as shown above and ¶ [0038]- ¶ [0039]); and
a dielectric layer (210) between the first contact structure (231/232/233) and a portion of the first sidewall of the source or drain region (225A/226A/227A/228A) of the semiconductor body (fins 221/222/223) (see Morrow, Figs. 1A, 2A, 2B, and 5D as shown above).
Morrow is silent upon explicitly disclosing wherein a dielectric layer between the first contact structure and a portion of the first sidewall of the source or drain region of the semiconductor body, and between the first contact structure and a portion of the second sidewall of the source or drain region of the semiconductor body.
For support see Yamamoto, which teaches wherein a dielectric layer between the first contact structure (9/16) and a portion of the first sidewall of the source or drain region (15) of the semiconductor body, and between the first contact structure (9/16) and a portion of the second sidewall of the source or drain region (15) of the semiconductor body (see Yamamoto, Fig.30 as shown above and col.16, lines 25-35).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Morrow and Yamamoto to enable the dielectric layer between the first contact structure and a portion of the first sidewall of the source or drain region of the semiconductor body, and between the first contact structure and a portion of the second sidewall of the source or drain region of the semiconductor body as taught by Yamamoto in order to ensure sufficient insulation between the semiconductor body and the first contact structure.
Regarding Claim 13: Morrow as modified teaches a computing device as set forth in claim 12 as above. The combination of Morrow and Yamamoto further teachers wherein a memory coupled to the board (110) (see Morrow, Fig.1A as shown above and Figs.10-11).
Regarding Claim 14: Morrow as modified teaches a computing device as set forth in claim 12 as above. The combination of Morrow and Yamamoto further teachers wherein a communication chip (Antenna) coupled to the board (110) (see Morrow, Fig.1A as shown above and Figs.10-11).
Regarding Claim 15: Morrow as modified teaches a computing device as set forth in claim 12 as above. The combination of Morrow and Yamamoto further teachers wherein a battery coupled to the board (110) (see Morrow, Fig.1A as shown above and Figs.10-11).
Regarding Claim 16: Morrow as modified teaches a computing device as set forth in claim 12 as above. The combination of Morrow and Yamamoto further teachers wherein a camera coupled to the board (110) (see Morrow, Fig.1A as shown above, Figs.10-11, and ¶ [062]).
Regarding Claim 17: Morrow as modified teaches a computing device as set forth in claim 12 as above. The combination of Morrow and Yamamoto further teachers wherein a speaker coupled to the board (110) (see Morrow, Fig.1A as shown above, Figs.10-11, and ¶ [062]).
Regarding Claim 18: Morrow as modified teaches a computing device as set forth in claim 12 as above. The combination of Morrow and Yamamoto further teachers wherein a GPS coupled to the board (see Morrow, Fig.1A as shown above, Figs.10-11, and ¶ [062]).
Regarding Claim 19: Morrow as modified teaches a computing device as set forth in claim 12 as above. The combination of Morrow and Yamamoto further teachers wherein a motion sensor coupled to the board (see Morrow, Fig.1A as shown above, Figs.10-11, and ¶ [062]).
Regarding Claim 20: Morrow as modified teaches a computing device as set forth in claim 12 as above. The combination of Morrow and Yamamoto further teachers wherein the component is a packaged integrated circuit die (see Morrow, Fig.1A as shown above).
Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Morrow et al. (WO 2014/209278 A1, hereinafter refer to Morrow) and Yamamoto et al. (U.S. Pat. No. 5,666,002, hereinafter refer to Yamamoto) as applied to claim 4 above and further in view of Xie et al. (U.S. 2013/0187228 A1, hereinafter refer to Xie).
Regarding Claim 5: Morrow as modified teaches an integrated circuit structure as applied to claim 4 above. The combination of Morrow and Yamamoto is silent upon explicitly disclosing wherein an epitaxial material between the top of the semiconductor body and the first contact structure.
For support see Xie, which teaches an epitaxial material (16A) between the top of the semiconductor body (16) and the first contact structure (46) (see Xie, Figs.1T-1U as shown below, ¶ [0019], and ¶ [0030]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Morrow, Yamamoto, and Xie to enable the combination of Morrow’s and Yamamoto’s source/drain region to be formed of an epitaxial material between the top of the semiconductor body and the first contact structure as taught by Xie in order to achieves an integrated circuit structure with improved source/drain contact resistance.
Regarding Claim 6: Morrow as modified teaches an integrated circuit structure as set forth in claim 5 as above. The combination of Morrow, Yamamoto, and Xie further teaches wherein the epitaxial material (16A) is further partially along the first and second sidewalls of the source or drain region of the semiconductor body (16) (see Xie, Figs.1T-1U as shown below, ¶ [0019], and ¶ [0030]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
