DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on August 19, 2024, has been fully considered by the examiner.
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Memory Device Including a Transfer Circuit and Method for Operating the Device”
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 2-5 and 10-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “the bit line discharged as a program operation is performed” in lines 3-4. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the bit line discharged as a program operation is performed” shall be interpreted as “the bit line connected to the memory cell,” which finds antecedent basis in claim 1, lines 8-9.
Claim 3 recites the limitation “the discharged bit line” in lines 4-5. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the discharged bit line” shall be interpreted as “the bit line connected to the memory cell,” which finds antecedent basis in claim 1, lines 8-9. Claims 4-5 depend on claim 3.
Claim 9 recites the limitation “the memory cell” in lines 4-5, 10, and 14. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the memory cell” in lines 4-5 shall be interpreted as “a memory cell of the at least one memory cell” (see line 3), and “the memory cell” in lines 10 and 14 shall be interpreted as “the memory cell of the at least one memory cell.” Claims 10-17 depend on claim 9.
Claim 11 recites the limitation “The semiconductor apparatus of claim 8” in line 1. There is insufficient antecedent basis for this limitation in the claim (note claim 8 references “a semiconductor apparatus,” but only in the context of a method for operating said apparatus).
For the purpose of this action, “The semiconductor apparatus of claim 8” in line 1 shall be interpreted as “The semiconductor apparatus of claim [[8]] 9.” Claims 12-17 depend on claim 11.
Claim 11 recites the limitation “the memory cell” in line 3. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the memory cell” in line 3 shall be interpreted as “the memory cell of the at least one memory cell.”
Claim 11 recites the limitation “the program pulse with an increased level" in lines 7-8. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the program pulse with an increased level" in lines 7-8 shall be interpreted as, “the program pulse with [[an]] the increased level," which finds antecedent basis in claim 9, line 11.
Claim 17 recites the limitation “the memory cell” in line 3. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the memory cell” in line 3 shall be interpreted as “the memory cell of the at least one memory cell.”
Claim 17 recites the limitation “the program pulse with an increased level" in line 4. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this action, “the program pulse with an increased level" in line 4 shall be interpreted as, “the program pulse with [[an]] the increased level," which find antecedent basis in claim 9, line 11.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-4 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang, et al (US 20220270697 A1), hereinafter Hwang.
Regarding independent claim 1, Hwang teaches a method (FIGS. 12-15) for operating a semiconductor apparatus (FIG. 2), comprising:
receiving a program command (¶[0039]);
applying a program pulse to a memory cell (FIG. 14, S1401);
sensing a threshold voltage of the memory cell (FIG. 15; ¶[0164-0167]);
determining whether a program is completed according to a result of the sensing of the threshold voltage of the memory cell (FIG. 14, S1403, S1405); and
increasing a voltage level of a bit line (e.g., from a program permission voltage) connected to the memory cell by a voltage level corresponding to a level of the threshold voltage of the memory cell according to a determination result in the determining of whether the program has completed (FIG. 15, S1509; ¶[0167] teaches “the memory device 100 applies, to the bit line, a bit line voltage determined based on whether the first verify data and the second verify data correspond to the off-cell data or the on-cell data”).
Regarding claim 2, Hwang teaches the limitations of claim 1.
Hwang further teaches in the increasing of the voltage level of the bit line, the voltage level of the bit line discharged as a program operation is performed from a memory cell in an erase state to a memory cell in a program state is increased (¶[0143] teaches “The voltage of the bit line BL may be decreased when the threshold voltage of the memory cell is lower than the verify voltage Vvfy,” which will be the case when a cell is in an erased state, whereas a programmed cell will have a threshold voltage greater than its verify voltage).
Regarding claim 3, Hwang teaches the limitations of claim 1.
Hwang further teaches in the increasing of the voltage level of the bit line, a voltage of a sensing node with a level increased in the sensing of the threshold voltage of the memory cell is transferred to the discharged bit line (FIG. 12 shows BL_CN and SO_CN simultaneously enable connection circuits 1001 and 1005 in FIGS. 10-11, thereby connecting sense node SO to bit line BL; see also ¶[0142]).
Regarding claim 4, Hwang teaches the limitations of claim 3.
Hwang further teaches increasing a voltage level of the program pulse (FIG. 14, S1405) after the increasing of the voltage level of the bit line (FIG. 14, S1403, which includes FIG. 15, S1509 (see ¶[0160])),
wherein the applying of the program pulse to the memory cell is performed again after the increasing of the voltage level of the program pulse (FIG. 14, S1401).
Regarding claim 6, Hwang teaches the limitations of claim 1.
Hwang further teaches the sensing of the threshold voltage of the memory cell is performed when a sensing node and the bit line are connected (FIG. 12 shows BL_CN and SO_CN simultaneously enable connection circuits 1001 and 1005 in FIGS. 10-11, thereby connecting sense node SO to bit line BL; see also ¶[0142]), a plurality of latches included in a page buffer being commonly connected to the sensing node (¶[0008]).
Regarding claim 7, Hwang teaches the limitations of claim 6.
Hwang further teaches in the determining of whether the program has completed (FIG. 14, S1403, S1407), whether the memory cell has been programmed is determined on the basis of a voltage level of the sensing node when the voltage level of the bit line is transferred to the sensing node (FIG. 15, S1505, “before connection between sensing node and bit line is released”; ¶[0166]).
Regarding claim 8, Hwang teaches the limitations of claim 7.
Hwang further teaches the increasing of the voltage level of the bit line is performed when it is determined in the determining of whether the program has completed that the memory cell has not been programmed (the steps of FIG. 15 are executed within FIG. 14, S1403 (see ¶[0160]); the memory cell has not been programmed when the “N” branch of S1403 is taken).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang, et al (US 20220270697 A1), hereinafter Hwang, in view of Lee (US 20190385658 A1).
Regarding claim 5, Hwang teaches the limitations of claim 4.
Hwang further teaches the increasing of the voltage level of the bit line comprises:
disconnecting the sensing node and the bit line connected in the sensing of the threshold voltage of the memory cell (FIG. 12, CSO_CN disables TR6 (FIG. 11) at time t2, disconnecting sense node SO from bit line BL);
Hwang does not teach discharging the bit line; and
connecting the discharged bit line and the sensing node.
Lee teaches discharging the bit line (FIG. 17, the period from S15 to S16; ¶[0142]).
Hwang as modified by Lee teaches connecting the discharged bit line and the sensing node (Lee FIG. 17, precharge voltage Vpr is applied to bit line BL at time S16; Hwang FIG. 15 S1503 teaches supplying the precharge voltage to each of the bit line and sensing node, which requires a connection between BL and SO (see FIG. 11)).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the method of Hwang to include discharging bit lines. The ordinary artisan would have been motivated to modify Hwang in the above manner for the purpose of performing an equalization operation (Lee ¶[0142], FIG. 17).
10. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190385658 A1) in view of Hwang, et al (US 20220270697 A1), hereinafter Hwang.
Regarding independent claim 9, Lee teaches a semiconductor apparatus (FIG. 2) comprising:
a cell string (FIG. 3, ST) connected between a source line (FIG. 3, SL) and a bit line (FIG. 3, BL1) and comprising at least one memory cell (FIG. 3, F1..F16);
a line driving circuit (FIG. 2, 210, 220) that drives a word line (FIG. 2, LL; ¶[0033]) connected to the memory cell;
a page buffer connected to the bit line (FIG. 2, PB1..PBm, connected to BL1..BLn, respectively); and
a control circuit (FIG. 2, 300) configured to control the line driving circuit (FIG. 2, e.g., OP_CMD to 210) to provide a program pulse to the word line during a program operation (¶[0005]), and control the page buffer through the bit line to determine whether the memory cell has been programmed (¶[0041-0042]),
wherein, before the program pulse with an increased level (i.e., the next ISPP loop; ¶[0072]) after the bit line is discharged (FIG. 17, discharge period from S15 to S16; ¶[0142]) is provided to the word line, the page buffer increases a voltage level of the bit line discharged (FIG. 17, BL voltage increases at S16).
Lee does not teach the bit line voltage level is increased by a voltage level corresponding to a threshold voltage level of the memory cell under the control of the control circuit.
Hwang teaches the bit line voltage level is increased by a voltage level corresponding to a threshold voltage level of the memory cell under the control of the control circuit (FIG. 15, S1509; ¶[0167] teaches “the memory device 100 applies, to the bit line, a bit line voltage determined based on whether the first verify data and the second verify data correspond to the off-cell data or the on-cell data”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Hwang into the method of Lee to include a two-step verify method determining the applied bit line voltage (Hwang, FIG. 15). The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of improved reliability and an improved operation speed (Hwang ¶[0006-0009]).
11. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190385658 A1) in view of Hwang, et al (US 20220270697 A1), hereinafter Hwang, and further in view of Choi (US 20210407606 A1).
Regarding claim 10, Lee as modified by Hwang teaches the limitations of claim 9.
Hwang further teaches the page buffer comprises:
a plurality of latches commonly connected to a sensing node (¶[0008]); and
a connection circuit configured to connect and disconnect the bit line and the sensing node under the control of the control circuit (FIG. 10, e.g., 1001, 1005).
Lee further teaches discharging the bit line under the control of the control circuit (e.g., ¶[0042] and FIG. 2 teaches control logic 300 is responsible for controlling peripheral circuits 200 containing page buffer group 230 to adjust voltages and sequence discharging; bit line discharge is described, e.g., in ¶[0142]).
Lee does not explicitly teach a bit line discharge circuit.
Choi teaches a bit line discharge circuit in a page buffer circuit (FIG. 5, DIS in PB1).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Choi into the method of Lee to include a bit line discharge circuit in a page buffer circuit. The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of discharging a bit line so it may have the level of the ground voltage GND (Choi ¶[0074], FIG. 6).
Regarding claim 11, Lee as modified by Hwang teaches the limitations of claim 9.
Hwang further teaches the connection circuit connects the bit line and the sensing node during a verify operation for determining whether the memory cell has been programmed (FIG. 12 shows BL_CN and SO_CN simultaneously enable connection circuits 1001 and 1005 in FIGS. 10-11, thereby connecting sense node SO to bit line BL; see also ¶[0142]).
Lee as modified by Hwang further teaches connecting the bit line and the sensing node before the program pulse with an increased level is provided to the word line (Lee FIG. 17, precharge voltage Vpr is applied to bit line BL at time S16; Hwang FIG. 15 S1503 teaches supplying the precharge voltage to each of the bit line and sensing node, which occurs before applying the increased program pulse in FIG. 14, S1405 and S1401, and which requires a connection between BL and SO (see FIG. 11)).
Lee does not teach disconnecting the bit line and the sensing node when the bit line is discharged.
Choi teaches disconnecting the bit line and the sensing node when the bit line is discharged (FIG. 6, sense node SO is disconnected from bit line BL while connected through discharge circuit DIS).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Choi into the method of Lee to include disconnecting the bit line and the sensing node when the bit line is discharged. The ordinary artisan would have been motivated to modify Lee in the above manner for the purpose of preventing sense node SO from being discharged (Choi ¶[0067], FIG. 6).
Allowable Subject Matter
12. Claims 12-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
13. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 12, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a third transistor configured to connect the bit line and a fourth transistor based on a voltage level of the transfer node. Claims 13-17 depend on claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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