DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on 5/6/2025, IDS filed on 6/23/2025, IDS filed on 8/12/2025, IDS filed on 9/16/2025, IDS filed on 3/4/2026, and IDS filed on 6/2/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (US 2020/0144380; hereinafter ‘Hwang’).
Regarding claim 1, Hwang teaches a memory device (three-dimensional semiconductor memory device, [0027]), comprising:
a film stack (ST, FIG. 2A, [0028]), comprising:
conductive layers (EL, FIG. 2A, [0028]) and first dielectric layers (ILD, FIG. 2A, [0028]) alternatingly stacked in a first direction (EL and ILD alternatingly stacked in a third direction D3 perpendicular to a top surface of substrate 10, [0028]);
a staircase structure (a stepwise structure of ST, FIG. 2A, [0031]) extending in a second direction perpendicular to the first direction (ST extending in a first direction D1 from CAR toward CNR, wherein D1 is perpendicular to D3, FIG. 2A, [0031-0032]); and
a dividing wall (SP, FIG. 1A, [0063]) extending in the second direction (SP extending in D1, FIG. 1A) and located adjacent to the staircase structure (SP located adjacent to ST in CNR, FIGS. 1A and 2C, [0063, 0066]);
a gate line slit (GLS) (CSP, FIGS. 1A and 2D, [0063]) disposed in the dividing wall (CSP disposed in SP, FIGS. 1A and 2D), wherein the GLS extends through the film stack in the first direction (CSP penetrates ST in D3, FIG. 2D) and extends in the second direction (CSP extends D1, FIG. 1A);
a first barrier layer (25, FIG. 2A, [0035]), comprising:
a first portion (a portion of 25 disposed along and conformably covering the stepwise structure of ST; hereinafter ‘25-1’) disposed on the staircase structure (shown in FIG. 2A); and
a second portion (another portion of 25 extending toward CSP and disposed on a sidewall of SP; hereinafter ‘25-2’) disposed on a sidewall of the dividing wall (shown in FIGS. 3C-3D); and
a second barrier layer (35, FIGS. 1B and 2A, [0035])
disposed on the first portion of the first barrier layer (35 disposed on 25-1, FIG. 2A),
wherein the second barrier layer is different from the first barrier layer (35 has etch selectivity with respect to 25 and includes silicon nitride or silicon oxynitride, whereas 25 includes the same silicon oxide material as ILD, [0030, 0036, 0038]).
Regarding claim 2, Hwang teaches the memory device of claim 1, wherein the first barrier layer covers at least sidewalls of staircase steps of the staircase structure (25 conformally covering the top of surfaces and sidewalls of the steps of ST, FIG. 2A, [0040-0042, 0108]).
Regarding claim 3, Hwang teaches the memory device of claim 2, wherein the second barrier layer covers at least the first barrier layer located at the sidewalls of the staircase steps of the staircase structure (35 conformally covering 25 along the sidewalls of the staircase steps of ST, FIG. 2A, [0040-0043, 0108]).
Regarding claim 4, Hwang teaches the memory device of claim 1, further comprising:
an insulating layer (55, FIG. 2A, [0034]) disposed on the second barrier layer to cover a top surface and sidewalls of the second barrier layer (55 covering the top surface and sidewalls of 35, FIG. 2A).
Regarding claim 5, Hwang teaches the memory device of claim 4, further comprising:
a contact structure (CPLG, FIG. 2A, [0070]), extending through the insulating layer, the second barrier layer and the first barrier layer in the first direction (CPLG extending in D3 through 55, 25, and 35, FIGS. 1A and 2A), wherein the contact structure is in contact with one of the conductive layers of the film stack (CPLG contacting a corresponding electrode EL of ST, FIG. 2A).
Regarding claim 6, Hwang teaches the memory device of claim 1, wherein the second barrier layer is distant from the GLS in a third direction perpendicular to the first direction and the second direction (35 spaced apart from CSP in D2, wherein D2 is perpendicular to directions D3 and D1, FIG. 1B and 3C-3D).
Regarding claim 7, Hwang teaches the memory device of claim 1, wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride (25 corresponding the same silicon oxide dielectric material as ILD, and 35 comprising silicon nitride, [0030, 0036, 0038]).
Regarding claim 10, Hwang teaches a memory device (three-dimensional semiconductor memory device, [0027]), comprising:
a film stack (ST, FIG. 2A, [0028]), comprising:
conductive layers (EL, FIG. 2A, [0028]) and first dielectric layers (ILD, FIG. 2A, [0028]) alternatingly stacked in a first direction (EL and ILD alternatingly stacked in a third direction D3 perpendicular to a top surface of substrate 10, [0028]);
a staircase structure (a stepwise structure of ST, FIG. 2A, [0031]) extending in a second direction perpendicular to the first direction (ST extending in a first direction D1 from CAR toward CNR, wherein D1 is perpendicular to D3, FIG. 2A, [0031-0032]); and
a dividing wall (SP, FIG. 1A, [0063]) extending in the second direction (SP extending in D1, FIG. 1A) and located adjacent to the staircase structure (SP located adjacent to ST in CNR, FIGS. 1A and 2C, [0063, 0066]);
a gate line slit (GLS) (CSP, FIGS. 1A and 2D, [0063]) disposed in the dividing wall (CSP disposed in SP, FIGS. 1A and 2D), wherein the GLS extends through the film stack in the first direction (CSP penetrates ST in D3, FIG. 2D) and extends in the second direction (CSP extends D1, FIG. 1A);
a first barrier layer (25, FIG. 2A, [0035]) disposed on the staircase structure (25 disposed along and conformably covering the stepwise structure of ST, FIG. 2A);
a second barrier layer (35, FIGS. 1B and 2A, [0035]) disposed on the first barrier layer (35 disposed on 25, FIG. 2A), wherein the second barrier layer is different from the first barrier layer (35 has etch selectivity with respect to 25 and includes silicon nitride or silicon oxynitride, whereas 25 includes the same silicon oxide material as ILD, [0030, 0036, 0038]); and
a contact structure (CPLG, FIG. 2A, [0070]), extending through the second barrier layer and the first barrier layer in the first direction (CPLG extending in D3 through 35 and 25, FIG. 2A), wherein the contact structure is in contact with one of the conductive layers of the film stack (CPLG contacting a corresponding electrode EL of ST, FIG. 2A).
Regarding claim 11, Hwang teaches the memory device of claim 10, wherein the first barrier layer covers at least sidewalls of staircase steps of the staircase structure (25 conformally covering the top of surfaces and sidewalls of the steps of ST, FIG. 2A, [0040-0042, 0108]).
Regarding claim 12, Hwang teaches the memory device of claim 11, wherein the second barrier layer covers at least the first barrier layer located at the sidewalls of the staircase steps of the staircase structure (35 conformally covering 25 along the sidewalls of the staircase steps of ST, FIG. 2A, [0040-0043, 0108]).
Regarding claim 13, Hwang teaches the memory device of claim 10, further comprising:
an insulating layer (55, FIG. 2A, [0034]) disposed on the second barrier layer to cover a top surface and sidewalls of the second barrier layer (55 covering the top surface and sidewalls of 35, FIG. 2A), wherein the contact structure extends through the insulating layer in the first direction (CPLG extends through 55 in D3, FIG. 2A).
Regarding claim 14, Hwang teaches the memory device of claim 10, the first barrier layer disposed on a sidewall of the dividing wall (25 disposed on a sidewall of SP, FIGS. 3C-3D).
Regarding claim 15, Hwang teaches the memory device of claim 10, wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride (25 corresponding the same silicon oxide dielectric material as ILD, and 35 comprising silicon nitride, [0030, 0036, 0038]).
Regarding claim 16, Hwang teaches a memory device (three-dimensional semiconductor memory device, [0027]), comprising:
a film stack (ST, FIG. 2A, [0028]), comprising:
conductive layers (EL, FIG. 2A, [0028]) and first dielectric layers (ILD, FIG. 2A, [0028]) alternatingly stacked in a first direction (EL and ILD alternatingly stacked in a third direction D3 perpendicular to a top surface of substrate 10, [0028]);
a staircase structure (a stepwise structure of ST, FIG. 2A, [0031]) extending in a second direction perpendicular to the first direction (ST extending in a first direction D1 from CAR toward CNR, wherein D1 is perpendicular to D3, FIG. 2A, [0031-0032]); and
a dividing wall (SP, FIG. 1A, [0063]) extending in the second direction (SP extending in D1, FIG. 1A) and located adjacent to the staircase structure (SP located adjacent to ST in CNR, FIGS. 1A and 2C, [0063, 0066]);
a gate line slit (GLS) (CSP, FIGS. 1A and 2D, [0063]) disposed in the dividing wall (CSP disposed in SP, FIGS. 1A and 2D), wherein the GLS extends through the film stack in the first direction (CSP penetrates ST in D3, FIG. 2D) and extends in the second direction (CSP extends D1, FIG. 1A);
a first barrier layer (25, FIG. 2A, [0035]) disposed on the staircase structure (25 disposed along and conformably covering the stepwise structure of ST, FIG. 2A); and
a second barrier layer (35, FIGS. 1B and 2A, [0035]) disposed on the first barrier layer (35 disposed on 25, FIG. 2A), wherein the second barrier layer is different from the first barrier layer (35 has etch selectivity with respect to 25 and includes silicon nitride or silicon oxynitride, whereas 25 includes the same silicon oxide material as ILD, [0030, 0036, 0038]) and the first barrier layer and the second barrier layer covers at least sidewalls of staircase steps of the staircase structure (25 and 35 conformally covering at least the sidewalls of the staircase steps of ST, FIG. 2A).
Regarding claim 17, Hwang teaches the memory device of claim 16, further comprising:
an insulating layer (55, FIG. 2A, [0034]) disposed on the second barrier layer to cover a top surface and sidewalls of the second barrier layer (55 covering the top surface and sidewalls of 35, FIG. 2A).
Regarding claim 18, Hwang teaches the memory device of claim 17, further comprising:
a contact structure (CPLG, FIG. 2A, [0070]), extending through the insulating layer, the second barrier layer and the first barrier layer in the first direction (CPLG extending in D3 through 55, 25, and 35, FIGS. 1A and 2A), wherein the contact structure is in contact with one of the conductive layers of the film stack (CPLG contacting a corresponding electrode EL of ST, FIG. 2A).
Regarding claim 19, Hwang teaches the memory device of claim 16, wherein the first barrier layer comprises silicon oxide and the second barrier layer comprises silicon nitride (25 corresponding the same silicon oxide dielectric material as ILD, and 35 comprising silicon nitride, [0030, 0036, 0038]).
Regarding claim 20, Hwang teaches the memory device of claim 16, the first barrier layer disposed on a sidewall of the dividing wall (25 disposed on a sidewall of SP adjacent to CSP, FIGS. 3C-3D).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 2020/0144380) in view of Yu et al. (US 2018/0330985; hereinafter ‘Yu’).
Regarding claim 8, Hwang teaches the memory device of claim 1, but does not teach the memory device wherein the first barrier layer comprises a thickness in a range between 10 nm to 100 nm.
Yu teaches a memory device (3D NAND structure, [0003]) wherein the first barrier layer (encapsulation layer 1180, FIG. 11, [0079]) comprises a thickness in a range between 10 nm to 100 nm (encapsulation layer has a thickness of about 1 nm to about 250 nm, [0005]).
As taught by Yu, one of ordinary skill in the art would utilize and modify the above teaching into Hwang to obtain and achieve the memory device wherein the first barrier layer comprises a thickness in a range between 10 nm to 100 nm as claimed, because a sufficient thickness in required to encapsulate and protect the staircase structure during subsequent etching processes [0003-0005, 0045]. Further, it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Yu in combination with Hwang due to the above reason.
Regarding claim 9, Hwang teaches the memory device of claim 1, but does not teach the memory device wherein the second barrier layer comprises a thickness in a range between 50 nm to 500 nm.
Yu teaches a memory device (3D NAND structure, [0003]) wherein the first barrier layer (encapsulation layer 1180, FIG. 11, [0079]) comprises a thickness in a range between 50 nm to 500 nm (encapsulation layer has a thickness of about 1 nm to about 350 nm, [0050]).
As taught by Yu, one of ordinary skill in the art would utilize and modify the above teaching into Hwang to obtain and achieve the memory device wherein the first barrier layer comprises a thickness in a range between 50 nm to 500 nm as claimed, because a sufficient thickness in required to encapsulate and protect the staircase structure during subsequent etching processes [0003-0005, 0045]. Further, it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Yu in combination with Hwang due to the above reason.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that SHIMIZU (US 2020/0273879), Kim et al. (US 2017/0117222), and SUN et al. (US 2020/0194447) as a three-dimensional memory device having a staircase patterned film stack.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/16/26
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