DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Akihiro (JP 2013031325), Bernard et al. (U.S. Patent Application Publication Number 2010/0001586), and Chou et al. (U.S. Patent Application Publication Number 2019/0213091).
Regarding Claim 1, Akihiro discloses a power supply (Figure 1, item U1) comprising:
a processor (Figure 2, item 15, paragraphs 0026-0028 and 0040; i.e., the calculation unit 15 processes the detection results from voltage detector 11 and current detector 12 [from itself as well as from the other uninterruptable power supplies] and in response controls the number of uninterruptable power supplies to be used and is therefore equivalent to the claimed “processor”);
a communication line (Figure 1, item 5) communicatively coupled to a plurality of redundant power supplies (Figure 1, items U2 and U3, paragraph 0019);
a plurality of components (Figures 1/2, items 1, 2, and SW0) configured to provide power to a device (Figure 1, item 6, paragraph 0017);
a memory (Figure 2, item 16 with item 17), wherein the memory comprises a cold redundancy logic (Figure 2, item 16, paragraphs 0028-0029), configured to direct the power supply to:
generate a ranking for each of the plurality of redundant power supplies (paragraph 0029; i.e., the priority order [equivalent to the claimed “ranking”] of each uninterruptable power supply U1-U3 is generated based on its respective position);
assign the ranking to each of the plurality of redundant power supplies (paragraph 0029; i.e., the rankings of each uninterruptable power supply U1-U3 is assigned and then stored in storage unit 17);
determine whether a change in activity state is required (paragraph 0033; i.e., a particular power supply [e.g., power supply U1] decides/determines when to enter a standby mode);
transmit a change in activity state to at least one of the plurality of redundant power supplies via the communication line (paragraph 0033; i.e., when a particular power supply [e.g., power supply U1] decides to enter a standby mode, it transmits a signal [the claimed “change in activity state signal”] to the other power supplies U2 and U3 indicating that change via communication line 5).
Akihiro does not expressly disclose wherein the power supply is to gather a plurality of input factors;
format an activity state signal for transmission, wherein the activity state signal is modulated to a high-frequency signal and wherein formatting involves setting at least one of a voltage level, frequency, and protocol.
In the same field of endeavor (e.g., redundant power supplies), Bernard teaches wherein the power supply (Figure 2A, item 261) is to gather a plurality of input factors (paragraphs 0029 and 0031; i.e., the “plurality of factors” may include the BBU priority, availability, status, and other conditions).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Bernard’s teachings of redundant power supplies with the teachings of Akihiro, for the purpose of providing the ability to select the best backup power supply (e.g., a most efficient power supply) to use in the event of power failure.
Also in the same field of endeavor (e.g., redundant power supplies), Chou teaches format an activity state signal for transmission, wherein the activity state signal is modulated to a high-frequency signal and wherein formatting involves setting at least one of a voltage level, frequency, and protocol (Figure 2, item 128, paragraphs 0032-0033; i.e., the CMC 220 within a power supply 128 transmits an activity state signal to the management switch 110 by formatting the signal to the I2C standard [the claimed “protocol”]; the I2C standard allows devices to transmit signals at up to 5 Mbps [equivalent to the claimed “high-frequency signal”] - see attached article “A Basic Guide to I2C”, Table 1-1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Chou’s teachings of redundant power supplies with the teachings of Akihiro, for the purpose of allowing more data to be transmitted per second and for standardizing communication rules between the various devices, thereby resulting in more reliable data integrity.
Regarding Claim 2, Bernard teaches wherein the plurality of input factors includes attribute data associated with the plurality of redundant power supplies (paragraphs 0029 and 0031).
Regarding Claim 3, Bernard teaches wherein the attribute data includes at least one of: a power factor (paragraphs 0032 and 0034; i.e., the charge status of each BBU being equivalent to the claimed “power factor”), phase, efficiency, or a current load.
Regarding Claim 4, Bernard teaches wherein the ranking (paragraph 0031; i.e., a priority of each BBU) is generated based on the plurality of input factors (paragraph 0032; i.e., the priority of each BBU is based on various factors such as its capacity and charge).
Regarding Claim 5, Bernard teaches wherein the ranking is configured to associate a more efficient power supply with a higher ranking (paragraph 0034; i.e., rankings may be based on which BBUs have common power, charge, voltage, or other capacities, which is corresponds to being more efficient with selecting the power supplies).
Regarding Claim 6, Akihiro discloses wherein the ranking is assigned via the communication line (paragraph 0037; i.e., a user can enter the various rankings/priorities for each of the power supplies U1-U3 into the memory 17 of a first power supply U1, after which those rankings/priorities are distributed to the other power supplies U2 and U3 via communication line 5).
Regarding Claim 7, Akihiro discloses wherein the communication line is utilized for load balancing between the power supply and the plurality of redundant power supplies (paragraph 0027).
Regarding Claim 8, Akihiro discloses wherein the communication line is an I-share line paragraph 0027; i.e., the instant specification defines this feature to mean “a dedicated connection between parallel PSUs that enables active current sharing and balanced load distribution among the PSUs” [paragraph 0043]; Akihiro states that “the shared currents of the plurality of uninterruptible power supply devices U1 to U3 are equal on the basis of the detection results of the voltage detector 11 and the current detector 12 of the uninterruptible power supply devicesU1 to U3”; this information sharing occurs via the communication line 5; therefore, Akihiro discloses an “I-share line”).
Regarding Claim 9, Bernard teaches wherein, prior to transmission, the cold redundancy logic is further configured to monitor the device (paragraph 0029).
Regarding Claim 10, Bernard teaches wherein, prior to transmission, the cold redundancy logic is further configured to determine that a change in activity state is needed based on the monitoring (paragraph 0029).
Regarding Claim 11, Bernard teaches wherein, prior to transmission, the cold redundancy logic is further configured to format the change in activity state (paragraph 0029; i.e., the “format” is the particular power mode that the ONT 230 enters into).
Regarding Claim 12, Akihiro discloses wherein, the communication line is utilized to transmit a lower-frequency signal between the power supply and the plurality of redundant power supplies (paragraph 0026; i.e., communications occur between the various power supplies via the bus 5; the claim does not state what the “lower-frequency signal” [specifically, which signal frequency it is lower than] is relative to and therefore the frequency at which the communications occur in Akihiro is equivalent to the claimed feature).
Regarding Claim 14, Bernard teaches wherein the activity state includes an active state (paragraph 0029; i.e., the ONT 230 can enable one of the BBUs to take over [enter into an active state]).
Regarding Claim 15, Bernard teaches wherein the activity state includes a sleep state (paragraph 0038; i.e., once the AC power is restored, the ONT resumes normal operation, which would include no longer using the BBU; Bernard does not expressly state that the unused BBUs enter a sleep state, however Akihiro teaches this feature [see paragraph 0032 - the selected power supply can enter a standby state]).
Regarding Claim 20, Akihiro discloses a method of managing power supplies (Figure 1, items U1-U3) comprising:
generating a ranking for each of the one or more redundant power supplies (paragraph 0029; i.e., the priority order [equivalent to the claimed “ranking”] of each uninterruptable power supply U1-U3 is generated based on its respective position);
assigning the ranking to each of the one or more redundant power supplies via a communication line coupled to each of the one or more redundant power supplies (paragraph 0037; i.e., a user can enter the various rankings/priorities for each of the power supplies U1-U3 into the memory 17 of a first power supply U1, after which those rankings/priorities are forwarded to the other power supplies U2 and U3 by the command unit 16 via communication line 5); and
transmitting a change in activity state to at least one of the one or more redundant power supplies via the communication line (paragraph 0033; i.e., when a particular power supply [e.g., power supply U1] decides to enter a standby mode, it transmits a signal [the claimed “change in activity state signal”] to the other power supplies U2 and U3 indicating that change via communication line 5);
determining whether a change in activity state is required (paragraph 0033; i.e., a particular power supply [e.g., power supply U1] decides/determines when to enter a standby mode).
Akihiro does not expressly disclose gathering a plurality of input factors associated with one or more redundant power supplies;
formatting an activity state signal for transmission, wherein the activity state signal is modulated to a high-frequency signal and wherein formatting involves setting at least one of a voltage level, frequency, and protocol.
In the same field of endeavor, Bernard teaches gathering a plurality of input factors associated with one or more redundant power supplies (paragraphs 0029 and 0031; i.e., the “plurality of factors” may include the BBU priority, availability, status, and other conditions).
Also in the same field of endeavor, Chou teaches formatting an activity state signal for transmission, wherein the activity state signal is modulated to a high-frequency signal and wherein formatting involves setting at least one of a voltage level, frequency, and protocol (Figure 2, item 128, paragraphs 0032-0033; i.e., the CMC 220 within a power supply 128 transmits an activity state signal to the management switch 110 by formatting the signal to the I2C standard [the claimed “protocol”]; the I2C standard allows devices to transmit signals at up to 5 Mbps [equivalent to the claimed “high-frequency signal”] - see attached article “A Basic Guide to I2C”, Table 1-1).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 20.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Akihiro, Bernard, and Chou as applied to claim 12 above, and further in view of Horikoshi et al. (U.S. Patent Application Publication Number 2025/0309855).
Regarding Claim 13, Akihiro, Bernard, and Chou do not expressly disclose wherein the formatting comprises generating a higher-frequency signal compared to the lower-frequency signal, such that the higher-frequency signal can be received by the plurality of redundant power supplies through a high-pass filter applied to the communication line.
In the same field of endeavor (e.g., power supply communication techniques), Horikoshi teaches wherein the formatting comprises generating a higher-frequency signal compared to the lower-frequency signal, such that the higher-frequency signal can be received by the plurality of redundant power supplies (Figure 1, item 10, paragraph 0021; i.e., the combination of references would contain a plurality of redundant power supplies) through a high-pass filter applied to the communication line (Figure 3, item HP11, paragraph 0073).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Horikoshi’s teachings of power supply communication techniques with the teachings of Akihiro, Bernard, and Chou, for the purpose of being able to send the signals to and from the redundant power supplies without introducing noise.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Akihiro and Chou.
Regarding Claim 16, Akihiro discloses a power supply (Figure 1, item U2, paragraph 0013; i.e., all of the power supplies U1-U3 contain the same components) comprising:
a processor (Figure 2, item 15, paragraphs 0026-0028 and 0040; i.e., the calculation unit 15 processes the detection results from voltage detector 11 and current detector 12 [from itself as well as from the other uninterruptable power supplies] and in response controls the number of uninterruptable power supplies to be used and is therefore equivalent to the claimed “processor”);
a communication line (Figure 1, item 5) communicatively coupled to a plurality of additional power supplies within a power supply system (Figure 1, items U1 and U3, paragraph 0019);
a plurality of components (Figures 1/2, items 1, 2, and SW0) configured to provide power to a device (Figure 1, item 6, paragraph 0017); and
a memory (Figure 2, item 16 with item 17), wherein the memory comprises a cold redundancy logic (Figure 2, item 16, paragraphs 0028-0029), configured to direct the power supply to:
receive a ranking (i.e., a priority) from one of the plurality of additional power supplies (paragraph 0037; i.e., a user can enter the various rankings/priorities for each of the power supplies U1-U3 into the memory 17 of a first power supply U1, after which those rankings/priorities are forwarded to the other power supplies U2 and U3 by the command unit 16);
modify an activity state based on the ranking (paragraphs 0032-0034; i.e., depending on the assigned ranking/priority, the power supply U2 will decide to enter a standby state or active state [the claimed “activity state”]);
monitor a signal received via the communication line (paragraph 0027; i.e., detection results [the claimed “signal”] of the voltage detector 11 and current detector 12 are shared between all of the power supplies U1-U3);
receive a change in activity state signal (paragraph 0033; i.e., when a particular power supply [e.g., power supply U1] decides to enter a standby mode, it transmits a signal [the claimed “change in activity state signal”] to the other power supplies U2 and U3 indicating that change); and
change a current activity state of the power supply (paragraph 0033; i.e., if the power supply U2 is in a ranking/priority where it needs to enter a standby state, it would do so [the claimed “change a current activity state”]).
Akihiro does not expressly disclose wherein the activity state signal is modulated to a high-frequency signal and wherein formatting involves setting at least one of a voltage level, frequency, and protocol.
In the same field of endeavor (e.g., redundant power supplies), Chou teaches wherein the activity state signal is modulated to a high-frequency signal and wherein formatting involves setting at least one of a voltage level, frequency, and protocol (Figure 2, item 128, paragraphs 0032-0033; i.e., the CMC 220 within a power supply 128 transmits an activity state signal to the management switch 110 by formatting the signal to the I2C standard [the claimed “protocol”]; the I2C standard allows devices to transmit signals at up to 5 Mbps [equivalent to the claimed “high-frequency signal”] - see attached article “A Basic Guide to I2C”, Table 1-1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Chou’s teachings of redundant power supplies with the teachings of Akihiro, for the purpose of allowing more data to be transmitted per second and for standardizing communication rules between the various devices, thereby resulting in more reliable data integrity.
Regarding Claim 17, Akihiro discloses wherein the ranking comprises configuration data (paragraph 0037; i.e., the priority information being equivalent to the claimed “configuration data”).
Regarding Claim 18, Akihiro discloses wherein the change in activity state signal is received via the communication line (Figure 1, item 5, paragraph 0033).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Akihiro and Chou as applied to claim 18 above, and further in view of Horikoshi.
Regarding Claim 19, Akihiro and Chou do not expressly disclose wherein a high-pass filter is applied to the communication line for receiving the change in activity state signal.
In the same field of endeavor (e.g., power supply communication techniques), Horikoshi teaches wherein a high-pass filter is applied to the communication line for receiving the change in activity state signal (Figure 3, item HP11, paragraph 0073).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Horikoshi’s teachings of power supply communication techniques with the teachings of Akihiro and Chou, for the purpose of being able to send the signals to and from the redundant power supplies without introducing noise.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a system for ranking redundant power supplies.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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