DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed 22 December, 2025 has been entered. Claims 2-21 remain pending in the application. Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed 26 September, 2025. Examiner further acknowledges the filing of a terminal disclaimer which has overcome the rejection under double patenting, as well as amendments to the claims which have been rejected upon further search and consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian et al (U.S. Patent Pub. No. 2011/0222547), hereinafter referred to as Subramanian, in view of Matsumoto et al (U.S. Patent No. 5,881,017), hereinafter referred to as Matsumoto, Ohhashi et al (U.S. Patent Pub. No. 2010/0250872), hereinafter referred to as Ohhashi, and Saito et al (U.S. Patent Pub. No. 2008/0133809), hereinafter referred to as Saito.
In regard to claim 2, Subramanian teaches a memory component comprising: a plurality of memory banks (Fig. 2 memories 220; Paragraph 0015, lines 1-5 four banks) and a data interface block configured to transfer data between the memory component and an external component (Fig. 2 packet processor 210 communicates externally using packets); and a plurality of separate communication buses coupled between each memory bank of the plurality of memory banks and the data interface block (Fig. 2 data buses DQ; Paragraph 0015, lines 11-15 each memory bank has its own data bus).
Subramanian does not directly teach the remaining limitations of claim 2. However, Matsumoto teaches an embodiment of a memory component including memory banks wherein each of the plurality of memory banks comprises a plurality of storage cells (Fig. 1 memory cell array banks 71) wherein each communication bus of the plurality of separate communication buses is configured to transfer respective data segments (Fig. 1 sense amplifier buses input to read pre-amplifiers; Column 22, line 59 to Column 23, line 4 each bank stores a different set of columns of data which are transferred during operation), from alternating memory banks of the plurality of memory banks on alternating buses of the plurality of separate communication buses (Fig. 21, timing diagram showing alternating bus and bank read accesses on read preamplifier buses A0 and A1) during respective time periods that at least partially overlap (Fig. 21, transfer operations from A0 and A1 overlap before output, see RBA0 and RBA1 signals times t0-t2). One of ordinary skill in the art could readily implement the memory banks of Matsumoto and their read bus control circuitry in the memory system of Subramanian and its disclosed separate buses, achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Matsumoto in order to perform an interleaved memory operation and benefit from fast operations in SDRAM (Column 7, lines 21-24).
Previously cited references do not disclose buses having a data width equal to a specific data transfer size, however Ohhashi teaches an apparatus for accessing a memory bank (see Fig. 1; buses MWDATA and MRDATA transfer data from the memory bank) having buses with a 256 bit width (¶ 0024, lines 4-7) equal to an access (data transfer) size (¶ 0024, lines 1-5, the data transfer of the access must practically have a size of 256 bits to be satisfied with a burst of four 64-bit transfers or one 256-bit transfer). One of ordinary skill in the art could combine these disclosures in the packet processor of Subramanian which accesses memory banks. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Ohhashi in order to complete accesses in fewer command cycles by matching the data width of buses to the size of accesses (¶ 0024).
Matsumoto does not explicitly disclose an embodiment wherein each data segment is associated with different data access commands directed to alternating memory banks, however Saito teaches an embodiment of a memory component wherein alternating banks receive individual commands and column addresses for read data outputs (Fig. 7), achieving the claimed limitation. One of ordinary skill in the art could readily implement command processing circuitry disclosed by Saito (Fig. 4) in the memory banks outlined above to achieve this limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Saito in order to direct data access commands to different banks and "improve access efficiency of semiconductor memory" (Paragraph 0003).
As for claim 3, the previously cited references teach the memory component of claim 2. Additionally, Saito discloses an embodiment wherein data is transferred on alternating buses separated by a delay period (see Fig. 7, data transferred on bus 15 followed by transfer on bus 17 after a delay), achieving the claimed limitation.
As for claim 4, the previously cited references teach the memory component of claim 2. Additionally, Matsumoto teaches an embodiment wherein data segments (data in cells) are transferred on alternating buses during time periods that overlap. Fig. 21 shows read preamplifier and register outputs which contain data transferred from memory banks A0 and A1. The transfer of cell data from banks A0 and A1 (Column 22, lines 30-34 memory cells are sense amplified) occurs during overlapping time periods as shown. Connecting these direct output buses as described in the disclosure of Subramanian would result in data being transferred to the interface block on alternating buses during overlapping time periods, achieving the claimed limitation.
As for claim 5, the previously cited references teach the memory component of claim 4. Additionally, Matsumoto discloses alternating between the two buses to read multiple different storage cells during the alternating read process (Column 22, lines 22-64; e.g. reading a third cell onto the first bus in an overlapping time period; see Fig. 21 again), achieving the claimed limitation.
Claims 8-12 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian in view of Matsumoto, Ohhashi, Saito, and Ware et al (U.S. Patent Pub. No. 2011/0283060), hereinafter referred to as Ware.
As for claim 8, the previously cited references teach the memory component of claim 2. They do not teach the remaining limitations of claim 8. However, Ware teaches a command interface coupled to a plurality of memory banks which receives commands including memory bank location addresses from a memory controller (Fig. 1 Interface 25 connected to banks in core 19a; Paragraph 0026, command interface receives command from controller including command/address and data links), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Ware in order to issue commands directly to banks and improve performance in a memory component (Paragraph 0027, lines 12-17).
As for claim 9, applicant is directed to the rejection of claims 2 and 8 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 10, applicant is directed to the rejection of claim 3 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 11, applicant is directed to the rejection of claim 4 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 12, applicant is directed to the rejection of claim 5 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 15, the previously cited references teach the memory component of claim 9. Additionally, Ohhashi teaches an apparatus for accessing a memory bank (see Fig. 1; buses MWDATA and MRDATA transfer data from the memory bank) having buses with a 256 bit width (¶ 0024, lines 4-7) equal to an access (data transfer) size (¶ 0024, lines 1-5, the data transfer of the access must have a size of 256 bits to be satisfied with a burst of four 64-bit transfers or one 256-bit transfer. A person of ordinary skill could incorporate this matching data width with the communication buses in the cited references, achieving the claimed limitations.
As for claim 16, applicant is directed to the rejection of claims 2 and 8 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 17, applicant is directed to the rejection of claim 3 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 18, applicant is directed to the rejection of claim 4 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 19, applicant is directed to the rejection of claim 5 above, as the claims include the same limitations and are therefore rejected on the same rationale.
Claims 6, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian in view of Matsumoto, Saito, and Hsieh (U.S. Patent No. 6,212,194).
In regard to claim 6, the previously cited references teach the memory component of claim 2. They do not teach the remaining limitations of claim 6. However, Hsieh teaches a state machine arbitrating bus routing circuitry coupled to a plurality of buses (e.g. buses coupled to memory banks disclosed in Subramanian) that rotates among a plurality of states (Fig. 6; located in arbitrator 92 shown in Fig. 5; system of Fig. 5 is bus routing system of Fig. 1; Column 13, lines 21-34 state machine outputs are port IDs rotating through the coupled seed generator), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Hsieh to improve bus arbitration (Hsieh Column 1, lines 66-70 disclose this as a goal of the invention).
As for claim 13, applicant is directed to the rejection of claim 6 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 20, applicant is directed to the rejection of claim 6 above, as the claims include the same limitations and are therefore rejected on the same rationale.
Claims 7, 14, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian in view of Matsumoto, Ohhashi, Saito, and Jeddeloh et al (U.S. Patent Pub. No. 2010/0110745), hereinafter referred to as Jeddeloh.
In regard to claim 7, the previously cited references teach the memory component of claim 2. They do not teach the remaining limitations of claim 7. However, Jeddeloh teaches a memory system including an interface utilizing serialization for communication with a host (see serializers and deserializers 112 in Fig. 1). If combined with the modified memory system of Subramanian, data from memory banks would be serialized before communication to an external component, achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Jeddeloh in order to serialize data from multiple memory banks and benefit from increased bandwidth, parallelism, and scalability (Paragraph 0014, lines 7-8).
As for claim 14, applicant is directed to the rejection of claim 7 above, as the claims include the same limitations and are therefore rejected on the same rationale.
As for claim 21, applicant is directed to the rejection of claim 7 above, as the claims include the same limitations and are therefore rejected on the same rationale.
Response to Arguments
Applicant's arguments (see page 10 of response filed 22 December, 2025) have been fully considered but they are not persuasive. Applicant argues that Matsumoto does not teach buses having a data width equal to a data transfer size. The newly amended limitations have resulted in further search and consideration, wherein reference Ohhashi was found to teach buses having a data width equal to a data transfer size, which are also alternatively selectable. This reference more accurately captures the slightly broader scope of the claim resulting from changing “memory access request size” to read “data transfer size”. Importantly, a “request size” indicates the presence of a requestor and target and some form of metadata included in communications. A “data transfer size” indicates only the size of transfer of some data. Additionally, the newly cited reference captures the exemplary embodiment of buses having a 256 bit width to transfer data (see instant application, ¶ 0022, 0033, 0037). This has been addressed in the updated rejections of amended claims 2, 15, and 16.
Remarks regarding the relevance of Matsumoto in teaching claimed limitations (see pages 15-16 of response) were considered but found unpersuasive. Matsumoto’s disclosure is related to accessing memory banks using buses, and essentially takes the form of a group of memory banks having an integrated interface for output. The cited benefit of Matsumoto is increasing the operation speed of SDRAM, a common form of memory module which is additionally referenced in the instant specification (¶ 0021). This device would be obviously relevant to one of ordinary skill in the art when considering various methods or systems of interfacing with memory banks. Therefore, arguments that Matsumoto does not teach claimed limitations were also found unpersuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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