DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20220059657 A1 to Noborio et al. (hereinafter “Noborio”).
Regarding claim 1, Noborio teaches a semiconductor device (figs. 1-5) comprising:
a semiconductor substrate (underlying layers wherein are disposed the conductive features, namely elements 1, 2, and 2a, hereinafter “substrate”; fig. 2) [0032] of silicon carbide [0031];
a trench (gate trench 6; fig. 2) [0037] formed in an upper surface (vertically upper) of the semiconductor substrate (substrate);
a gate insulating film (7; fig. 2) [0039] formed on an inner surface (in the trench) of the trench (8);
gate wiring (gate electrode 8; fig. 2) [0039] formed on the gate insulating film (7) and embedded (surrounded by) in the trench (8); and
a gate lifting portion (region RC) being a region in which a portion of the gate wiring (8b; fig. 4) [0089] is lifted (vertically higher; see fig. 4) from the trench (6; see fig. 4) onto the upper surface (vertically upper) of the semiconductor substrate (substrate),
wherein a side wall (vertical wall of 6; fig. 4) of the trench (6) in the gate lifting portion (approaching vertically upper portion) includes:
a vertical portion (vertical portion annotated below) being perpendicular to the upper surface (vertically upper) of the semiconductor substrate (substrate);
a horizontal portion (horizontal portion annotated below) located at a top (vertically top) of the trench (6) and being parallel to the upper surface (upper surface) of the semiconductor substrate (substrate); and
a sloped portion (sloped portion annotated below) located in a shoulder portion (peripheral; fig. 4 being a cross section of line IV-IV from fig. 1) of the trench (6) and provided between the vertical portion (vertical portion) and the horizontal portion (horizontal portion),
the sloped portion (sloped portion) has been sloped (angled) so that the trench (6) is widened upward (widened vertically upward in fig. 4), and is straight in cross section (see fig. 4), and
in cross section (fig. 4), a corner (transition of vertical portion and sloped portion) of the vertical portion (vertical portion) and the sloped portion (sloped portion) does not protrude inward (protrudes horizontally in fig. 4) of the trench (6) from a region (region of transition between vertical portion and sloped portion) between a tangent (line defined by plane thereof) to the vertical portion (vertical portion) and a tangent (line defined by the plan thereof) to the sloped portion (sloped portion).
It is noted that claim 1 recites the term “formed.” This term is considered as a process limitation. In such cases, only the structure implied by the process step is limiting. M.P.E.P. 2113.
Regarding claim 4, Noborio teaches the semiconductor device according to claim 1, wherein in the gate lifting portion (RC), a portion (portion of 3; fig. 4) [0033] of the semiconductor substrate (substrate) at least adjacent to the vertical portion of the trench (6) is a P type semiconductor layer [0033].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Noborio as applied to claim 1 above, and further in view of U.S. Pat. Pub. No. US 20130285140 A1 to Kagawa et al. (hereinafter “Kagawa”).
Regarding claim 2, Noborio teaches the semiconductor device according to claim 1, wherein the trench extends into a drift layer (n-type current dispersion layer 2a; fig. 2) [0031] of a first conductivity type (n-type) [0031], and
Noborio does not teach a field relaxation layer of a second conductivity type is formed at a bottom of the trench.
Kagawa, however, teaches teaches a semiconductor device (trench-gate type MOSFET of fig. 2) [0033] comprising a field relaxation layer (p-type protective diffusion layer 13; fig. 2) [0036] of a second conductivity type (p-type) [0036] formed at a bottom of the trench (5; fig. 2) [0035].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the semiconductor device of Noborio to comprise a field relaxation layer (of p-type) at a bottom of the trench to enhance the depletion of the drift layer to prevent breakdown of the gate insulating film as taught by Kagawa [0036].
It is noted that claim 2 recites the term “formed.” This term is considered as a process limitation. In such cases, only the structure implied by the process step is limiting. M.P.E.P. 2113.
Regarding claim 3, Noborio in view of Kagawa teaches the semiconductor device according to claim 2, wherein an impurity layer (p-type base region 3; fig. 5) [0033] of the second conductivity type (p-type) [0033] connected (electrically) to the field relaxation layer (13 of Kagawa) is formed on a portion of the side wall (vertical sidewall) of the trench (6).
It is noted that claim 3 recites the term “formed.” This term is considered as a process limitation. In such cases, only the structure implied by the process step is limiting. M.P.E.P. 2113.
Regarding claim 5, Noborio in view of Kagawa teaches the semiconductor device according to claim 2, wherein in the gate lifting portion (RC), a portion (portion of 3; fig. 4) [0033] of the semiconductor substrate (substrate) at least adjacent to the vertical portion of the trench (6) is a P type semiconductor layer [0033].
Regarding claim 6, Noborio in view of Kagawa teaches the semiconductor device according to claim 3, wherein in the gate lifting portion (RC), a portion (portion of 3; fig. 4) [0033] of the semiconductor substrate (substrate) at least adjacent to the vertical portion of the trench (6) is a P type semiconductor layer [0033].
Allowable Subject Matter
Claims 7-10 allowed.
Regarding claim 7, it is not found a reference which reasonably reads on “reducing the mask; forming a sloped portion in a shoulder portion of the trench by first etching using the reduced mask; and etching, after the first etching, a corner of the vertical portion and the sloped portion by second etching using the reduced mask.” The closest references found are:
US 20130168701 A1 to Kiyosawa et al. (hereinafter “Kiyosawa”) which teaches the second formation step for a corner in a trench (formation of 51; fig. 2) but this step is done through annealing [0075]. It is noted that Kiyosawa teaches that etching is possible for the corner formation step [0089], but that such a process would result in a rounded corner 51. Kiyosawa at least shows a preference to the annealing process, as this process avoids some damage in the trench (see e.g., ¶ [0085]), i.e., there may be an argument against combination.
JP 2000277488 A to Onozawa (hereinafter “Onozawa”) which teaches the process required by claim 7 including steps of trench formation (figs. 3 and 4), mask reduction (fig. 5), sloped portion formation (fig. 5), and corner formation (figs. 6 and 7); and teaches that these processes increase electric field concentration. But the resulting structure is a tapered edge, not a corner (see figs. 1-11). It is noted that the broadest reasonable interpretation of corner (where two edges meet at an angle) may allow for Onozawa to read on claim 7 when only the figures are considered. However, when Onozawa is considered as a whole i.e., including the description and, in particular, the discussion surrounding the tapered edge, the Examiner believes it is more likely than not that a combination of Noborio and Onozawa is not obvious i.e., a prima facie case of obviousness cannot be established.
Claims 8-10 are allowed by virtue of their dependence on an allowable claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time.
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/ETHAN EDWARD CUTLER/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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