DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities: in line 7, replace “equal to toggle signal” with --equal to the toggle signal--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McCollough et al. (U.S. Patent Number 6,121,849).
Regarding Claim 1, McCollough discloses an integrated circuit (Figure 1, item 11) comprising:
logic circuitry configured to perform a function within the integrated circuit (Figure 1, item 14, Column 3, lines 22-33);
a monitored clock source (Figure 1, item 21) configured to provide a monitored clock signal (Figure 1, item 54) to the logic circuitry, wherein the monitored clock source is predetermined to output the monitored clock signal at a specified operating frequency (Column 4, lines 32-42; i.e., the “specified operating frequency” of system clock 54 is the same as the reference clock 48 frequency);
a reference clock source configured to generate a reference clock signal (Figure 1, item 16, Column 5, lines 8-21); and
a clock monitoring system (Figure 1, item 12) comprising:
a toggle signal generator (Figure 1, items 18 and 20) configured to generate a toggle signal using the reference clock signal (Column 3, lines 56-64 and Column 4, lines 16-29; i.e., the reference signal 48 is equivalent to the claimed “toggle signal”),
a clock signal detector (Figure 1, item 24) coupled to the toggle signal generator (i.e., indirectly through monitored clock source 21) and the monitored clock source, wherein the clock signal detector is configured to generate an output signal (Figure 1, item 46) equal to the toggle signal (Column 4, lines 30-50; i.e., assuming the variable ‘N’ is 1, the output signal 46 will have a frequency that is identical to the frequency of toggle signal 48 [the output signal of clock signal detector 24 is therefore “equal to the toggle signal”]) when the monitored clock signal is present at an input to the clock signal detector (Column 4, lines 30-50; i.e., the clock signal detector 24 will only provide the output signal 46 equal to the toggle signal 48 when the monitored clock signal 54 is present at the input of clock signal detector 24; if no clock is being output from monitored clock source 21, then the output signal 46 would not be equal to the toggle signal 48); and
a loss of clock detector (Figure 1, item 22) coupled to the toggle signal generator and the clock signal detector, wherein the loss of clock detector is configured to:
compare the output signal of the clock signal detector to the toggle signal (Column 4, lines 51-52); and
when the output signal of the clock signal detector is not equal to the toggle signal, generate an output signal indicative of a loss of clock signal condition (Figure 1, item 52, Column 5, lines 2-7).
Regarding Claim 7, McCollough discloses wherein the toggle signal generator and the loss of clock detector are implemented within a clock monitoring unit (CMU) (Figure 1, items 18/20 and 22; i.e., the components 18, 20, and 22 are considered equivalent to the claimed “clock monitoring unit”) and the clock signal detector is external to and is not implemented within the CMU (Figure 1, item 24).
Regarding Claim 16, McCollough discloses a method comprising:
receiving a reference clock signal (Figure 1, item 16, Column 5, lines 8-21);
generating a toggle signal using the reference clock signal (Column 3, lines 56-64 and Column 4, lines 16-29; i.e., the reference signal 48 is equivalent to the claimed “toggle signal”);
generating a clock detector output signal (Figure 1, item 46) equal to the toggle signal (Column 4, lines 30-50; i.e., assuming the variable ‘N’ is 1, the output signal 46 will have a frequency that is identical to the frequency of toggle signal 48 [the output signal of clock signal detector 24 is therefore “equal to the toggle signal”]) when a monitored clock signal (Figure 1, item 54) is received (Column 4, lines 30-50; i.e., the clock signal detector 24 will only provide the output signal 46 equal to the toggle signal 48 when the monitored clock signal 54 is present at the input of clock signal detector 24; if no clock is being output from monitored clock source 21, then the output signal 46 would not be equal to the toggle signal 48);
comparing the clock detector output signal to the toggle signal (Column 4, lines 51-52); and
when the clock detector output signal is not equal to the toggle signal, generating an output signal indicative of a loss of clock signal condition (Figure 1, item 52, Column 5, lines 2-7).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over McCollough as applied to claims 1 and 16 above, and further in view of Sridharan et al. (U.S. Patent Number 12,261,609).
Regarding Claim 2, McCollough does not expressly disclose wherein the monitored clock source includes a clock divider network.
In the same field of endeavor (e.g., clock monitoring techniques), Sridharan teaches wherein the monitored clock source (Figure 5, item 500; i.e., a PLL) includes a clock divider network (Figure 5, items 505, 540, and 550, Column 8, lines 54-50 and Column 9, lines 21-26).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Sridharan’s teachings of clock monitoring techniques with the teachings of McCollough, for the purpose of allowing the monitored clock source to output clock signals of different frequencies, thereby allowing for greater flexibility in the use of the logic components.
Regarding Claim 3, Sridharan teaches wherein a frequency of the monitored clock signal is different from a frequency of the reference clock signal (Figure 5, item 501, Column 9, lines 21-26).
Regarding Claim 20, Sridharan teaches wherein receive the monitored clock signal includes receiving a clock signal from a clock divider network (Figure 5, items 505, 540, and 550, Column 8, lines 54-50 and Column 9, lines 21-26).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over McCollough and Sridharan as applied to claim 3 above, and further in view of Duggal et al. (U.S. Patent Application Publication Number 2019/0041440).
Regarding Claim 4, McCollough and Sridharan do not expressly disclose wherein the clock monitoring system includes a memory storing a value of an evaluation window duration, and the toggle signal is configured to alternate between a high value and a low value at a frequency determined by the evaluation window duration.
In the same field of endeavor (e.g., clock monitoring techniques), Duggal teaches wherein the clock monitoring system includes a memory storing a value of an evaluation window duration (paragraph 0109; i.e., the time duration of monitoring the clock is held constant, which would indicate that it is stored in a memory), and the toggle signal is configured to alternate between a high value and a low value at a frequency determined by the evaluation window duration (paragraphs 0038-0039; i.e., the synchronized count enable signal 128 [the “toggle signal”] alternates between high and low at a frequency that is defined by the defined time duration/window [the “evaluation window duration”]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Duggal’s teachings of clock monitoring techniques with the teachings of McCollough and Sridharan, for the purpose of providing a specific amount of time that the clock monitoring system would need to be powered on, thereby allowing it to be powered off when it is outside of the evaluation time window.
Regarding Claim 5, Duggal teaches wherein the evaluation window duration is determined by the frequency of the monitored clock signal (paragraph 0109; i.e., the evaluation window duration would necessarily be longer than a plurality of clock pulses of the incoming clock signal 124-1 [the “monitored clock signal”] so that the monitor processor can properly evaluate whether it is within a threshold range of the reference clock 122 [see paragraph 0098]).
Regarding Claim 6, Duggal teaches a plurality of clock signal detectors (Figure 7, items 110) coupled to processors (Figure 7, items 510, paragraph 0073), wherein the loss of clock detector is configured to receive signals from the plurality of clock signal detectors to detect a loss-of-clock conditions in at least one of the processors within a single evaluation window duration (paragraph 0098; i.e., a fail indicates the clock signal is outside the respective frequency range, which could include a complete loss of clock signal) and wherein the integrated circuit does not include a plurality of a plurality of clock monitoring units that each require two or more evaluation window durations to detect a clock signal fault (Figure 7, item 540, paragraphs 0094-0095; i.e., there is only a single clock monitoring unit 540 and it only requires a single evaluation window duration).
Claims 8 are rejected under 35 U.S.C. 103 as being unpatentable over McCollough as applied to claim 1 above, and further in view of Berzins et al. (U.S. Patent Application Publication Number 2015/0200652).
Regarding Claim 8, McCollough does not expressly disclose wherein the clock signal detector includes a first latch, a data input of the first latch is configured to receive the toggle signal, and a clock input of the first latch is configured to receive the monitored clock signal.
In the same field of endeavor (e.g., clock monitoring techniques), Berzins teaches wherein the clock signal detector (Figure 1A, item 135) includes a first latch (Figure 1A, item 105), a data input of the first latch is configured to receive the toggle signal (Figure 1A, item 112), and a clock input of the first latch is configured to receive the monitored clock signal (Figure 1A, item CK, paragraphs 0035-0036).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Berzin’s teachings of clock monitoring techniques with the teachings of McCollough, for the purpose of a low-power, high-speed, and area-efficient data storage for receiving the toggle signal (as opposed to, e.g., flip-flops or other types of memory).
Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over McCollough and Duggal.
Regarding Claim 9, McCollough discloses a clock monitoring system comprising:
a first input (Figure 1, see input to item 24) configured to receive a monitored clock signal (Figure 1, item 54);
a second input (Figure 1, items 32 and 34) configured to receive a reference clock signal (Figure 1, item 16, Column 5, lines 8-21);
a toggle signal generator (Figure 1, items 18 and 20) configured to generate a toggle signal using the reference clock signal (Column 3, lines 56-64 and Column 4, lines 16-29; i.e., the reference signal 48 is equivalent to the claimed “toggle signal”),
a clock signal detector (Figure 1, item 24) coupled to the toggle signal generator (i.e., indirectly through monitored clock source 21) and configured to receive the monitored clock signal, wherein the clock signal detector is configured to generate an output signal (Figure 1, item 46) equal to the toggle signal (Column 4, lines 30-50; i.e., assuming the variable ‘N’ is 1, the output signal 46 will have a frequency that is identical to the frequency of toggle signal 48 [the output signal of clock signal detector 24 is therefore “equal to the toggle signal”]) when the monitored clock signal is present at an input to the clock signal detector (Column 4, lines 30-50; i.e., the clock signal detector 24 will only provide the output signal 46 equal to the toggle signal 48 when the monitored clock signal 54 is present at the input of clock signal detector 24; if no clock is being output from monitored clock source 21, then the output signal 46 would not be equal to the toggle signal 48); and
a loss of clock detector (Figure 1, item 22) coupled to the toggle signal generator and the clock signal detector, wherein the loss of clock detector is configured to:
compare the output signal of the clock signal detector to the toggle signal (Column 4, lines 51-52); and
when the output signal of the clock signal detector is not equal to toggle signal, generate an output signal indicative of a loss of clock signal condition (Figure 1, item 52, Column 5, lines 2-7).
McCollough does not expressly disclose a window duration memory unit configured to store a value determining an evaluation window duration;
the toggle signal generator is configured to use the evaluation window duration to generate the toggle signal.
In the same field of endeavor (e.g., clock monitoring techniques), Duggal teaches a window duration memory unit configured to store a value determining an evaluation window duration (paragraph 0038 and 0109; i.e., the time duration of monitoring the clock [the claimed “evaluation window duration”], which can be based on a reference clock signal 122, is held constant which would indicate that it is stored in a memory);
the toggle signal generator (Figure 1, item 120) is configured to use the evaluation window duration to generate the toggle signal (Figure 1, item 127, paragraphs 0036 and 0039-0040; i.e., the toggle signal 127 [which is synchronized with the monitored clock signal 124] is generated during/using the evaluation window duration to enable the up counter 130 to continue to detect and count the monitored clock signal 124).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Duggal’s teachings of clock monitoring techniques with the teachings of McCollough, for the purpose of providing a specific amount of time that the clock monitoring system would need to be powered on, thereby allowing it to be powered off when it is outside of the evaluation time window.
Regarding Claim 15, McCollough discloses wherein the clock monitoring system is incorporated into an automotive microcontroller (Column 3, lines 19-35; i.e., the types of circuitry [e.g., a CPU] that the IC circuitry may be can be used in an automative application).
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over McCollough and Duggal as applied to claim 9 above, and further in view of Sridharan.
Regarding Claim 10, McCollough and Duggal do not expressly disclose wherein the monitored clock signal is received from a clock divider network.
In the same field of endeavor (e.g., clock monitoring techniques), Sridharan teaches wherein the monitored clock signal is received from a clock divider network (Figure 5, items 505, 540, and 550, Column 8, lines 54-50 and Column 9, lines 21-26).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Sridharan’s teachings of clock monitoring techniques with the teachings of McCollough and Duggal, for the purpose of allowing the monitored clock source to output clock signals of different frequencies, thereby allowing for greater flexibility in the use of the logic components.
Regarding Claim 11, Sridharan teaches wherein a frequency of the monitored clock signal is different from a frequency of the reference clock signal (Figure 5, item 501, Column 9, lines 21-26).
Regarding Claim 12, Duggal teaches wherein the toggle signal is configured to alternate between a high value and a low value at a frequency determined by the evaluation window duration (paragraphs 0038-0039; i.e., the synchronized count enable signal 128 [the “toggle signal”] alternates between high and low at a frequency that is defined by the defined time duration/window [the “evaluation window duration”]).
Regarding Claim 13, Duggal teaches wherein the evaluation window duration is determined by the frequency of the monitored clock signal (paragraph 0109; i.e., the evaluation window duration would necessarily be longer than a plurality of clock pulses of the incoming clock signal 124-1 [the “monitored clock signal”] so that the monitor processor can properly evaluate whether it is within a threshold range of the reference clock 122 [see paragraph 0098]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over McCollough and Duggal as applied to claim 9 above, and further in view of Berzins.
Regarding Claim 14, McCollough and Duggal do not expressly disclose wherein the clock signal detector includes a first latch, a data input of the first latch is configured to receive the toggle signal, and a clock input of the first latch is configured to receive the monitored clock signal.
In the same field of endeavor (e.g., clock monitoring techniques), Berzins teaches wherein the clock signal detector (Figure 1A, item 135) includes a first latch (Figure 1A, item 105), a data input of the first latch is configured to receive the toggle signal (Figure 1A, item 112), and a clock input of the first latch is configured to receive the monitored clock signal (Figure 1A, item CK, paragraphs 0035-0036).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Berzin’s teachings of clock monitoring techniques with the teachings of McCollough and Duggal, for the purpose of a low-power, high-speed, and area-efficient data storage for receiving the toggle signal (as opposed to, e.g., flip-flops or other types of memory).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over McCollough as applied to claim 16 above, and further in view of Duggal.
Regarding Claim 17, McCollough does not expressly disclose receiving an evaluation window duration; and
causing the toggle signal to alternate between a high value and a low value at a frequency determined by the evaluation window duration.
In the same field of endeavor (e.g., clock monitoring techniques), Duggal teaches receiving an evaluation window duration (paragraph 0109; i.e., the time duration of monitoring the clock is held constant, which would indicate that it is stored in a memory); and
causing the toggle signal to alternate between a high value and a low value at a frequency determined by the evaluation window duration (paragraphs 0038-0039; i.e., the synchronized count enable signal 128 [the “toggle signal”] alternates between high and low at a frequency that is defined by the defined time duration/window [the “evaluation window duration”]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Duggal’s teachings of clock monitoring techniques with the teachings of McCollough, for the purpose of providing a specific amount of time that the clock monitoring system would need to be powered on, thereby allowing it to be powered off when it is outside of the evaluation time window.
Regarding Claim 18, Duggal teaches determining the evaluation window duration using a frequency of the monitored clock signal (paragraph 0109; i.e., the evaluation window duration would necessarily be longer than a plurality of clock pulses of the incoming clock signal 124-1 [the “monitored clock signal”] so that the monitor processor can properly evaluate whether it is within a threshold range of the reference clock 122 [see paragraph 0098]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over McCollough as applied to claim 16 above, and further in view of Berzins.
Regarding Claim 19, McCollough does not expressly disclose receiving the toggle signal at a data input of a first latch; and receiving the monitored clock signal at a clock input of the first latch.
In the same field of endeavor (e.g., clock monitoring techniques), Berzins teaches receiving the toggle signal (Figure 1A, item 112) at a data input of a first latch (Figure 1A, item 105); and receiving the monitored clock signal at a clock input of the first latch (Figure 1A, item CK, paragraphs 0035-0036).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Berzin’s teachings of clock monitoring techniques with the teachings of McCollough, for the purpose of a low-power, high-speed, and area-efficient data storage for receiving the toggle signal (as opposed to, e.g., flip-flops or other types of memory).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a device for detecting a loss of clock.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175