Prosecution Insights
Last updated: October 01, 2026
Application No. 18/809,472

Selective Dielectric Capping for Hybrid Bonding

Non-Final OA §103
Filed
Aug 20, 2024
Priority
Nov 03, 2023 — provisional 63/547,222
Examiner
HOSSAIN, MOAZZAM
Art Unit
Tech Center
Assignee
Nanyang Technological University
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
746 granted / 847 resolved
+28.1% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
39 currently pending
Career history
868
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 847 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Prosecution This office action considers claims 1-20, in Claims - 03/24/2023, pending for prosecution and are examined on their merits. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 1A; [0022] or C 18, L 18-37)= (element 100; Figure No. 1; Paragraph No. [0022]) or Column No 18, Line Nos. 18-17. For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” or “Column No, Line Nos" shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claims 1, 2, 7-9, 11-15, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Triyoso; Dina H. et al. (US 20230009688 A1) hereinafter referenced as Triyoso in view of Goradia; Prerna (US 20220356582 A1); hereinafter referenced as Goradia Regarding Claim 1. Triyoso teaches a method (processes; Figs 4A-4D; [0015, 0049+]) for increasing dielectric bonding strength during wafer-level processing, comprising (See the entire document Figs 3A-3D along with other figures and relevant disclosures, claims 1,6, [0025-0075], specifically; as cited below): (see below for “immersing a substrate into a chemical bath, wherein the chemical bath) forms a self-assembled monolayer (306 in Step 434; fig 4D; [005] corresponding to Fig 3C; [0034-0035]) on at least one metal surface (304) of the substrate (3); and selectively depositing (step 444; Fig 4D; [0063] corresponding to Fig 3D; [0036]) a dielectric material (of high-k; [0043]) to form a dielectric cap (308; Fig 3D; [0043]) on at least one dielectric surface (301) of the substrate (3) absent of the self-assembled monolayer. But, Triyoso does not expressly disclose “immersing a substrate into a chemical bath , wherein the chemical bath”; However, in the analogous art, Goradia teaches amethod of coating an l conductive metal layer on a non-conductive surface of articles contacting the chemistries at room temperature for short durations is disclosed. The methodology is non non-toxic aqueous bath of different salt.. The cost-effective methodology can be used on a wide variety of non-conductive surfaces such as glass, fibers, textiles, ceramic, plastic, foam and so on (Title). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to modify Triyoso’s coating module 120 by Goradia process and , thereby the combination of (Triyoso and Goradia) comprises immersing a substrate (3) into a chemical bath (Goradia), wherein the chemical bath forms a self-assembled monolayer (306 in Step 434; fig 4D; [005] corresponding to Fig 3C; [0034-0035]) on at least one metal surface (304) of the substrate (3),since this process, at least, provides a big change in the electroless plating technology in chemical processes industry, which is a low cost, easy to be deployed methodology that is manufacturable, for different types of articles(Goradia [0052]). Regarding Claim 2. the combination of (Triyoso and Goradia) as applied to the method of claim 1, further teaches, wherein immersing the substrate into the chemical bath (Goradia [0052]) occurs at atmospheric pressure and ambient temperature. Regarding Claim 7. the combination of (Triyoso and Goradia) as applied to the method of claim 1, further teaches, wherein the chemical bath includes an alkanethiol (Goradia [0018,0042]). Regarding Claim 8,. the combination of (Triyoso and Goradia) as applied to the method of claim 1, further teaches, wherein the alkanethiol (Goradia [0018, 0042]) has a linear structure or a benzene ring structure. Regarding Claim 9. the combination of (Triyoso and Goradia) as applied to the method of claim 1, further teaches, wherein the dielectric material is a high-k ([0043) dielectric material. Regarding Claim 11. the combination of (Triyoso and Goradia) as applied to the method of claim 1, further teaches, wherein the substrate is immersed in the chemical bath for approximately 10 minutes (Goradia [0016]) to approximately 30 minutes. Regarding Claim 12. the combination of (Triyoso and Goradia) as applied to the method of claim 1, further teaches, wherein ([0030])) the metal surface is copper, silver, gold, palladium, platinum, cobalt, titanium, nickel, or combinations thereof. Regarding Claim 13. the combination of (Triyoso and Goradia) as applied to the method of claim 1, wherein a thickness of the dielectric material is greater than zero nm to approximately 10nm (obvious as it is more than zero nm see Fig 3E and from the [0037]). Regarding Claim 14. Triyoso teaches a method (processes; Figs 4A-4D; [0015, 0049+]) for increasing dielectric bonding strength during wafer-level processing, comprising (See the entire document Figs 3A-3D along with other figures and relevant disclosures, claims 1,6, [0025-0075], specifically; as cited below): (see below for “immersing a substrate into a chemical bath, wherein the chemical bath) forms a self-assembled monolayer (306 in Step 434; fig 4D; [005] corresponding to Fig 3C; [0034-0035]) on at least one metal surface (304) of the substrate (3); and (see below for “ wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature)[AltContent: ] selectively depositing (step 444; Fig 4D; [0063] corresponding to Fig 3D; [0036]) a high-k dielectric material (high-k; [0043]) to form a dielectric cap (308; Fig 3D; [0043]) on at least one dielectric surface (301) of the substrate (3) absent of the self-assembled monolayer. wherein a thickness of the high-k dielectric material is greater than zero nm to approximately 10nm (obviousas it is more than zero nm see Fig 3E and from the [0037]). But, Triyoso does not expressly disclose “immersing a substrate into a chemical bath , wherein the chemical bath” and “ wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature” However, in the analogous art, Goradia teaches a method of coating a conductive metal layer on a non-conductive surface of articles contacting the chemistries at room temperature for short durations is disclosed. The methodology is non-toxic aqueous bath of different salt.. The cost-effective methodology can be used on a wide variety of non-conductive surfaces such as glass, fibers, textiles, ceramic, plastic, foam and so on (Title, [0052]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to modify Triyoso’s coating module 120 by Goradia process and , thereby the combination of (Triyoso and Goradia) comprises immersing a substrate (3) into a chemical bath (Goradia), wherein the chemical bath forms a self-assembled monolayer (306 in Step 434; fig 4D; [005] corresponding to Fig 3C; [0034-0035]) on at least one metal surface (304) of the substrate (3), and wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature (Goradia) ,since this process, at least, provides a big change in the electroless plating technology in chemical processes industry, which is a low cost, easy to be deployed methodology that is manufacturable, for different types of articles(Goradia [0052]). Regarding Claim 15. the combination of (Triyoso and Goradia) as applied to the method of claim 14, further teaches, wherein the substrate is immersed in the chemical bath for approximately 10 minutes (Goradia [0016]) to approximately 30 minutes. Regarding Claim 17. the combination of (Triyoso and Goradia) as applied to the method of claim 14, further teaches, wherein the chemical bath includes an alkanethiol with a linear structure or a benzene ring structure. Regarding Claim 18. the combination of (Triyoso and Goradia) as applied to the method of claim 14, further teaches, wherein the alkanethiol (Goradia [0018, 0042]) has a linear structure or a benzene ring structure. Regarding Claim 20. Triyoso teaches A non-transitory, computer readable medium ([0017] having instructions stored thereon (construed from Fig 1; [0017] he controller 114 includes one or more computer processors 116 and memory 118 storing computer-executable instructions that may be executed by the computer processors or other logic/processing devices. The controller 114 may store process component 136 than can include a recipe or process condition routines that may be implemented by controlling or directing the components of the system 100 to obtain certain conditions within the coating module 104 and/or the anneal module 112 ) that, when executed, cause a method (processes; Figs 4A-4D; [0015, 0049+]) for increasing dielectric bonding strength during wafer-level processing, comprising (See the entire document Figs 3A-3D along with other figures and relevant disclosures, claims 1,6, [0025-0075], specifically; as cited below): (see below for “immersing a substrate into a chemical bath, wherein the chemical bath) forms a self-assembled monolayer (306 in Step 434; fig 4D; [005] corresponding to Fig 3C; [0034-0035]) on at least one metal surface (304) of the substrate (3); and (see below for “ wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature). selectively depositing (step 444; Fig 4D; [0063] corresponding to Fig 3D; [0036]) a dielectric material (high-k; [0043]) to form a dielectric cap (308; Fig 3D; [0043]) on at least one dielectric surface (301) of the substrate (3) absent of the self-assembled monolayer. But, Triyoso does not expressly disclose “immersing a substrate into a chemical bath , wherein the chemical bath” and “ wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature” However, in the analogous art, Goradia teaches a method of coating a conductive metal layer on a non-conductive surface of articles contacting the chemistries at room temperature for short durations is disclosed. The methodology is non non-toxic aqueous bath of different salt.. The cost-effective methodology can be used on a wide variety of non-conductive surfaces such as glass, fibers, textiles, ceramic, plastic, foam and so on (Title,[0062]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to modify Triyoso’s coating module 120 by Goradia process and , thereby the combination of (Triyoso and Goradia) comprises immersing a substrate (3) into a chemical bath (Goradia), wherein the chemical bath forms a self-assembled monolayer (306 in Step 434; fig 4D; [005] corresponding to Fig 3C; [0034-0035]) on at least one metal surface (304) of the substrate (3), and wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature (Goradia) ,since this process, at least, provides a big change in the electroless plating technology in chemical processes industry, which is a low cost, easy to be deployed methodology that is manufacturable, for different types of articles(Goradia [0052]). Claims 3-6 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Triyoso; Dina H. et al. (US 20230009688 A1) hereinafter referenced as Triyoso; in view of Goradia; Prerna (US 20220356582 A1); hereinafter referenced as Goradia; and in further view of Rogers; Jack et al. (US 20230253361 A1); hereinafter referenced as Rogers. Regarding Claim 3,16. the combination of (Triyoso and Goradia) as applied to the method of claim 1 and/or 15, while further teaches, (the method) further comprising: removing the self-assembled monolayer (step 450; fig 4D, 3E; [0053]) from the substrate (3); but, does not expressly disclose bonding the dielectric material of the substrate to another substrate with surfaces covered by the dielectric material by contacting substrates together; and annealing substrates to bond metal surfaces together. However, in the analogous art, Rogers teaches a method of hybrid bonding and, more particularly, to technologies for plasma oxidation protection of bonding pads during hybrid bonding of semiconductor devices ([0001]), wherein (Figs 3B,11-12, [0061]) in step 334, bonding the dielectric material of the substrate (102) to another substrate (104) with surfaces covered by the dielectric material (112) by contacting substrates together; and annealing (steps 346) substrates to bond metal surfaces (120) together. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, to modify the combination of (Triyoso and Goradia) method with teaching of Rogers’s bonding step 334 and annealing step 336) and , thereafter the combination of (Triyoso, Goradia and Rogers) comprises the process steps as claimed. ,since this inclusion, at least, contacts the treated bonding surfaces and annealing to complete hybrid bonding.of two substrate (Rogers [0061]). Regarding Claim 4, 17. the combination of (Triyoso, Goradia and Rogers) as applied to the method of claim 3 and or 17, further teaches, (the method) further comprising: removing the self-assembled monolayer (step 450; fig 4D; [0046]) using a plasma-based process ([0046]) for approximately 10 seconds to approximately 60 seconds. Regarding Claim 5. the combination of (Triyoso, Goradia and Rogers as applied to the method of claim 3, further teaches, wherein the substrate is a die ([0029]). Regarding Claim 6. the combination of (Triyoso, Goradia and Rogers as applied to the method of claim 3, further teaches, wherein annealing occurs at a temperature of approximately 150 degrees Celsius (obvious from Rogers [0061] annealed at a temperature in the range of about 100 degrees Celsius to about 400 degrees Celsius; see MPEP 2144.05, I). Examiner like to not that while, Rogers does not explicitly teaches the temperature of approximately 150 degrees Celsius, some of its value fall within the claim range, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. See MPEP 2144.05, I. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to enable using “annealed at a temperature in the range of about 100 degrees Celsius to about 400 degrees Celsius”, as disclosed in prior art, to arrive at the recited limitation of temperature of approximately 150 degrees Celsius. Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Triyoso; Dina H. et al. (US 20230009688 A1) hereinafter referenced as Triyoso; in view of Goradia; Prerna (US 20220356582 A1); hereinafter referenced as Goradia; and in further view of CHANG; Chung-Wei et al. (US 20230062572 A1); hereinafter referenced as Chang. Regarding Claim 10, 19. the combination of (Triyoso and Goradia) as applied to the method of claim 1 and/or claim 14, while further teaches, wherein the high-k ([0043]) dielectric material but does not expressly disclose either “aluminum oxide or hafnium oxide”. However, the examiner takes official notice that both aluminum oxide or hafnium oxide is known in the art. For example, in the analogous art, Chang discloses ([0060]) both “aluminum oxide or hafnium oxide” are of high-k materials. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of what is well known into the method of the combination of (Triyoso and Goradia). The ordinary artisan would have been motivated to modify . the combination of (Triyoso and Goradia) in the manner set forth above for at least the purpose of utilizing known material to ensure successful device operation. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898 August 18, 2026
Read full office action

Prosecution Timeline

Aug 20, 2024
Application Filed
Oct 15, 2024
Response after Non-Final Action
Aug 20, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+11.1%)
2y 4m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 847 resolved cases by this examiner. Grant probability derived from career allowance rate.

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