DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by a first interpretation of US 20210391335 (Xia).
As to claim 1: A first interpretation of Xia teaches a semiconductor device comprising a capacitor structure (Xia Fig 25), the capacitor structure positioned on a substrate and comprising:
a first electrode structure comprising a plurality of first horizontal electrode portions and a first conductive pillar (380 comprising 382 and 381), the plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the substrate (382 spaced apart along vertical direction), and the first conductive pillar connected to each first horizontal electrode portion of the plurality of first horizontal electrode portions and extending in the first direction (381 connect to 382 and extend vertically);
a second electrode structure comprising a plurality of second horizontal electrode portions and a second conductive pillar (360 comprising 361 and 340), the second conductive pillar extending through the plurality of first horizontal electrode portions in the first direction (340 extend between 382 in vertical direction), and the plurality of second horizontal electrode portions spaced apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the plurality of first horizontal electrode portions (361 alternate vertically with 382); and
a capacitor dielectric layer between the side wall of the second conductive pillar and the plurality of first horizontal electrode portions (370), and the capacitor dielectric layer on an upper surface, a side surface, and a bottom surface of each second horizontal electrode portion of the plurality of second horizontal electrode portions (370 having claimed disposition).
As to claim 2: Xia teaches the semiconductor device of claim 1, wherein the second conductive pillar has a circular planar shape (Fig 27 340 circular), and
wherein each second horizontal electrode portion of the plurality of second horizontal electrode portions has an annular planar shape surrounding the second conductive pillar (382 annular around 340).
As to claim 3: Xia teaches the semiconductor device of claim 2, wherein a side surface of at least one second horizontal electrode portion of the plurality of second horizontal electrode portions forms a concentric circle with a side surface of a portion of the second conductive pillar (interface between 361 and 340 forms concentric circles), the portion of the second conductive pillar being at a same level as the at least one second horizontal electrode portion (features at a same vertical height).
As to claim 4: Xia teaches the semiconductor device of claim 1, wherein the first conductive pillar extends in a first horizontal direction (381 extends into page), and wherein the second conductive pillar extends in the first horizontal direction and is spaced apart from the first conductive pillar in a second horizontal direction (340 extends into page and separated horizontally from 381).
As to claim 5: Xia teaches the semiconductor device of claim 4, wherein each second horizontal electrode portion of the plurality of second horizontal electrode portions comprises a first sub-electrode portion on a first side surface of the second conductive pillar (portion of 361 connected to 340) and a second sub-electrode portion on a second side surface of the second conductive pillar, the second side surface opposite to the first side surface (portion of 361 away from 340), and
wherein in the second horizontal direction, a width of the first sub-electrode portion is same as a width of the second sub-electrode portion (split two portions of 361 equally).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-8, and 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over a second interpretation of Xia and US 20180323200 (Tang et al).
As to claim 1: A second interpretation of Xia teaches a semiconductor device comprising a capacitor structure (Xiao Fig 25), the capacitor structure positioned on a substrate and comprising:
a first electrode structure comprising a plurality of first horizontal electrode portions and a first conductive pillar (380 comprising 382 and 381), the plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the substrate (382 spaced apart along vertical direction), and the first conductive pillar connected to each first horizontal electrode portion of the plurality of first horizontal electrode portions and extending in the first direction (381 connect to 382 and extend vertically);
a second electrode structure comprising a plurality of second horizontal electrode portions and a second conductive pillar (360 comprising 361 and 340), the second conductive pillar extending through the plurality of first horizontal electrode portions in the first direction (340 extend between 382 in vertical direction), and the plurality of second horizontal electrode portions spaced apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the plurality of first horizontal electrode portions (361 alternate vertically with 382); and
Xia fails to explicitly teach a capacitor dielectric layer or disposition thereof.
Tang teaches a device similar to that of Xia, and explicitly teaches the inclusion of a capacitor dielectric layer between conductive electrode portions (Fig 1 shows conductor 26 and neighboring 52, plus Fig 44 shows detailed view with silicon nitride layer 35 therebetween), and the capacitor dielectric layer on an upper surface, a side surface, and a bottom surface of each second horizontal electrode portion of the plurality of second horizontal electrode portions (35 around upper/side/lower surfaces of 26).
All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing.
As to claim 6: Xia+Tang teach the semiconductor device of claim 1. Xia further teaches wherein the first electrode structure comprises a plurality of mold insulating layers alternately arranged with the plurality of first horizontal electrode portions (Fig 25, 370 alternate with 382), wherein the plurality of mold insulating layers respectively comprise a plurality of openings (openings at same level as 330), and the plurality of mold insulating layers overlap each other in the first direction (overlap along vertical direction), and wherein the plurality of second horizontal electrode portions are arranged in the plurality of openings (361 therein).
As to claim 7: Xia+Tang teach the semiconductor device of claim 6. Tang, as applied to claim 1, further teaches wherein a portion of the capacitor dielectric layer is in a respective opening of the plurality of openings of the plurality of mold insulating layers (layer 35 of Tang on electrodes and therefore in the openings of Xia).
As to claim 8: Xia+Tang teach the semiconductor of claim 6. Tang, as applied to claim 1, further teaches wherein a portion of the capacitor dielectric layer is in contact with a respective mold insulating layer of the plurality of mold insulating layers (layers 35 of Tang on electrodes and therefore contact mold layers 370 also in contact)
As to claim 11: Xia+Tang teach the semiconductor device of claim 1. Xia further teaches wherein each first horizontal electrode portion of the plurality of first horizontal electrode portions comprises a first concavo-convex surface (outside surfaces forming a convex surface as seen in view of Fig 27), and wherein each second horizontal electrode portion of the plurality of second horizontal electrode portions comprises a second concavo-convex surface conforming to a shape of the first concavo-convex surface (analogous surface of second horizontal electrode portion forms same surface shape).
As to claim 12: A second interpretation of Xia teaches a semiconductor device comprising a capacitor structure (Xia Fig 25), the capacitor structure positioned on a substrate and comprising:
a first electrode structure comprising a plurality of first horizontal electrode portions (382), a plurality of mold insulating layers (370), and a first conductive pillar (381), the plurality of first horizontal electrode portions spaced apart from each other in a first direction perpendicular to an upper surface of the substrate (382 spaced apart along vertical direction), the plurality of mold insulating layers alternately arranged with the plurality of first horizontal electrode portions and respectively comprising a plurality of openings (370 in spaces between 382), the plurality of mold insulating layers overlapping each other in the first direction (portions of 370 overlapping), and the first conductive pillar connected to each first horizontal electrode portion of the plurality of first horizontal electrode portions and extending in the first direction (381 connected to 382 and extending vertically);
a second electrode structure comprising a plurality of second horizontal electrode portions and a second conductive pillar (360 comprising 361 and 340), the second conductive pillar extending through the plurality of first horizontal electrode portions in the first direction (340 extend between 382 in vertical direction), and the plurality of second horizontal electrode portions spaced apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the plurality of first horizontal electrode portions (361 alternate vertically with 382);
This interpretation of Xia fails to explicitly teach a capacitor dielectric layer or its disposition. Tang, as applied to claim 1 and for the same reasons listed above, teach the remaining limitations regarding a capacitor dielectric layer.
As to claim 13: Xia+Tang teaches the semiconductor device of claim 12. Xia further teaches wherein the plurality of second horizontal electrode portions are alternately arranged with the plurality of first horizontal electrode portions (382 alternate with 361 in vertical direction).
As to claim 14: Xia+Tang teaches the semiconductor device of claim 12. Xia further teaches wherein the second conductive pillar has a circular planar shape (Fig 27 340 circular), and
wherein each of the plurality of openings has an annular planar shape surrounding the second conductive pillar (e.g., 331 annular around 340).
As to claim 15: Xia+Tang teaches the semiconductor device of claim 14. Xia further teaches wherein a side surface of each second horizontal electrode portion of the plurality of second horizontal electrode portions forms a concentric circle with the side wall of the second conductive pillar (Fig 27 sides of 382 form circle with sides of 340).
As to claim 16: Xia+Tang teaches the semiconductor device of claim 12. Xia further teaches wherein the first conductive pillar extends in a first horizontal direction (Fig 25 381 extends into the page, also as seen in top view of Fig 26), and
wherein the second conductive pillar extends in the first horizontal direction and is spaced apart from the first conductive pillar in a second horizontal direction (340 forms same shape as 381 and spaced in left-right direction in Fig 25).
As to claim 17: Xia+Tang teaches the semiconductor device of claim 16. Xia further teaches wherein each second horizontal electrode portion of the plurality of second horizontal electrode portions comprises a first sub-electrode portion on a first side surface of the second conductive pillar (portion of 361 connected to 340) and a second sub-electrode portion on a second side surface of the second conductive pillar, the second side surface opposite to the first side surface (portion of 361 away from 340), and
wherein in the second horizontal direction, a width of the first sub-electrode portion is same as a width of the second sub-electrode portion (split two portions of 361 equally).
Claim(s) 9, 10, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xia and Tang as applied to claims 1 and 12 above, and further in view of US 20230014263 (Huang).
As to claim 9: Xia+Tang teaches the semiconductor device of claim 6, but fails to explicitly teach compositions of the mold insulating layers or the horizontal electrode portions.
Huang discloses a device similar to that of Xia and Tang, wherein isolation structures between capacitors may be silicon nitride (¶0061), and also that electrode portions may comprise polysilicon (¶0096).
It would have been obvious to use the specific materials disclosed by Huang for the device disclosed by Xia and Tang as those having ordinary skill in the art knew these materials were appropriate for the claimed device elements.
As to claim 10: Xia+Tang teaches the semiconductor device of claim 1, but fails to explicitly teach a conductive electrode layer on the capacitor or the composition thereof.
Huang discloses a conductive electrode layer being between a capacitor dielectric layer and mold insulating layers (Fig 5D, conductive layer 223 between capacitor dielectric layer 223 and molding material 18c), and where the conductive electrode layer may comprise tantalum (¶0092). It would have been obvious, for the same reasons as those presented in the claim 9 rejection above, to combine Huang with Xia+Tang.
As to claim 18: Xia+Tang teaches the semiconductor device of claim 12, but fails to explicitly teach a conductive electrode layer on the capacitor or the composition thereof.
Huang discloses a conductive electrode layer being between a capacitor dielectric layer and mold insulating layers (Fig 5D, conductive layer 223 between capacitor dielectric layer 223 and molding material 18c), and where the conductive electrode layer may comprise tantalum (¶0092). It would have been obvious, for the same reasons as those presented in the claim 9 rejection above, to combine Huang with Xia+Tang.
Conclusion
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/Corbyn D Mellinger/Examiner, Art Unit 2899
/EVAN G CLINTON/Primary Examiner, Art Unit 2899
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