DETAILED ACTION
This action is in response to the application filed 08/20/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1-5 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, it is unclear if “the sampling sub-circuit” (line 4) refers to “each of the sampling sub-circuits” (lines 3 & 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN Doc ID CN 103698579 B (Hereinafter Wang) in view of CN Doc ID. CN 219458660 U (Hereinafter Chen).
Regarding claim 1, Wang discloses a direct current voltage sampling circuit [e.g. Fig. 1] used for a medium-voltage power module, the medium-voltage power module comprising two cascaded H-bridge circuits, wherein the current voltage sampling circuit comprises
and the sampling sub-circuit comprises: a voltage dividing circuit [e.g. Fig. 1, element 1] connected in parallel to an output end of the H-bridge circuit to provide a divided voltage of a direct current voltage input by the H-bridge; an isolation module [e.g. Fig. 1, element 2] connected to the voltage dividing circuit [e.g. Fig. 1, connection between elements 1 & 2] to provide an output isolated from the divided voltage; a direct current isolated power supply [e.g. Fig. 1, element 4], which supplies power to the isolation module independently of the H-bridge circuit [e.g. Fig. 1, element 4 is independent of the input to the sampling device]; and an amplifier conditioning module [e.g. Fig. 1, element 3] connected to the isolation module [e.g. Fig. 1, connection between elements 2 & 3] to convert an isolated voltage signal into a sampled voltage output,
Wang fails to disclose two sampling sub-circuits, wherein parasitic capacitances of the isolation module and the direct current isolated power supply are both less than 2 pF, and the sampled voltage outputs of the two sampling sub-circuits are provided to a same local controller
Chen teaches two sampling sub-circuits [e.g. Fig. 4, element 230], and the sampled voltage outputs of the two sampling sub-circuits are provided to a same local controller [e.g. Fig. 4, element 240].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Wang to further include two sampling sub-circuits, and the sampled voltage outputs of the two sampling sub-circuits are provided to a same local controller as taught by Chen to ensure the reliability of the sampled voltage value and reduce output loss of the power module.
Wang disclose the claimed invention except for parasitic capacitances being less than 2pF. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the parasitic capacitances be less than 2pF, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F2d 272, 205 USPQ 215 (CCPA 1980).
Therefore, it would have been obvious to one having ordinary skill in the at the time the invention was filed to modify the circuit of Wang to include the features of having the parasitic capacitances be less than 2pF, because it provides for a reduction in component variance, which can increase operational efficiencies.
Regarding claim 2, Wang fails to disclose the direct current voltage sampling circuit of Claim 1, wherein the parasitic capacitances of the isolation module and the direct current isolated power supply are both less than 1.7 pF.
Wang disclose the claimed invention except for parasitic capacitances being less than 1.7 pF. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the parasitic capacitances be less than 2pF, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F2d 272, 205 USPQ 215 (CCPA 1980).
Therefore, it would have been obvious to one having ordinary skill in the at the time the invention was filed to modify the circuit of Wang to include the features of having the parasitic capacitances be less than 1.7 pF, because it provides for a reduction in component variance, which can increase operational efficiencies.
Regarding claim 3, Wang discloses the direct current voltage sampling circuit of Claim 1, wherein the isolation module is a magnetic coupling isolation amplifier, a capacitive coupling isolation amplifier, or an optical coupling isolation amplifier [e.g. Fig. 1, element 2 optocoupler isolation amplifier].
Regarding claim 4, Wang discloses the direct current voltage sampling circuit of Claim 1, wherein the voltage dividing circuit [e.g. Fig. 1, element 1] comprises a first voltage dividing resistor [e.g. Fig. 2, element R4] and a second voltage dividing resistor [e.g. Fig. 2, element R2] connected in series [e.g. Fig. 2, series connection between R2 & R4]; wherein the isolation module is connected in parallel to two ends of the first voltage dividing resistor [e.g. Fig. 2, element;
Wang disclose the claimed invention except for a ratio of resistance of the first voltage dividing resistor to resistance of the second voltage dividing resistor ranging from 0.02 to 0.1. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a ratio of resistance of the first voltage dividing resistor to resistance of the second voltage dividing resistor range from 0.02 to 0.1, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Therefore, it would have been obvious to one having ordinary skill in the at the time the invention was filed to modify the circuit of Wang to include the features of having a ratio of resistance of the first voltage dividing resistor to resistance of the second voltage dividing resistor range from 0.02 to 0.1, because it provides for a reduction in component variance, which can increase operational efficiencies.
Regarding claim 5, the direct current voltage sampling circuit of Claim 1, wherein the voltage dividing circuit comprises a first voltage dividing resistor, a second voltage dividing resistor, and a third voltage dividing resistor sequentially connected in series; and the isolation module is connected in parallel to two ends of the first voltage dividing resistor or the third voltage dividing resistor; and
Wang fails to disclose wherein a ratio of resistance of the first voltage dividing resistor to resistance of the second voltage dividing resistor ranges from 0.02 to 0.1; and a ratio of resistance of the third voltage dividing resistor to resistance of the second voltage dividing resistor ranges from 0.02 to 0.1.
Wang disclose the claimed invention except for a ratio of resistance of the first voltage dividing resistor to resistance of the second voltage dividing resistor ranging from 0.02 to 0.1 and a ratio of resistance of the third voltage dividing resistor to resistance of the second voltage dividing resistor ranges from 0.02 to 0.1. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a ratio of resistance of the first voltage dividing resistor to resistance of the second voltage dividing resistor range from 0.02 to 0.1, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Therefore, it would have been obvious to one having ordinary skill in the at the time the invention was filed to modify the circuit of Wang to include the features of having a ratio of resistance of the first voltage dividing resistor to resistance of the second voltage dividing resistor range from 0.02 to 0.1 and a ratio of resistance of the third voltage dividing resistor to resistance of the second voltage dividing resistor ranges from 0.02 to 0.1, because it provides for a reduction in component variance, which can increase operational efficiencies.
Regarding claim 6, Wang discloses the direct current voltage sampling circuit of Claim 1, wherein the amplifier conditioning module converts the isolated voltage signal into the sampled voltage output in a form of an analog signal [e.g. Fig. 1, element 3 AD8656 ARMZ amplifier; AD8656 ARMZ amplifier is an analog device].
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN Doc ID CN 103698579 B (Hereinafter Wang) in view of CN Doc ID. CN 219458660 U (Hereinafter Chen) and CN Doc ID. CN 115208179 A (Hereinafter Fang).
Regarding claim 7, Wang fails to disclose the direct current voltage sampling circuit of Claim 1, wherein the amplifier conditioning module converts the isolated voltage signal into the sampled voltage output in a form of a digital signal.
Fang discloses the direct current voltage sampling circuit of Claim 1, wherein the amplifier conditioning module converts the isolated voltage signal into the sampled voltage output in a form of a digital signal [e.g. paragraph 105, “The operational amplifier in the sampling and conditioning circuit uses TI's LMV612, and the digital control chip uses TI's TMS320F280049. The sampling and conditioning circuit converts the collected output voltage signal into a signal acceptable to the CPU and sends it to the program processing unit in the CPU for processing”]. Therefore, it would have been obvious to one having ordinary skill in the at the time the invention was filed to modify the circuit of Wang to include the features of Fang because it provides for a specific control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190237815 A1 - DAN; Zhimin et al. - INSULATION DETECTION CIRCUIT AND METHOD, AND BATTERY MANAGEMENT SYSTEM.
US 20210231742 A1 - LI; Meng et al. - INSULATION DETECTION CIRCUIT, DETECTION METHOD AND BATTERY MANAGEMENT SYSTEM
CN 213210273 U - XU, FEI - Voltage current sampling circuit structure of direct current power supply
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/JARED RAYMOND HAUSMAN/Examiner, Art Unit 2838
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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