DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 7/08/2026 have been fully considered but they are not persuasive. The applicant argues and merely states the noise capacitors are not in parallel with electrode surfaces yet fails to explain how they are not in parallel with the surfaces. Moreover, the applicant does not explain how the applicant’s noise capacitors are in parallel with the electrode surfaces. Still further, the specification is silent on how the applicant’s capacitors are connected in parallel with the electrode; as a result therefore, the examiner still considers Nishizawa’s to be in parallel with the surfaces as claimed.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-9, 14, 18 and 19 is is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Nishizawa et al. (US 20170063218).
Claims 1 and 14; Nishizawa et al. disclose a power conversion device (figure 2), comprising: a smoothing capacitor (514) connected to an upper and lower arm circuit (140) that generates and outputs AC power (188), and configured to smooth voltage pulsations; a noise absorbing capacitor (515) connected to the upper and lower arm circuit (140), and configured to absorb noise; a P-side bus bar (564p) connected to a P-side electrode surface (563p) of the smoothing capacitor (514), which is on a high potential side, and the noise absorbing capacitor (560p); a N-side bus bar (564n) connected to a N-side electrode surface (563n) of the smoothing capacitor (514), which is on a low-potential side electrode surface, and the noise absorbing capacitor (515); and a ground bus bar (569) having one end connected to the noise absorbing capacitor (515) and the other end connected to a member having a ground potential (gnd), wherein the noise absorbing capacitor comprises a P-side noise absorbing capacitor (upper 515) connected to the P-side bus bar and an N-side noise absorbing capacitor (lower 515) connected to the N-side bus bar, and the P-side noise absorbing capacitor and the N-side noise absorbing capacitor (514) are arranged in parallel with the P-side electrode surface and the N-side electrode surface (see illustrations above); the P-side electrode surface and the N-side electrode surface are orthogonal to a z direction, and the P-side noise absorbing capacitor and the N-side noise absorbing capacitor are arranged in parallel with the P-side electrode surface and the N-side electrode surface in a state in which the P-side noise absorbing capacitor and the N-side noise absorbing capacitor do not overlap the P-side electrode surface and the N-side electrode surface in the z direction (that is, the noise capacitors do not extend beyond the smoothing capacitor surface on either of the p or n side).
Claim 2; Nishizawa et al. disclose an electrical insulating plate (565) laminated and arranged between the P-side bus bar (565p) and the N-side bus bar (564n), wherein the P-side bus bar has a P-side flat plate portion (fig. 6) having a flat plate shape and facing the electrically insulating plate (565), the N-side bus bar has a N- side flat plate portion (fig. 5) having a flat plate shape and facing the electrically insulating plate (565), and the noise absorbing capacitor (515) is arranged at a position different from the electrically insulating plate (565) when viewed from a direction perpendicular to the P-side electrode surface (564p) and the N-side electrode surface (564n).
Claim 3; Nishizawa et al. disclose an electrical insulating plate (565) laminated and arranged between the P-side bus bar (564p) and the N-side bus bar (564n), wherein the noise absorbing capacitor (515) is arranged with the electrical insulating plate in a direction perpendicular to the P-side electrode surface (564p) and the N- side electrode surface (564n).
Claims 9 and 18; figure 6; p and n at least partially overlap in the z directions; see illustrations above.
Claim 19; Nishizawa et al. disclose a power conversion device (fig. 2), comprising: a smoothing capacitor (514) connected to an upper and lower arm circuit (bridge 140) that generates and outputs AC power (MG1), and configured to smooth voltage pulsations; a noise absorbing capacitor (515) connected to the upper and lower arm circuit, and configured to absorb noise; a P-side bus bar (564p) connected to a P-side electrode surface of the smoothing capacitor (514), which is on a high potential side, and the noise absorbing capacitor; a N-side bus bar (564n) connected to a N-side electrode surface of the smoothing capacitor (514), which is on a low-potential side electrode surface, and the noise absorbing capacitor (515); and a ground bus bar (569) having one end connected to the noise absorbing capacitor and the other end connected to a member having a ground potential, wherein the noise absorbing capacitor (515) comprises a P-side noise absorbing capacitor (515, p side) connected to the P-side bus bar and an N-side noise absorbing capacitor (515 n side) connected to the N-side bus bar, the P-side electrode surface and the N-side electrode surface are orthogonal to a z direction (see illustrations above), and a positional region of the P-side noise absorbing capacitor in the z-direction and a positional region of the N-side noise absorbing capacitor in the z-direction at least partially overlap each other (the examiner considers the noise capacitors to overlap in the same plane in the z direction. That is, they are aligned along the same plane and not offset to a point of no overlap or not aligned. See illustrations above).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 10-13 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishizawa et al. in view of Otsuka et al. (US 20070002594 - IDS).
Claims 10-13; Nishizawa et al. disclose the claimed subject matter in regards to claim 1 supra except for the smoothing capacitor comprises a plurality of smoothing capacitors.
Otsuka et al. teach a power converter with noise capacitors and a plurality of smoothing capacitors arranged in a direction and the noise capacitors are arranged in the direction. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Nishizawa et al. to include noise capacitors and a plurality of smoothing capacitors arranged in a direction and the noise capacitors are arranged in the direction in order to provide a compact configuration to save space and reduce overall size.
Claims 16-17; Nishizawa et al. disclose the claimed subject matter in regards to claim 1 supra except for a Z direction is perpendicular to the P-side electrode surface and the N-side electrode surface, and the smoothing capacitor and the semiconductor module are arranged in a X direction that is perpendicular to the Z direction.
Otsuka et al. teach a Z direction is perpendicular to the P-side electrode surface and the N-side electrode surface, and the smoothing capacitor and the semiconductor module are arranged in a X direction that is perpendicular to the Z direction figure 24 and 26, for example.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Nishizawa et al. to include a Z direction is perpendicular to the P-side electrode surface and the N-side electrode surface, and the smoothing capacitor and the semiconductor module are arranged in a X direction that is perpendicular to the Z direction in order to provide a compact form converter that provides a smaller package with space savings.
Otsuka et al. also teach a y direction is perpendicular to the Z direction and the X direction, and the P-side noise absorbing capacitor and the N-side noise absorbing capacitor are arranged in the y direction (figure 17B).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify Nishizawa et al. to include a y direction is perpendicular to the Z direction and the X direction, and the P-side noise absorbing capacitor and the N-side noise absorbing capacitor are arranged in the y direction in order to provide a compact form converter that provides a smaller package with space savings.
Allowable Subject Matter
Claims 4-6 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY L LAXTON/Primary Examiner, Art Unit 2838 9/17/2026
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