DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority based on an application JP 2022-029466 filed in Japan Patent Office (JPO) on 2/28/2022 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 8/20/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 6 is objected to because of the following informalities:
In claim 6, lines 3-4, “the second member is includes” should read --the second member includes-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO et al. (US 2020/0381324; hereinafter ‘YAMAMOTO’) in view of Kim et al. (US 2008/0203444; hereinafter ‘Kim’) and Schweitzer (“Effective Heat Spreading Angle”, Electronics Cooling, Vol. 21, No. 3, 2015).
Regarding claim 1, YAMAMOTO teaches a semiconductor device (first semiconductor element 10 with third resin layer 16 disposed thereon, FIG. 10, [0024-0025, 0095-0097]; hereinafter ‘SD’) comprising:
a first insulating layer (12, [0024]);
a device layer (11, [0024]) that comprises:
a transistor (11 includes a transistor, [0024]) on a first surface which is one surface of the first insulating layer (11 is disposed on a lower surface of 12, FIG. 10);
a plurality of bumps (15, [0025]) on the device layer (15 on the 11); and
an insulating member (16, [0096]) bonded to a second surface of the first insulating layer opposite to the first surface (16 bonded to an upper surface 12b opposite to the lower surface, FIGS. 2 and 10, [0031, 0102-0103]).
YAMAMOTO does not teach the semiconductor device comprising: a transistor including a plurality of source regions and a plurality of drain regions, a source contact electrode connected to a source contact region on surfaces of the plurality of source regions, a drain contact electrode connected to a drain contact region on surfaces of the plurality of drain regions, a plurality of wires, and a plurality of vias; wherein the apex of the criterion conical surface is a point on the second surface directly below a geometric center of a minimum encompassing rectangle having a smallest area encompassing all of the plurality of source contact regions and the plurality of drain contact regions.
Kim teaches a semiconductor device [0005] comprising:
a transistor (400, FIGS. 2 and 3A-3D, [0047]), including
a plurality of source regions (460, FIGS. 2 and 3D, [0054],) and
a plurality of drain regions (470, FIGS. 2 and 3D, [0054])
a source contact electrode (491, FIG. 2, [0060]) connected to a source contact region (surface regions of respective 460 contacted by conductive plugs 465, FIG. 3D, [0060]; hereinafter ’460SCR’) on surfaces of the plurality of source regions (460SCR on surfaces of 460),
a drain contact electrode (497, FIG. 2, [0061]) connected to a drain contact region (surface regions of respective 470 contacted by conductive plugs 475, FIG. 3D, [0061]; hereinafter ‘470DCR’) on surfaces of the plurality of drain regions (470DCR on surfaces of 470),
a plurality of wires (490 and 495, FIG. 2, [0063]), and
a plurality of vias (465 and 475, FIGS. 2 and 3D, [0060-0061]).
Kim does not explicitly teach that the apex of the criterion conical surface is a point on the second surface directly below a geometric center of a minimum encompassing rectangle having a smallest area encompassing all of the plurality of source contact regions and the plurality of drain contact regions.
Kim, however, teaches the plurality of source contact regions 460SCR and the plurality of drain contact regions 470DCR arranged in plan view, as shown in FIG. 2. The outmost boundaries of theses source and drain contact regions necessarily define a minimum encompassing rectangle having a geometric center.
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO to obtain and achieve the semiconductor device comprising: a transistor including a plurality of source regions and a plurality of drain regions, a source contact electrode connected to a source contact region on surfaces of the plurality of source regions, a drain contact electrode connected to a drain contact region on surfaces of the plurality of drain regions, a plurality of wires, and a plurality of vias as claimed, because this structure provides electrical interconnection of the transistor regions while reducing device area and parasitic capacitance and improving high-frequency performance [0006-0008, 0068].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Kim in combination with YAMAMOTO due to the above reason.
In the resulting combination of Yamamoto and Kim, the apex of the criterion conical surface is a point on the second surface directly below a geometric center of a minimum encompassing rectangle having a smallest area encompassing all of the plurality of source contact regions and the plurality of drain contact regions (a point on the upper surface 12b of Yamamoto’s insulating layer 12 directly below the geometric center of the minimum encompassing rectangle defined by the outermost source contact regions 460SCR and drain contact regions 470DCR shown in Kim’s FIG. 2).
YAMAMOTO in view of Kim does not teach the semiconductor device wherein a conical surface whose apex is located on the second surface, whose central axis is a straight line perpendicular to the second surface, and whose generatrix is a half-line extending toward the insulating member at an angle of 45° with respect to the central axis is defined as a criterion conical surface, and when a direction perpendicular to the second surface is defined as a thickness direction, an entire range in the thickness direction of a side surface of the insulating member is located outside the criterion conical surface in at least a partial range in a peripheral direction.
Schweitzer teaches a semiconductor device (Figure 1) wherein
a conical surface whose apex is located on the second surface, whose central axis is a straight line perpendicular to the second surface, and whose generatrix is a half-line extending toward the insulating member at an angle of 45° with respect to the central axis is defined as a criterion conical surface (a 45° criterion conical surface beginning at the center of the active area and extending through the underlying layered structure in the thickness direction along the x-axis perpendicular to the semiconductor layer surfaces, as geometrically established based on the 45° heat spreading boundaries shown in the dashed lines in Figures 3), and
when a direction perpendicular to the second surface is defined as a thickness direction, an entire range in the thickness direction of a side surface of the insulating member is located outside the criterion conical surface in at least a partial range in a peripheral direction (the corresponding dimensional relationship illustrated by the 8.0 mm wide and 1.27 mm thick underlying structure, wherein each side surface is located 4.0 mm from the center of the 1.0 mm wide active area, while each 45° heat spreading boundary extends no farther than 1.77 mm from the center at the bottom surface, such that the side surface remains outside the 45° heat spreading boundary over the entire thickness of the underlying structure, Figures 1 and 3).
Schweitzer does not explicitly teach that the apex is directly below the geometric center of the minimum encompassing rectangle of the source and drain contact regions.
Schweitzer, however, teaches a 45° heat spreading boundary extending from a semiconductor active area through an underlying layered structure in a thickness direction perpendicular to the semiconductor surfaces (Figure 3).
Because the 45° heat spreading boundary illustrated by Schweitzer begins at the outer edges of the active area, it encompasses a greater lateral extent than a 45° criterion conical surface beginning at the geometric center of the same area. Therefore, a side surface located outside Schweitzer’s heat spreading boundary would necessarily also be located outside the claimed criterion conical surface extending from the above identified apex.
As taught by Schweitzer, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO in view of Kim to obtain and achieve the semiconductor device wherein a conical surface whose apex is located on the second surface, whose central axis is a straight line perpendicular to the second surface, and whose generatrix is a half-line extending toward the insulating member at an angle of 45° with respect to the central axis is defined as a criterion conical surface, and when a direction perpendicular to the second surface is defined as a thickness direction, an entire range in the thickness direction of a side surface of the insulating member is located outside the criterion conical surface in at least a partial range in a peripheral direction as claimed, because providing sufficient lateral extent for heat spreading increases the effective heat transfer area, reduces thermal resistance, and improves dissipation of heat generated by the transistor.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Schweitzer in combination with YAMAMOTO in view of Kim due to the above reason.
Regarding claim 2, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 1, YAMAMOTO in view of Kim does not teach the semiconductor device wherein the entire range in the thickness direction and an entire range in the peripheral direction of the side surface of the insulating member are outside the criterion conical surface whose apex is a point on the second surface directly below the geometric center of the minimum encompassing rectangle.
Schweitzer teaches the semiconductor device, wherein the entire range in the thickness direction and an entire range in the peripheral direction of the side surface of the insulating member are outside the criterion conical surface whose apex is a point on the second surface directly below the geometric center of the minimum encompassing rectangle (the corresponding dimensional relationship illustrated by the 8.0 mm x 8.0 mm and 1.27 mm thick underlying structure surrounding the centrally located active area, whereby all four side surfaces remain outside the 45° heat spreading boundary throughout the thickness and around the entire periphery, Figures 1 and 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of Schweitzer to obtain and achieve the semiconductor device wherein the entire range in the thickness direction and an entire range in the peripheral direction of the side surface of the insulating member are outside the criterion conical surface whose apex is a point on the second surface directly below the geometric center of the minimum encompassing rectangle as claimed, because extending the insulating member beyond the 45° heat spreading boundary around the entire periphery increases the effective heat-transfer area I all lateral directions, thereby reducing thermal resistance and improving dissipation of heat generated by the transistor (Figures 1 and 3).
Regarding claim 3, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 1, YAMAMOTO in view of Kim does not teach the semiconductor device wherein the entire range in the thickness direction of the side surface of the insulating member is outside any of the criterion conical surfaces whose apex is a point in a region, on the second surface, that overlaps the minimum encompassing rectangle in plan view.
Schweitzer teaches the semiconductor device, wherein the entire range in the thickness direction of the side surface of the insulating member is outside any of the criterion conical surfaces whose apex is a point in a region, on the second surface, that overlaps the minimum encompassing rectangle in plan view (the corresponding dimensional relationship illustrated by the 45° heat spreading boundary extending from the outer edges of the 1.0 mm x 1.0 mm active area, which defines an outer envelope encompassing the 45° conical surfaces extending from points throughout the active area, wherein the side surfaces of the 8.0 mm x 8.0 mm and 1.27 mm thick underlying structure remain outside that envelope throughout the entire thickness, Figures 1 and 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of Schweitzer to obtain and achieve the semiconductor device wherein the entire range in the thickness direction of the side surface of the insulating member is outside any of the criterion conical surfaces whose apex is a point in a region, on the second surface, that overlaps the minimum encompassing rectangle in plan view as claimed, because extending the insulating member beyond the 45° heat spreading envelope of the entire active area increases the effective heat transfer area and improves dissipation of heat generated throughout the active area (Figures 1 and 3).
Regarding claim 10, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 1, wherein the first insulating layer includes silicon oxide (YAMAMOTO: the insulating layer 12 composed of silicon oxide film, [0024]).
Regarding claim 14, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 1, YAMAMOTO further teaches a semiconductor module (200, FIG. 10, [0095]) comprising: the semiconductor device according to claim 1;
a module substrate (1, [0095]) including a land (a surface region of second wiring layer 3b contacted by bump 15, FIG. 10, [0023-0025]) on which the semiconductor device is mounted (SD being mounted on the surface region of 3b through 15, FIG. 10, [0024]) and to which each of the plurality of bumps of the semiconductor device is connected (each 15 of SD being connected to the surface region of 3b, FIG. 10, [0025]); and
a sealing resin (7, FIG. 10, [0095]) covering the semiconductor device (7 covering SD, FIG. 10, [0030]).
Claims 4-7 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (US 2020/0381324) in view of Kim (US 2008/0203444) and Schweitzer (“Effective Heat Spreading Angle”, Electronics Cooling, Vol. 21, No. 3, 2015) as applied to claim 1 above, and further in view of KONISHI et al. (US 2021/0335658; hereinafter ‘KONISHI’).
Regarding claim 4, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 1, but does not teach the semiconductor device wherein the insulating member comprises: a first member bonded to the first insulating layer; and a second member at a position farther from the first member as seen from the first insulating layer and having a thermal conductivity higher than a thermal conductivity of the first member.
KONISHI teaches a semiconductor device (FIG. 1, [0027]) wherein the insulating member (17 and 18, FIG. 1 (h), [0035, 0039]) comprises:
a first member (adhesive for transfer 18 having a thermal conductivity of about 1 W/m·k, FIG. 1(h), [0035]) bonded to the first insulating layer (18 bonded to buried oxide film 12, FIG. 1(h), [0039]); and
a second member (high thermal conductivity insulating transfer substrate 17 having a thermal conductivity of 40 W/m·k or more, FIG. 1(h), [0035, 0039]) at a position farther from the first member as seen from the first insulating layer (17 positioned farther from buried oxide film 12 than 18) and having a thermal conductivity higher than a thermal conductivity of the first member (17 having higher thermal conductivity than 18).
As taught by KONISHI, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO in view of Kim and Schweitzer to obtain and achieve the semiconductor device wherein a second member at a position farther from the first member as seen from the first insulating layer and having a thermal conductivity higher than a thermal conductivity of the first member as claimed, because positioning a high thermal conductivity insulating substrate outside a relatively low thermal conductivity adhesive layer provides an electrically insulating and efficient heat-dissipation path for the semiconductor device [0035, 0076].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by KONISHI in combination with YAMAMOTO in view of Kim and Schweitzer due to the above reason.
Regarding claim 5, YAMAMOTO in view of Kim, Schweitzer, and KONISHI teaches the semiconductor device according to claim 4, YAMAMOTO in view of Kim and Schweitzer does not teach the semiconductor device wherein a thickness of the first member is smaller than a thickness of the second member.
KONISHI teaches the semiconductor device wherein a thickness of the first member is smaller than a thickness of the second member (18 has a thickness of 1 µm, whereas 17 has a thickness of 725 µm, FIG. 1(h), [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of KONISHI to obtain and achieve the semiconductor device wherein a thickness of the first member is smaller than a thickness of the second member as claimed, because forming the relatively low-thermal-conductivity layer thinner than the insulating substrate minimizes the layer’s thermal resistance while preserving the structural support and heat-dissipation capability provided by the insulating substrate [0035, 0045].
Regarding claim 6, YAMAMOTO in view of Kim, Schweitzer, and KONISHI teaches the semiconductor device according to claim 4, YAMAMOTO in view of Kim and Schweitzer does not teach the semiconductor device wherein the first member includes an organic insulating material and the second member is includes an inorganic insulating material.
KONISHI teaches the semiconductor device wherein the first member includes an organic insulating material (18 comprising a silicon resin, epoxy-modified rubber, epoxy-modified silicon, [0035]), and the second member is includes an inorganic insulating material (17 comprising a Si3N4 sintered body having an electrical resistivity of 5 E+15 Ω·cm, [0035, 0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of KONISHI to obtain and achieve the semiconductor device wherein the first member includes an organic insulating material and the second member is includes an inorganic insulating material as claimed, because using a compliant organic resin adhesive between the device structure and the inorganic insulating substrate enables low stress, heat resistant bonding while maintaining the heat-dissipation and electrical isolation functions of the substrate [0021, 0025-0026].
Regarding claim 7, YAMAMOTO in view of Kim, Schweitzer, and KONISHI teaches the semiconductor device according to claim 4, YAMAMOTO in view of Kim and Schweitzer does not teach the semiconductor device wherein the first member includes a polymer compound.
KONISHI teaches the semiconductor device wherein the first member includes a polymer compound (18 comprising a silicon resin, epoxy-modified rubber, or epoxy-modified silicon, [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of KONISHI to obtain and achieve the semiconductor device the first member includes a polymer compound as claimed, because the polymer compounds provide heat resistant and low stress bonding between the semiconductor structure and the insulating transfer substrate [0021, 0035].
Regarding claim 18, YAMAMOTO in view of Kim, Schweitzer, and KONISHI teaches the semiconductor device according to claim 5, YAMAMOTO in view of Kim and Schweitzer does not teach the semiconductor device wherein the first member includes an organic insulating material and the second member is includes an inorganic insulating material.
KONISHI teaches the semiconductor device wherein the first member includes an organic insulating material (18 comprising a silicon resin, epoxy-modified rubber, epoxy-modified silicon, [0035]), and the second member is includes an inorganic insulating material (17 comprising a Si3N4 sintered body having an electrical resistivity of 5 E+15 Ω·cm, [0035, 0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of KONISHI to obtain and achieve the semiconductor device wherein the first member includes an organic insulating material and the second member is includes an inorganic insulating material as claimed, because using a compliant organic resin adhesive between the device structure and the inorganic insulating substrate enables low stress, heat resistant bonding while maintaining the heat-dissipation and electrical isolation functions of the substrate [0021, 0025-0026].
Regarding claim 19, YAMAMOTO in view of Kim, Schweitzer, and KONISHI teaches the semiconductor device according to claim 5, YAMAMOTO in view of Kim and Schweitzer does not teach the semiconductor device wherein the first member includes a polymer compound.
KONISHI teaches the semiconductor device wherein the first member includes a polymer compound (18 comprising a silicon resin, epoxy-modified rubber, or epoxy-modified silicon, [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of KONISHI to obtain and achieve the semiconductor device the first member includes a polymer compound as claimed, because the polymer compounds provide heat resistant and low stress bonding between the semiconductor structure and the insulating transfer substrate [0021, 0035].
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (US 2020/0381324) in view of Kim (US 2008/0203444) and Schweitzer (“Effective Heat Spreading Angle”, Electronics Cooling, Vol. 21, No. 3, 2015) as applied to claim 1 above, and further in view of Choi (US 2002/0163074).
Regarding claim 8, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 1, but does not teach the semiconductor device further comprising: a conductive plate member bonded to a surface of the insulating member on a side opposite to a surface bonded to the first insulating layer.
Choi teaches a semiconductor device (200, FIG. 12, [0033, 0039]) further comprising: a conductive plate member (conductive layer 222, [0040]) bonded to a surface of the insulating member on a side opposite to a surface bonded to the first insulating layer (222 bonded to the backside surface of insulating dielectric layer 220, opposite the front side surface facing semiconductor die 242, FIG. 12, [0035, 0039]).
As taught by Choi, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO in view of Kim and Schweitzer to obtain and achieve the semiconductor device further comprising: a conductive plate member bonded to a surface of the insulating member on a side opposite to a surface bonded to the first insulating layer as claimed, because the conductive backside layer dissipates heat transmitted through the insulating dielectric layer while the dielectric layer maintain electrical isolation of the semiconductor device [0035, 0041].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Choi in combination with YAMAMOTO in view of Kim and Schweitzer due to the above reason.
Regarding claim 9, YAMAMOTO in view of Kim, Schweitzer, and Choi teaches the semiconductor device according to claim 8, YAMAMOTO in view of Kim and Choi does not teach the semiconductor device wherein the conductive plate member extends in plan view to an outside of the criterion conical surface whose apex is a point on the second surface directly below the geometric center of the minimum encompassing rectangle.
Schweitzer teaches the semiconductor device wherein the conductive plate member extends in plan view to an outside of the criterion conical surface whose apex is a point on the second surface directly below the geometric center of the minimum encompassing rectangle (the 8.0 mm x 8.0 mm Cu leadframe extends laterally in plan view beyond the 45° heat spreading boundary originating from the centrally located active area, Figures 1 and 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of Schweitzer to obtain and achieve the semiconductor device wherein the conductive plate member extends in plan view to an outside of the criterion conical surface whose apex is a point on the second surface directly below the geometric center of the minimum encompassing rectangle as claimed, because extending the copper leadframe beyond the heat spreading boundary provides an enlarged area over which heat can spread and be transferred away from the semiconductor device, thereby reducing thermal resistance (Figures 1 and 3).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (US 2020/0381324) in view of Kim (US 2008/0203444) and Schweitzer (“Effective Heat Spreading Angle”, Electronics Cooling, Vol. 21, No. 3, 2015) as applied to claim 1 above, and further in view of KOROKU et al. (US 2009/0243097; hereinafter ‘KOROKU’).
Regarding claim 11, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 1, but does not teach the semiconductor device further comprising: an organic protective film including an organic insulating material and being on the device layer, wherein the plurality of bumps are respectively connected to the wires of the device layer through a plurality of openings in the organic protective film, and the organic protective film is not in at least a part of a peripheral portion of an upper surface of the device layer.
KOROKU teaches a semiconductor device (FIG. 1, [0045]) further comprising:
an organic protective film (9, FIG. 1, [0051]) including an organic insulating material (9 made of an organic material such as a polyimide-based resin, [0051]) and being on the device layer (9 provided on the passivation film 7 over a device layer (hereinafter ‘DLKOROKU’) comprising integrated circuit elements including a transistor and low dielectric constant film/wiring line stack structure 3, FIG. 1, [0045-0046, 0051]) wherein
the plurality of bumps (external connection bump electrodes 14, FIG. 1, [0053]) are respectively connected to the wires of the device layer through a plurality of openings in the organic protective film (14 being respectively connected to uppermost wiring lines 5 of DLKOROKU through upper wiring lines 11 and openings 8 and 10, FIG. 1, [0050-0053])
the organic protective film is not in at least a part of a peripheral portion (a peripheral portion of DLKOROKU in which connection pad portion 5a and corresponding opening 10 are located, FIG. 1, [0051]; hereinafter ‘PP’) of an upper surface of the device layer (9 is not in a part of PP of DLKOROKU, FIG. 1, [0054]).
As taught by KOROKU, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO in view of Kim and Schweitzer to obtain and achieve the semiconductor device further comprising: an organic protective film including an organic insulating material and being on the device layer, wherein the plurality of bumps are respectively connected to the wires of the device layer through a plurality of openings in the organic protective film, and the organic protective film is not in at least a part of a peripheral portion of an upper surface of the device layer as claimed, because forming the peripheral opening in advance facilitates laser processing of the underlying structure without requiring the thick organic resin film, which highly absorbs laser energy, to be cut by the laser [0063].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by KOROKU in combination with YAMAMOTO in view of Kim and Schweitzer due to the above reason.
Regarding claim 12, YAMAMOTO in view of Kim, Schweitzer, and KOROKU teaches the semiconductor device according to claim 11, YAMAMOTO in view of Kim and Schweitzer does not teach the semiconductor device wherein the device layer comprises a metal layer in the peripheral portion of the device layer in plan view, and at least a part of the metal layer is on an outside of the organic protective film in plan view.
KOROKU teaches the semiconductor device wherein
the device layer comprises a metal layer (a connection pad portion 5a of uppermost wiring line 5, FIG. 1, [0050]) in the peripheral portion of the device layer in plan view (5a in PP of DLKOROKU in plan view, FIG. 1), and
at least a part of the metal layer is on an outside of the organic protective film in plan view (a part of 5a corresponding to opening 10 being outside upper protective film 9 in plan view, FIG. 1, [0051-0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the above teachings of KOROKU to obtain and achieve the semiconductor device wherein the device layer comprises a metal layer in the peripheral portion of the device layer in plan view, and at least a part of the metal layer is on an outside of the organic protective film in plan view as claimed, because it enables electrical connection between the internal wiring and the external connection bump electrode [0052-0053].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (US 2020/0381324) in view of Kim (US 2008/0203444) and Schweitzer (“Effective Heat Spreading Angle”, Electronics Cooling, Vol. 21, No. 3, 2015) as applied to claim 1 above, and further in view of Hikita et al. (US 2006/0060895; hereinafter ‘Hikita’).
Regarding claim 13, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 1, but does not teach the semiconductor device wherein a thickness of the insulating member is equal to or greater than a thickness from a lower surface of the device layer to an upper surface of a wire of an uppermost layer included in the device layer.
Hikita teaches a semiconductor device (FIG. 5, [0063]) wherein a thickness of the insulating member is equal to or greater than a thickness from a lower surface of the device layer to an upper surface of a wire of an uppermost layer included in the device layer (a 500 µm thick insulator substrate 200 corresponding to the insulating member and having a thickness greater than the 1925 nm thickness from the lower surface of conductive layer 202 to the upper surface of gate electrode 208 corresponding to a wire of an uppermost layer included in the device layer, wherein conductive layer 202, channel layer 203, Schottky layer 204, and gate electrode 208 have thickness of 500 nm, 1000 nm, 25 nm, and 400 nm, respectively, FIG. 5, [0063-0064]).
As taught by Hikita, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO in view of Kim and Schweitzer to obtain and achieve the semiconductor device wherein a thickness of the insulating member is equal to or greater than a thickness from a lower surface of the device layer to an upper surface of a wire of an uppermost layer included in the device layer as claimed, because maintaining a sufficiently thick insulating member preserves the mechanical strength necessary for supporting the semiconductor device [0068].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hikita in combination with YAMAMOTO in view of Kim and Schweitzer due to the above reason.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (US 2020/0381324) in view of Kim (US 2008/0203444) and Schweitzer (“Effective Heat Spreading Angle”, Electronics Cooling, Vol. 21, No. 3, 2015) as applied to claim 14 above, and further in view of Hikita (US 2006/0060895).
Regarding claim 15, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor module according to claim 14, but does not teach that a thickness of the insulating member is equal to or greater than a dimension in a direction perpendicular to the second surface from a wire of an uppermost layer included in the device layer to the land.
Hikita teaches a semiconductor device (FIG. 5, [0063]) wherein a thickness of the insulating member is equal to or greater than a dimension in a direction perpendicular to the second surface from a wire of an uppermost layer included in the device layer to the land (a 500 µm thick insulator substrate 200 corresponding to the insulating member and being thicker than 5 µm vertical dimension form drain electrode 207 corresponding to a wire of an uppermost layer included in the device layer to an external surface of interconnect metal 214 corresponding to a surface contacting the land, FIG. 5, [0062-0063, 0066]).
As taught by Hikita, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO in view of Kim and Schweitzer to obtain and achieve the semiconductor module wherein a thickness of the insulating member is equal to or greater than a dimension in a direction perpendicular to the second surface from a wire of an uppermost layer included in the device layer to the land as claimed, because maintaining a sufficiently thick insulating member preserves the mechanical strength necessary for the semiconductor device while accommodating the vertical interconnection between the uppermost wire and the land [0068].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hikita in combination with YAMAMOTO in view of Kim and Schweitzer due to the above reason.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (US 2020/0381324) in view of Kim (US 2008/0203444) and Hikita (US 2006/0060895).
Regarding claim 16, YAMAMOTO teaches a semiconductor device (first semiconductor element 10 with third resin layer 16 disposed thereon, FIG. 10, [0024-0025, 0095-0097]; hereinafter ‘SD’) comprising:
a first insulating layer (12, [0024]);
a device layer (11, [0024]) including a transistor (11 includes a transistor, [0024]) on a first surface which is one surface of the first insulating layer (11 is disposed on a lower surface of 12, FIG. 10);
a plurality of bumps (15, [0025]) on the device layer (15 on the 11); and
an insulating member (16, [0096]) bonded to a second surface opposite to the first surface of the first insulating layer (16 bonded to an upper surface 12b opposite to the lower surface, FIGS. 2 and 10, [0031, 0102-0103]).
YAMAMOTO does not teach the semiconductor device comprising: the device layer including a plurality of wires, and a plurality of vias; wherein when a direction perpendicular to the second surface is defined as a thickness direction, a thickness of the insulating member is equal to or greater than a thickness from a lower surface of the device layer to an upper surface of a wire of an uppermost layer included in the device layer.
Hikita teaches a semiconductor device (FIG. 5, [0063]) comprising:
a device layer (a device layer including conductive layer 202, channel layer 203, Schottky layer 204, first insulating film 205, source electrode 206, drain electrode 207, and gate electrode 208, FIG. 5, [0063-0064]) including a plurality of wires (the horizontally extending portions of 206, 208, and 207), and a plurality of vias (the vertically extending portions of 206, 208, and 207 disposed respectively in openings 221, 222, and 223, [0064]);
wherein a thickness of the insulating member (insulator substrate 200, FIG. 5, [0063]) is equal to or greater than a thickness from a lower surface of the device layer to an upper surface of a wire of an uppermost layer included in the device layer (a 500 µm thick insulator substrate 200 having a thickness greater than the 1925 nm thickness from the lower surface of conductive layer 202 to the upper surface of 208 corresponding to a wire of an uppermost layer included in the device layer, wherein 202, 203, 204, and 208 have thickness of 500 nm, 1000 nm, 25 nm, and 400 nm, respectively, FIG. 5, [0063-0064]).
As taught by Hikita, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO to obtain and achieve the semiconductor device comprising: the device layer including a plurality of wires, and a plurality of vias; wherein when a direction perpendicular to the second surface is defined as a thickness direction, a thickness of the insulating member is equal to or greater than a thickness from a lower surface of the device layer to an upper surface of a wire of an uppermost layer included in the device layer as claimed, because maintaining a sufficiently thick insulating member preserves the mechanical strength necessary for supporting the semiconductor device [0068].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Hikita in combination with YAMAMOTO due to the above reason.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (US 2020/0381324) in view of Kim (US 2008/0203444) and Schweitzer (“Effective Heat Spreading Angle”, Electronics Cooling, Vol. 21, No. 3, 2015) as applied to claim 2 above, and further in view of KONISHI (US 2021/0335658).
Regarding claim 17, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 2, but does not teach the semiconductor device wherein the insulating member comprises: a first member bonded to the first insulating layer; and a second member at a position farther from the first member as seen from the first insulating layer and having a thermal conductivity higher than a thermal conductivity of the first member.
KONISHI teaches a semiconductor device (FIG. 1, [0027]) wherein the insulating member (17 and 18, FIG. 1 (h), [0035, 0039]) comprises:
a first member (adhesive for transfer 18 having a thermal conductivity of about 1 W/m·k, FIG. 1(h), [0035]) bonded to the first insulating layer (18 bonded to buried oxide film 12, FIG. 1(h), [0039]); and
a second member (high thermal conductivity insulating transfer substrate 17 having a thermal conductivity of 40 W/m·k or more, FIG. 1(h), [0035, 0039]) at a position farther from the first member as seen from the first insulating layer (17 positioned farther from buried oxide film 12 than 18) and having a thermal conductivity higher than a thermal conductivity of the first member (17 having higher thermal conductivity than 18).
As taught by KONISHI, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO in view of Kim and Schweitzer to obtain and achieve the semiconductor device wherein a second member at a position farther from the first member as seen from the first insulating layer and having a thermal conductivity higher than a thermal conductivity of the first member as claimed, because positioning a high thermal conductivity insulating substrate outside a relatively low thermal conductivity adhesive layer provides an electrically insulating and efficient heat-dissipation path for the semiconductor device [0035, 0076].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by KONISHI in combination with YAMAMOTO in view of Kim and Schweitzer due to the above reason.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over YAMAMOTO (US 2020/0381324) in view of Kim (US 2008/0203444) and Schweitzer (“Effective Heat Spreading Angle”, Electronics Cooling, Vol. 21, No. 3, 2015) as applied to claim 2 above, and further in view of Choi (US 2002/0163074).
Regarding claim 20, YAMAMOTO in view of Kim and Schweitzer teaches the semiconductor device according to claim 2, but does not teach the semiconductor device further comprising: a conductive plate member bonded to a surface of the insulating member on a side opposite to a surface bonded to the first insulating layer.
Choi teaches a semiconductor device (200, FIG. 12, [0033, 0039]) further comprising: a conductive plate member (conductive layer 222, [0040]) bonded to a surface of the insulating member on a side opposite to a surface bonded to the first insulating layer (222 bonded to the backside surface of insulating dielectric layer 220, opposite the front side surface facing semiconductor die 242, FIG. 12, [0035, 0039]).
As taught by Choi, one of ordinary skill in the art would utilize and modify the above teaching into YAMAMOTO in view of Kim and Schweitzer to obtain and achieve the semiconductor device further comprising: a conductive plate member bonded to a surface of the insulating member on a side opposite to a surface bonded to the first insulating layer as claimed, because the conductive backside layer dissipates heat transmitted through the insulating dielectric layer while the dielectric layer maintain electrical isolation of the semiconductor device [0035, 0041].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Choi in combination with YAMAMOTO in view of Kim and Schweitzer due to the above reason.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure in that Tsunemi et al. (US 2015/0137238), and Motoyama et al. (US 2017/0069586) as semiconductor devices having a semiconductor element and a bonded support substrate.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/16/26
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