DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-14, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada PG PUB 20160012902 (hereinafter Harada), in view of Shibata PG PUB 20070171721 (hereinafter Shibata).
Regarding independent claim 1, Harada teaches a method of controlling a memory device, comprising:
receiving a write instruction (S0 in figure 4A of Harada, write command in figure 5A of Harada, [0076] of Harada, “…when a write command (“8×Al D 1×”) is issued at time t0…”);
starting a write operation to a first address in response to the write instruction (t1-t2 in figure 5A of Harada, [0076] of Harada, “…the nonvolatile semiconductor memory device 10 executes the write operation based on this command (times t1 to t2 in FIG. 5A)… “Al” indicates the address of the memory cell MC of the write target, and “D” indicates the write data…”);
receiving a first read instruction of the first address ([0077] of Harada, “…at time t2, when the memory controller 20 issues the interrupt command (“XX” in FIG. 5A), the controller 150 interrupts the write operation up to that time…”);
suspending the write operation ([0014] of Harada, “…receive a first command to interrupt the write operation…”);
applying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction (S4 in figure 4A of Harada, [0071] of Harada, “…Upon receiving the read command, the controller 150 issues the busy signal of “L” level to the memory controller 20 and starts the read operation (step S4, FIG. 4B)…”);
resuming the write operation after applying the read voltage (S7 in figure 4A of Harada, [0014] of Harada, “…resumes the write operation based on the write data and the write voltage held in the register upon receiving the resumption command…”); and
outputting read data corresponding to the first address from a data register (SDL/UDL/LDL/XDL in figure 3 of Harada, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”)
Harada teaches in [0094] that “output the read data to the register 170 without destroying the write data”, teaches in [0096] that “the register 170 in the nonvolatile semiconductor memory device 10 holds information immediately before the interrupt. Hence, even when the resumption command is received, the write voltage may be transferred to the word line WL from the point of interrupt”, indicating read data output is decoupled from write operation, while write data is preserved and can resume later.
But Harada does not teach outputting read data during a period starting at resuming the write operation and ending at completion of the write operation. Rather Harada teaches in figure 5A read data output occurs before write resume.
However, Shibata teaches in [0128] that “the last write operation may be resumed during the output of result of the read operation to the external device”, teaches in [0133] that “the read data is subsequently transferred to SDC and then output to the external device. During the output, the last write operation may be resumed”. Further evidence can be seen in [0157]-[0158] (“during the output of the data from SDC to the external device, reading is performed”), suggesting continuous overlapping architecture. Shibata uses PDC and SDS to enable buffering, pipelining, and concurrent operations, resulting output operations occurs in parallel with internal memory operations.
It would have been obvious to modify Harada to include Shibata’s overlapping operation in order to increase read speed and reduce latency.
Regarding claim 2, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: setting a ready/busy signal to a busy state in response to the first read instruction ([0077] of Harada, “…the controller 150 interrupts the write operation up to that time and changes the busy signal to “H” level at time t3…”); and applying the read voltage during the busy state (t5-t6 in figure 5A of Harada, [0077] of Harada, “…At time t4, the read command (“00 30” in FIG. 5A) is issued. Then, the controller 150 outputs the busy signal of “L” level to the memory controller 20 and executes the read operation during the period of times t5 to t6...”)
Regarding claim 3, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: outputting the read data from the data register based on a read enable signal (“read enable signal” has been interpreted as control signal enabling data output, [0038] of Harada, “…controller 150 generates a control signal to control the sequence of data write, read, and erase based on a command CMD (interrupt command, resumption command…”, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”)
Regarding claim 4, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: setting a ready/busy signal to a busy state in response to the write instruction ([0076] of Harada, “…when a write command (“8×Al D 1×”) is issued …the controller 150 issues the busy signal of “L” level to the memory controller 20…”); and setting the ready/busy signal to a ready state when the data register is ready to be used (Harada shows that busy equal to operation ongoing, ready means operation completed/data available, [0081] of Harada, “… read data is sequentially transferred to the register 170 via the I/O...”)
Regarding claim 5, the combination of Harada and Shibata teaches the method according to claim 4, wherein the ready/busy signal is set to the ready state before receiving the first read instruction ([0076]/[0077] of Harada teaches busy asserted during write, and transitions occurs before read command timing, figure 5A show read command issued after state transition).
Regarding claim 7, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: transmitting write data of a first memory cell held by a latch circuit (SDL/UDL/LDL/XDL in figure 3 of Harada, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”) in a sense amplifier to the data register as read data (Harada teaches that both read data and stored write data are transferred through same data path (SDL[Wingdings font/0xE0]UDL[Wingdings font/0xE0]XDL[Wingdings font/0xE0]register 170), such that data stored in latch circuits can output via same path used for read data, thereby reasonably corresponding to transmitting write data as read data), wherein the first memory cell is connected to the word line and writing of the write data to the first memory cell is not completed ([0044] of Harada, “…the register 170 holds … write data at the time of interrupt of the write operation, and the status (threshold distribution) to which the memory cell MC has transited at the time of interrupt…”)
Regarding claim 8, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: transmitting data read from a second memory cell to the data register as read data (SDL/UDL/LDL/XDL in figure 3 of Harada, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”), wherein the second memory cell is connected to the word line and writing of write data to the second memory cell is completed (second cell is a cell already reached target state).
Regarding claim 9, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: transmitting write data of a first memory cell held by a latch circuit to the data register as read data (SDL/UDL/LDL/XDL in figure 3 of Harada, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”); and transmitting data read from a second memory cell to the data register as read data, wherein the first memory cell and the second memory cell are connected to the word line, writing of the write data to the first memory cell is not completed ([0044] of Harada, “…the register 170 holds … write data at the time of interrupt of the write operation, and the status (threshold distribution) to which the memory cell MC has transited at the time of interrupt…”), and writing of the write data to the second memory cell is completed (second cell is sharing WL with first cell and is a cell already reached target state).
Regarding claim 10, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: resuming the write operation (S7 in figure 4A of Harada) after the first read operation (S4 in figure 4A of Harada).
Regarding claim 11, the combination of Harada and Shibata teaches the method according to claim 1, further comprising:
setting a ready/busy signal to a busy state in response to the write instruction (t0-t1 in figure 5A of Harada, Busyn=”H”, [0076] of Harada, “…when a write command (“8×Al D 1×”) is issued at time to, the nonvolatile semiconductor memory device 10 executes the write operation based on this command (times t1 to t2 in FIG. 5A)…”);
setting the ready/busy signal to a ready state (t1 in figure 5A of Harada, BuSyn=”L”) from the busy state upon completion of transmission of write data from the data register to a latch circuit (figure 4B of Harada, “break write (stored in register 170)” occurs after program phase, prior to t1, data is programmed/transferred into internal latch (XDL/LDL/SDL), at completion, device exits busy);
setting the ready/busy signal to the busy state (t3 in figure 5A of Harada, Busyn=”H” of Harada) from the ready state after the suspending the write operation (S1-S2 in figure 4A of Harada); and
setting the ready/busy signal to the ready state (t5 in figure 5A of Harada, Busyn=”L” of Harada, or at T8 in figure 5A of Harada, upon completion of the read operation (data output at t5-t8, the ready/busy signal returns to a ready state) from the busy state upon completion of the first read operation (S4-S5 in figure 4A of Harada).
Note: the read/busy signal transition in Harada are directly associated with operational states, where busy corresponds to execution of write or read operations, and ready corresponding to completion or suspension states, as evidenced by figure 5A/5B and [0076]-[0077].
Regarding claim 12, the combination of Harada and Shibata teaches the method according to claim 1, further comprising:
setting a ready/busy signal to a busy state in response to the write instruction (t0-t1 in figure 5A of Harada, Busyn=”H”, [0076] of Harada, “…when a write command (“8×Al D 1×”) is issued at time to, the nonvolatile semiconductor memory device 10 executes the write operation based on this command (times t1 to t2 in FIG. 5A)…”, figure 5A of Harada teaches a single continuous operation sequence including writing, suspend, read, and resume operation, wherein the ready/busy sugnal transitions occur in the claimed order within the same operational timeline);
setting the ready/busy signal to a ready state from the busy state after the suspending the write operation (at t1, upon issuance of the break (suspend) command, the device transitions to Busy=”L” of Harada);
setting the ready/busy signal to the busy state from the ready state in response to the first read instruction (t4-t5 in figure 5A of Harada);
setting the ready/busy signal to the ready state from the busy state upon completion of the first read operation (t5-t8 in figure 5A of Harada, data out occurs, after completion, data returns to idle/ready); and
setting the ready/busy signal to the busy state from the ready state in response to a resume command to resume the write operation (6-S7 in figure 4A of Harada, figure 5A continuation, in response to a resume command (after the read phase), the device resumes the write operation and transitions from ready to a busy state).
Regarding claim 13, the combination of Harada and Shibata teaches the method according to claim 1, wherein the suspending the write operation is performed in response to a suspend command ([0077] of Harada, “…when the memory controller 20 issues the interrupt command (“XX” in FIG. 5A), the controller 150 interrupts the write operation up to that time and changes the busy signal to “H” level at time t3...”, under BRI, an “interrupt command” is reasonably interpreted as a “suspend command” because it causes temporary cessation of the write operation without termination).
Regarding claim 14, the combination of Harada and Shibata teaches the method according to claim 1, wherein the resuming the write operation is performed in response to a resume command ([0085] of Harada, “…when the memory controller 20 issues the resumption command (“YY” in FIG. 5A) at time t10, the controller 150 that has received it issues the busy signal of “L” level and resumes the write operation…”, [0073] of Harada, “…upon receiving the resumption command from the memory controller 20 (step S6), the controller 150 refers to the register 170 and resumes the write operation…”)
Regarding claim 19, the combination of Harada and Shibata teaches the method according to claim 7, wherein the transmitting the write data of the first memory cell held by the latch circuit in the sense amplifier to the data register as read data includes:
transmitting read data from the first memory cell to the data register (figure 5B/6B/7B of Harada teaches read data transfers from memory array to sense unit to SDL/UDK/LDL, then forward to data register/ DBUS); and
transmitting the write data from the latch circuit to the data register when the writing of the write data to the first memory cell is not completed (figure 7A/7B of Harada teaches LDL/XDL keep hold program data during program, suspension period, and later resumed phase, figure 7A teaches overwrite read data, [0103] of Harada, “…write data and QPW data stored in the UDL and the LDL…”, [0126], “…rewrite based on the data stored in the XDL and the LDL…”, S14 in figure 9 of Harada, Harada teaches that write data is stored in latch circuits including LDL/UDL ([0103]). During suspended write operation (figure 5A, t1-t2), data is read and transferred to the register 170 via latch structures. As shown in figure 7A, red data is overwritten by data stored in the latch circuits. Accordingly, Harada teaches transmitting write data from a latch circuit to a data register when the write operation is not completed).
Regarding claim 20, the combination of Harada and Shibata teaches the method according to claim 7, wherein the transmitting the write data of the first memory cell held by the latch circuit in the sense amplifier to the data register as read data includes: replacing data read from the first memory cell with the write data held by the latch circuit in the sense amplifier ([0108] of Harada, “… read data is overwritten on QPW data stored in a UDL..”, Harada teaches that data stored in latch circuits (LDL/XDL/UDL) is transferred to register 170 via the same output path used for read data ([0080]-[0081], and that during suspension the stored write data may overwrite read data ([0103]), thereby causing the latch-stored write data to be output through the read data path, which corresponds to transmitting write data as read data)
Claims 6, 15, 16, 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada PG PUB 20160012902 (hereinafter Harada), in view of Shibata PG PUB 20070171721 (hereinafter Shibata), further in view of Lee PG PUB 20180197610 (hereinafter Lee).
Regarding claim 6, the combination of Harada and Shibata teaches the method according to claim 1, but does not teach wherein the write operation before the suspending includes at least one loop of a program operation and a verify operation, and the write operation after the resuming includes at least one loop of a program operation and a verify operation.
However, Lee teaches in figure 12 the write operation before the suspending includes at least one loop of a program operation and a verify operation (N-LOOP in figure 12 of Lee), and the write operation after the resuming includes at least one loop of a program operation and a verify operation ((N+1)-LOOP in figure 12 of Lee).
It would have been obvious to modify Harada to include Shibata’s overlapping operation, to further include the detail suspend/resume operation of Lee such that the write operation before the suspending includes at least one loop of a program operation and a verify operation (N-LOOP in figure 12 of Lee), and the write operation after the resuming includes at least one loop of a program operation and a verify operation ((N+1)-LOOP in figure 12 of Lee), in order to allow read operations to be performed during programming, thereby enabling concurrent memory access operations, , and improving programming efficiency.
Regarding claim 15, the combination of Harada and Shibata teaches the method according to claim 1, wherein: the write operation includes repeating a program loop including a program operation and a verify operation (figure 4B of Harada).
But the combination of Harada and Shibata does not teach the suspending the write operation is performed upon completion of the program operation in one program loop, and the resuming the write operation is started by performing the verify operation in said one program loop.
However, Lee teaches in figure 13 and [0113] that “when a suspend command is input during the program execution operation of the N-loop, the non-volatile memory device 100 may immediately enter the suspend state without the performance of the program verify operation after finishing the program execution operation.”. Lee further teaches in [0113] that “the resumed program operation may start with the program verify operation of the N-loop”. Therefore, Lee teaches the suspending the write operation is performed upon completion of the program operation in one program loop (N-LOOP in figure 13 of Lee), and the resuming the write operation is started by performing the verify operation in said one program loop (N-LOOP in figure 13 of Lee).
It would have been obvious to modify Harada to include Shibata’s overlapping operation, to further include the detail suspend/resume operation of Lee such that the suspending the write operation is performed upon completion of the program operation in one program loop (N-LOOP in figure 13 of Lee), and the resuming the write operation is started by performing the verify operation in said one program loop (N-LOOP in figure 13 of Lee), in order to allow read operations to be performed during programming, thereby enabling concurrent memory access operations.
Regarding claim 16, the combination of Harada and Shibata teaches the method according to claim 1, wherein: the write operation includes repeating a program loop including a program operation and a verify operation (figure 4B of Harada).
But the combination of Harada and Shibata does not teach the suspending the write operation is performed upon completion of the verify operation in one program loop, and the resuming the write operation is started by performing the completed verify operation again in said one program loop.
However, Lee teaches in [0109] that “when the suspend command is input during the program execution operation of the N-loop, the non-volatile memory device 100 may enter the suspend state after completing up to the program verify operation of the N-loop without immediately entering the suspend state after finishing the program execution operation”. Lee further teaches in [0113] that “the resumed program operation may start with the program verify operation of the N-loop”. Therefore, Lee teaches the suspending the write operation is performed upon completion of the verify operation in one program loop ([109] of Lee), and the resuming the write operation is started by performing the completed verify operation again in said one program loop ([113] of Lee).
It would have been obvious to modify Harada to include Shibata’s overlapping operation, to further include the detail suspend/resume operation of Lee such that the suspending the write operation is performed upon completion of the verify operation in one program loop ([109] of Lee), and the resuming the write operation is started by performing the completed verify operation again in said one program loop ([113] of Lee), in order to allow read operations to be performed during programming, thereby enabling concurrent memory access operations, , and improving programming efficiency.
Regarding claim 17, the combination of Harada and Shibata teaches the method according to claim 1, wherein: the write operation includes repeating a program loop including a program operation and a verify operation (figure 4B of Harada).
But the combination of Harada and Shibata does not teach the suspending the write operation is performed upon completion of the verify operation in one program loop, and the resuming the write operation is started by performing the program operation in another program loop.
However, Lee teaches in figure 12 that the suspending the write operation is performed upon completion of the verify operation in one program loop (N-LOOP in figure 12 of Lee), and the resuming the write operation is started by performing the program operation in another program loop ((N+1)-LOOP in figure 12 of Lee).
It would have been obvious to modify Harada to include Shibata’s overlapping operation, to further include the detail suspend/resume operation of Lee such that the suspending the write operation is performed upon completion of the verify operation in one program loop (N-LOOP in figure 12 of Lee), and the resuming the write operation is started by performing the program operation in another program loop ((N+1)-LOOP in figure 12 of Lee), in order to allow read operations to be performed during programming, thereby enabling concurrent memory access operations, and improving programming efficiency.
Regarding claim 18, the combination of Harada, Shibata and Lee teaches the method according to claim 1, further comprising: repeatedly performing a program loop including a program operation and a verify operation, wherein a write voltage applied to the word line is stepped up every time the program operation is repeated (figure 4B of Harada, figure 12 of Lee).
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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