Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 7/23/2026. The changes and remarks disclosed therein have been considered. Claims 1, 18 have been amended. Therefore, claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-14, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada PG PUB 20160012902 (hereinafter Harada), in view of Shibata PG PUB 20070171721 (hereinafter Shibata).
Regarding independent claim 1, Harada teaches a method of controlling a memory device, comprising:
receiving a write instruction (S0 in figure 4A of Harada, write command in figure 5A of Harada, [0076] of Harada, “…when a write command (“8×Al D 1×”) is issued at time t0…”);
starting a write operation to a first address in response to the write instruction (time t1-t2 in figure 5A of Harada, [0076] of Harada, “…the nonvolatile semiconductor memory device 10 executes the write operation based on this command (times t1 to t2 in FIG. 5A)… “Al” indicates the address of the memory cell MC of the write target, and “D” indicates the write data…”);
Applying a program voltage to a word line corresponding to the first address in the write operation (the stepped write voltages V1-V4 applied before interruption in figure 4B of Harada; [0067] of Harada, “…the write voltage transferred to the word line WL rises stepwise as the write count increases. This aims at raising the threshold voltage of the memory cell MC up to the target voltage…”, see also [0042] of Harada, wherein the voltage generator generates a write voltage and the row decoder applies the generated voltage to a selected word line);
receiving a first read instruction of the first address during the write operation (the read command received at time t4 in figure 5A of Harada; S3 in figure 4A of Harada; [0069]-[0071] of Harada, after interruption of the write operation and before completion, the memory controller issues a read command and the controller starts a read operation, the recitation “during the write operation” is interpreted as requiring that the write operation has been started and has not yet been completed when the read instruction is received. Harada’s write operation begins in response to the write command, is temporarily interrupted, and is thereafter resumed. Accordingly, the read command received during the temporarily interruption is received during the overall, uncompleted write operation);
suspending the write operation ([0014] of Harada, “…receive a first command to interrupt the write operation…”, S1-S2 in figure 4A of Harada);
applying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction (S4 in figure 4A of Harada, [0071] of Harada, “…Upon receiving the read command, the controller 150 issues the busy signal of “L” level to the memory controller 20 and starts the read operation (step S4, FIG. 4B)…”);
resuming the write operation after applying the read voltage (S7 in figure 4A of Harada, [0014] of Harada, “…resumes the write operation based on the write data and the write voltage held in the register upon receiving the resumption command…”); and
outputting read data corresponding to the first address from a data register (SDL/UDL/LDL/XDL in figure 3 of Harada, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”)
Harada teaches in [0094] that the interrupt operation permits the memory device to “output the read data to the register 170 without destroying the write data”, and teaches in [0096] that “the register 170 in the nonvolatile semiconductor memory device 10 holds information immediately before the interrupt. Hence, even when the resumption command is received, the write voltage may be transferred to the word line WL from the point of interrupt”, indicating preserving the interrupted programming state while permitting a requested read operation.
But Harada does not teach (1) that the first read instruction specifies the same first address as the interrupted write operation, (2) that the read voltage is therefore applied to the same word line corresponding to the first address, and (3) outputting read data during a period starting at resuming the write operation and ending at completion of the write operation.
However, Shibata teaches reading data associated with a memory cell/page involved in a write operation by applying a read potential to the selected word line corresponding to that memory cell/page. For example, Shibata teaches in [0106] that, before or in connection with writing data to a selected memory cell, an internal read operation reads data from that memory cell, and the selected word line is supplied with a read potential. Shibata therefore teaches that data associated with selected memory cells and selected word lines involved in a programming operation may be read by applying a read potential to that selected word line.
Shibata further teaches overlapping resumed writing with output of preciously read data. Shibata teaches in [0128] that “the last write operation may be resumed during the output of result of the read operation to the external device”, and teaches in [0133] that “the read data is subsequently transferred to SDC and then output to the external device. During the output, the last write operation may be resumed”. Further evidence can be seen in [0157]-[0158] (“during the output of the data from SDC to the external device, reading is performed”), suggesting continuous overlapping architecture. Shibata uses PDC and SDS to enable buffering, pipelining, and concurrent operations, resulting output operations occurs in parallel with internal memory operations.
Harada teaches suspending a write operation in response to a read request and applying a read voltage to perform the requested read operation. Shibata teaches that cache-read operations in NAND flash may be performed on previously programmed page data while programming operations are ongoing, including outputting read data while the interrupted programming is resumed ([157]-[158]. Since NAND memories perform upper-page programming on cells that already contain lower-page data, one of ordinary skill in the art would have understood that the requested read operation may be directed to the same word line undergoing upper-page programming in order to obtain the previously programmed lower-page data, yielding the claimed applications of the read voltage to the word line corresponding to the first address.
It would have been obvious to modify Harada so that the read command identifies the same address as the interrupted write command and therefore causes the read voltage to be applied to the same selected word line, as taught by Shibata. Such a modification would permit the memory device to obtain or inspect the data presently associated with the selected memory cells while the write operation remains incomplete, without requiring completion of the entire write operation before the addressed data may be accessed).
It would have been obvious to modify Harada to resume the interrupted write operation while the read data retained in the data register is being output, as taught by Shibata, in order to overlap internal write operation with external data transfer in order to increase read speed and reduce latency.
Regarding claim 2, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: setting a ready/busy signal to a busy state in response to the first read instruction ([0078] of Harada, “…At time t4, the read command (“00 30” in FIG. 5A) is issued. Then, the controller 150 outputs the busy signal of “L” level to the memory controller 20 and executes the read operation during the period of times t5 to t6…”, after the read command “00 30” is issued at t4, the controller 150 output Busyn at the “L” level, corresponding to busy state); and applying the read voltage during the busy state (At time t4, the read command (“00 30” in FIG. 5A) is issued. Then, the controller 150 outputs the busy signal of “L” level to the memory controller 20 and executes the read operation during the period of times t5 to t6...”, [0071] of Harada, “…Upon receiving the read command, the controller 150 issues the busy signal of “L” level to the memory controller 20 and starts the read operation (step S4, FIG. 4B)…”)
Regarding claim 3, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: outputting the read data from the data register based on a read enable signal (“read enable signal” has been interpreted as control signal enabling data output, [0038] of Harada, “…controller 150 generates a control signal to control the sequence of data write, read, and erase based on a command CMD (interrupt command, resumption command…”, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”)
Regarding claim 4, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: setting a ready/busy signal to a busy state in response to the write instruction ([0076] of Harada, “…when a write command (“8×Al D 1×”) is issued …the controller 150 issues the busy signal of “L” level to the memory controller 20…”, [0044], [0068]-[0070], an d[0096] of Harada); and setting the ready/busy signal to a ready state when the data register is ready to be used (Harada shows that busy equal to operation ongoing, ready means operation completed/data available, [0081] of Harada, “… read data is sequentially transferred to the register 170 via the I/O...”)
Regarding claim 5, the combination of Harada and Shibata teaches the method according to claim 4, wherein the ready/busy signal is set to the ready state before receiving the first read instruction ([0076]/[0077] of Harada teaches busy asserted during write, and transitions occurs before read command timing, figure 5A show read command issued after state transition).
Regarding claim 7, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: transmitting write data of a first memory cell held by a latch circuit (SDL/UDL/LDL/XDL in figure 3 of Harada, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”) in a sense amplifier to the data register as read data (Harada teaches that both read data and stored write data are transferred through same data path (SDL[Wingdings font/0xE0]UDL[Wingdings font/0xE0]XDL[Wingdings font/0xE0]register 170), such that data stored in latch circuits can output via same path used for read data, thereby reasonably corresponding to transmitting write data as read data), wherein the first memory cell is connected to the word line and writing of the write data to the first memory cell is not completed ([0044] of Harada, “…the register 170 holds … write data at the time of interrupt of the write operation, and the status (threshold distribution) to which the memory cell MC has transited at the time of interrupt…”)
Regarding claim 8, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: transmitting data read from a second memory cell to the data register as read data (SDL/UDL/LDL/XDL in figure 3 of Harada, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”), wherein the second memory cell is connected to the word line and writing of write data to the second memory cell is completed (second cell is a cell already reached target state).
Regarding claim 9, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: transmitting write data of a first memory cell held by a latch circuit to the data register as read data (SDL/UDL/LDL/XDL in figure 3 of Harada, [0080]-[0081] of Harada, “… read data is temporarily stored in the SDL (represented by (1) in FIG. 5B), … transferred from the SDL to the UDL… is output to the register 170 via the XDL. The read data is sequentially transferred to the register 170 via the I/O…”); and transmitting data read from a second memory cell to the data register as read data, wherein the first memory cell and the second memory cell are connected to the word line, writing of the write data to the first memory cell is not completed ([0044] of Harada, “…the register 170 holds … write data at the time of interrupt of the write operation, and the status (threshold distribution) to which the memory cell MC has transited at the time of interrupt…”), and writing of the write data to the second memory cell is completed (second cell is sharing WL with first cell and is a cell already reached target state).
Regarding claim 10, the combination of Harada and Shibata teaches the method according to claim 1, further comprising: resuming the write operation (S7 in figure 4A of Harada) after the first read operation (S4 in figure 4A of Harada).
Regarding claim 11, the combination of Harada and Shibata teaches the method according to claim 1, further comprising:
setting a ready/busy signal to a busy state in response to the write instruction (BUSYn is set to the “L” level in response to the write command, [0076] of Harada, “…when a write command (“8×Al D 1×”) is issued at time to, the nonvolatile semiconductor memory device 10 executes the write operation based on this command (times t1 to t2 in FIG. 5A)…”);
setting the ready/busy signal to a ready state (Harada stores the write data necessary for resumption in the latch circuits, including the lower bit write data retained in LDL, and thereafter change BUSYn to “H” read level when the write operation is interrupted) from the busy state upon completion of transmission of write data from the data register to a latch circuit (figure 4B of Harada, “break write (stored in register 170)” occurs after program phase, prior to t1, data is programmed/transferred into internal latch (XDL/LDL/SDL), at completion, device exits busy);
setting the ready/busy signal to the busy state (Busyn change to ”L” busy level after issuance of the read command at t4 and during execution and during execution of the read operation from t5-t6 of Harada) from the ready state after the suspending the write operation (S1-S2 in figure 4A of Harada); and
setting the ready/busy signal to the ready state (Busyn=”H” of Harada, or at T8 in figure 5A of Harada, upon completion of the read operation (data output at t5-t8, the ready/busy signal returns to a ready state) from the busy state upon completion of the first read operation (S4-S5 in figure 4A of Harada).
Note: the read/busy signal transition in Harada are directly associated with operational states, where busy corresponds to execution of write or read operations, and ready corresponding to completion or suspension states, as evidenced by figure 5A/5B and [0076]-[0077].
Regarding claim 12, the combination of Harada and Shibata teaches the method according to claim 1, further comprising:
setting a ready/busy signal to a busy state in response to the write instruction (Busyn=”L”, [0076] of Harada, “…when a write command (“8×Al D 1×”) is issued at time to, the nonvolatile semiconductor memory device 10 executes the write operation based on this command (times t1 to t2 in FIG. 5A)…”, figure 5A of Harada teaches a single continuous operation sequence including writing, suspend, read, and resume operation, wherein the ready/busy signal transitions occur in the claimed order within the same operational timeline);
setting the ready/busy signal to a ready state from the busy state after the suspending the write operation (upon issuance of the break (suspend) command, the device transitions to Busy=”H” of Harada [0077] of Harada);
setting the ready/busy signal to the busy state from the ready state in response to the first read instruction (after issuance of the read command, BUSYn changes from “H” read level to “L” busy level while read operation is executed in figure 5A of Harada);
setting the ready/busy signal to the ready state from the busy state upon completion of the first read operation (t5-t8 in figure 5A of Harada, data out occurs, after completion, data returns to idle/ready); and
setting the ready/busy signal to the busy state from the ready state in response to a resume command to resume the write operation (6-S7 in figure 4A of Harada, figure 5A continuation, in response to a resume command (after the read phase), the device resumes the write operation and transitions from ready to a busy state).
Regarding claim 13, the combination of Harada and Shibata teaches the method according to claim 1, wherein the suspending the write operation is performed in response to a suspend command ([0077] of Harada, “…when the memory controller 20 issues the interrupt command (“XX” in FIG. 5A), the controller 150 interrupts the write operation up to that time and changes the busy signal to “H” level at time t3...”, under BRI, an “interrupt command” is reasonably interpreted as a “suspend command” because it causes temporary cessation of the write operation without termination).
Regarding claim 14, the combination of Harada and Shibata teaches the method according to claim 1, wherein the resuming the write operation is performed in response to a resume command ([0085] of Harada, “…when the memory controller 20 issues the resumption command (“YY” in FIG. 5A) at time t10, the controller 150 that has received it issues the busy signal of “L” level and resumes the write operation…”, [0073] of Harada, “…upon receiving the resumption command from the memory controller 20 (step S6), the controller 150 refers to the register 170 and resumes the write operation…”)
Regarding claim 19, the combination of Harada and Shibata teaches the method according to claim 7, wherein the transmitting the write data of the first memory cell held by the latch circuit in the sense amplifier to the data register as read data includes:
transmitting read data from the first memory cell to the data register (figure 5B/6B/7B of Harada teaches read data transfers from memory array to sense unit to SDL/UDK/LDL, then forward to data register/ DBUS); and
transmitting the write data from the latch circuit to the data register when the writing of the write data to the first memory cell is not completed (figure 7A/7B of Harada teaches LDL/XDL keep hold program data during program, suspension period, and later resumed phase, figure 7A teaches overwrite read data, [0103] of Harada, “…write data and QPW data stored in the UDL and the LDL…”, [0126], “…rewrite based on the data stored in the XDL and the LDL…”, S14 in figure 9 of Harada, Harada teaches that write data is stored in latch circuits including LDL/UDL ([0103]). During suspended write operation (figure 5A, t1-t2), data is read and transferred to the register 170 via latch structures. As shown in figure 7A, red data is overwritten by data stored in the latch circuits. Accordingly, Harada teaches transmitting write data from a latch circuit to a data register when the write operation is not completed).
Regarding claim 20, the combination of Harada and Shibata teaches the method according to claim 7, wherein the transmitting the write data of the first memory cell held by the latch circuit in the sense amplifier to the data register as read data includes: replacing data read from the first memory cell with the write data held by the latch circuit in the sense amplifier ([0108] of Harada, “… read data is overwritten on QPW data stored in a UDL..”, Harada teaches that data stored in latch circuits (LDL/XDL/UDL) is transferred to register 170 via the same output path used for read data ([0080]-[0081], and that during suspension the stored write data may overwrite read data ([0103]), thereby causing the latch-stored write data to be output through the read data path, which reasonable corresponds to outputting latch-held write data through the read-data output path).
Claims 6, 15, 16, 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harada PG PUB 20160012902 (hereinafter Harada), in view of Shibata PG PUB 20070171721 (hereinafter Shibata), further in view of Lee PG PUB 20180197610 (hereinafter Lee).
Regarding claim 6, the combination of Harada and Shibata teaches the method according to claim 1, but does not teach wherein the write operation before the suspending includes at least one loop of a program operation and a verify operation, and the write operation after the resuming includes at least one loop of a program operation and a verify operation.
However, Lee teaches in figure 12 the write operation before the suspending includes at least one loop of a program operation and a verify operation (N-LOOP in figure 12 of Lee), and the write operation after the resuming includes at least one loop of a program operation and a verify operation ((N+1)-LOOP in figure 12 of Lee).
It would have been obvious to modify Harada to include Shibata’s overlapping operation, to further include the detail suspend/resume operation of Lee such that the write operation before the suspending includes at least one loop of a program operation and a verify operation (N-LOOP in figure 12 of Lee), and the write operation after the resuming includes at least one loop of a program operation and a verify operation ((N+1)-LOOP in figure 12 of Lee), in order to allow read operations to be performed during programming, thereby enabling concurrent memory access operations, , and improving programming efficiency.
Regarding claim 15, the combination of Harada and Shibata teaches the method according to claim 1, wherein: the write operation includes repeating a program loop including a program operation and a verify operation (figure 4B of Harada).
But the combination of Harada and Shibata does not teach the suspending the write operation is performed upon completion of the program operation in one program loop, and the resuming the write operation is started by performing the verify operation in said one program loop.
However, Lee teaches in figure 13 and [0113] that “when a suspend command is input during the program execution operation of the N-loop, the non-volatile memory device 100 may immediately enter the suspend state without the performance of the program verify operation after finishing the program execution operation.”. Lee further teaches in [0113] that “the resumed program operation may start with the program verify operation of the N-loop”. Therefore, Lee teaches the suspending the write operation is performed upon completion of the program operation in one program loop (N-LOOP in figure 13 of Lee), and the resuming the write operation is started by performing the verify operation in said one program loop (N-LOOP in figure 13 of Lee).
It would have been obvious to modify Harada to include Shibata’s overlapping operation, to further include the detail suspend/resume operation of Lee such that the suspending the write operation is performed upon completion of the program operation in one program loop (N-LOOP in figure 13 of Lee), and the resuming the write operation is started by performing the verify operation in said one program loop (N-LOOP in figure 13 of Lee), in order to allow read operations to be performed during programming, thereby enabling concurrent memory access operations.
Regarding claim 16, the combination of Harada and Shibata teaches the method according to claim 1, wherein: the write operation includes repeating a program loop including a program operation and a verify operation (figure 4B of Harada).
But the combination of Harada and Shibata does not teach the suspending the write operation is performed upon completion of the verify operation in one program loop, and the resuming the write operation is started by performing the completed verify operation again in said one program loop.
However, Lee teaches in [0109] that “when the suspend command is input during the program execution operation of the N-loop, the non-volatile memory device 100 may enter the suspend state after completing up to the program verify operation of the N-loop without immediately entering the suspend state after finishing the program execution operation”. Lee further teaches in [0113] that “the resumed program operation may start with the program verify operation of the N-loop”. Therefore, Lee teaches the suspending the write operation is performed upon completion of the verify operation in one program loop ([109] of Lee), and the resuming the write operation is started by performing the completed verify operation again in said one program loop ([113] of Lee).
It would have been obvious to modify Harada to include Shibata’s overlapping operation, to further include the detail suspend/resume operation of Lee such that the suspending the write operation is performed upon completion of the verify operation in one program loop ([109] of Lee), and the resuming the write operation is started by performing the completed verify operation again in said one program loop ([113] of Lee), in order to allow read operations to be performed during programming, thereby enabling concurrent memory access operations, , and improving programming efficiency.
Regarding claim 17, the combination of Harada and Shibata teaches the method according to claim 1, wherein: the write operation includes repeating a program loop including a program operation and a verify operation (figure 4B of Harada).
But the combination of Harada and Shibata does not teach the suspending the write operation is performed upon completion of the verify operation in one program loop, and the resuming the write operation is started by performing the program operation in another program loop.
However, Lee teaches in figure 12 that the suspending the write operation is performed upon completion of the verify operation in one program loop (N-LOOP in figure 12 of Lee), and the resuming the write operation is started by performing the program operation in another program loop ((N+1)-LOOP in figure 12 of Lee).
It would have been obvious to modify Harada to include Shibata’s overlapping operation, to further include the detail suspend/resume operation of Lee such that the suspending the write operation is performed upon completion of the verify operation in one program loop (N-LOOP in figure 12 of Lee), and the resuming the write operation is started by performing the program operation in another program loop ((N+1)-LOOP in figure 12 of Lee), in order to allow read operations to be performed during programming, thereby enabling concurrent memory access operations, and improving programming efficiency.
Regarding claim 18, the combination of Harada, Shibata and Lee teaches the method according to claim 1, further comprising: repeatedly performing a program loop including a program operation and a verify operation, wherein a write voltage applied to the word line is stepped up every time the program operation is repeated (figure 4B of Harada, figure 12 of Lee).
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant argues that Harada and Shibata fail to teach or suggest: (1) applying both the program voltage and the read voltage to the same word line corresponding to the first address; (2) receiving the first read instruction during applicant of the program voltage.
Regarding the first point, the rejection is based on the combined teachings of Harada and Shibata rather than either reference individually. Harada teaches issuing a write command identifying address A1, where “A1” indicates the address of the memory cell severing as the write target, and beginning a write operation directed to that address. Harada further teaches interrupting that write operation, receiving a read command, performing a read operation, and thereafter resuming the interrupted write operation. See Harada, figure 4A, 4B, 5A and [0076]-[0078].
Although Harada does not expressively state the intervening read command is directed to the same address as the interrupted write operation, Shibata states that, in a NAND flash memory, data associated with a memory cell being programmed may be read as part of the programming process. Shibata teaches that an internal read operation is performed by applying a read potential to the selected word line before or in connection with programming the selected memory cells ([0116]-[0118]). Shibata further teach suspending a write operation, performing a read operation and resuming the write operation while outputting the read data ([0128], [0133]0, [0157]-[0158]).
In NAND flash memory, upper-page programming is performed on cells that already contain valid lower-page information, one of the ordinally skill in the art would have understood that NAND flash programming commonly employs multi-step programming, such a lower page and upper page programming. During upper page programming, the same physical memory cells and corresponding word line already contain valid lower page information. Accordingly, it would have been obviously to perform a read operation directed to that same word line in order to obtain previously programmed operation is temporary suspended, as suggested by Shibata. Applying Shibata’s teaching to Harada’s write-suspend/read/resume operation merely represents the predictable use of known NAND flash programming techniques to improve read responsiveness while preserving the interrupted programming state.
Accordingly, it would have been obviously to modify Harada such that the read operation is directed to the same addressed word line as the interrupted write operation, thereby applying both the program voltage and read voltage to the word line corresponding to the first address while maintaining the interrupted write state.
Applicant additionally argues that the claim 1 require the first read instruction to be received while the program voltage is being applied. This argument is also not persuasive because claim 1 recites receiving the first read instruction ”during the write operation”, not “during application of the program voltage”. Harada clearly teaches that the write operation has begun, is temporally suspended, and is later resumed. Therefore, the read instruction is received during the overall write operation, even though the read operation is executed after temporary suspension.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOCHUN L CHEN/Primary Examiner, Art Unit 2824
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