Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 4th, 2026 has been entered.
Response to Arguments
2. Applicant's arguments filed August 4th, 2026, with respect to the rejections of claims 11-20 have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Fleck et al (US 2001/0042193).
As Applicant’s arguments are directed toward limitations of the claims modified via amendment, they will be addressed in the rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-10 and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al (US 2019/0347125, herein Sankaran) in view of Ebersole (US 2013/0305013).
Regarding claim 1, Sankaran teaches a method comprising:
fetching, by a processor core, a plurality of machine code instructions ([1036-1037] instruction fetching, [1107], fetch stage);
decoding an opcode of a first machine code instruction of the plurality of machine code instructions, using the decoder ([1107-1109], decode stage, [1085], [1389], opcode); and
transmitting a second machine code instruction from the processor core to a coprocessor based decoding the opcode of the first machine code instruction ([1107-1110], dispatching decoded instructions to execution units based on operation needs and core type, [1105], coprocessor usage, [1085], [1389], opcodes).
Sankaran fails to teach the processor core being configured to fetch an instruction packet, determine, based on decoding the opcode of the first machine code instruction hat the first machine code instruction is associated with a coprocessor operation, or wherein a second machine code instruction of the plurality of machine code instructions corresponds to a no-operation for the processor core based on decoding the opcode of the first machine code instruction.
Ebersole teaches a system comprising a processor core configured to fetch an instruction packet ([0062], fetching instructions in batches) and determine, based on decoding the opcode of the first machine code instruction that the first machine code instruction is associated with a coprocessor operation ([0133], [0149], instructions that specify a routine to be handled by a specified coprocessor, [0069], [0091], use of opcodes), and determine by hardware logic that a machine code instruction of a plurality of machine code instructions corresponds to a no-operation for the processor core based on decoding the opcode of the first machine code instruction ([0149], treat decoded coprocessor routine instruction as no-op).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sankaran and Ebersole to utilize coprocessor-specific as well as no-op instructions. Sankaran does disclose the use of a coprocessor operation, but does not disclose explicit details of how such instructions are detected. Additionally, while Sankaran does disclose the use of no-op operations (Sankaran [0619-0622]), Sankaran discloses these for use in fence operations and interrupts. However, as detecting and handling both coprocessor-specific and no-op instructions are a routine and conventional aspect of the microprocessor art, utilizing them in a standard instruction set architecture would merely entail a simple substitution of known prior art elements to achieve predictable results, and therefore would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Sankaran and Ebersole teach the method of claim 1, further comprising: in response to determining that the first machine code instruction corresponds to the coprocessor operation, treating the second machine code instruction as a no-operation for the processor core (Ebersole [0149], treat coprocessor routines as no-ops).
Regarding claim 3, the combination of Sankaran and Ebersole teach the method of claim 1, wherein transmitting the second machine code instruction to the coprocessor comprises signaling, using hardware signals, an opcode of the second machine code instruction to the coprocessor (Sankaran [1082], instruction opcodes).
Regarding claim 4, the combination of Sankaran and Ebersole teach the method of claim 1, wherein the first machine code instruction includes the opcode and an operand, wherein the operand identifies the coprocessor among a plurality of coprocessors (Sankaran [1082], opcodes & [0411-0412], opcodes specific to accelerator, Ebersole [0133], coprocessor specific instructions).
Regarding claim 5, the combination of Sankaran and Ebersole teach the method of claim 4, further comprising determining whether to transmit the second machine code instruction to the coprocessor or another coprocessor of the plurality of coprocessors based on the opreand (Sankaran [1082], opcodes & [0411-0412], opcodes specific to accelerator, Ebersole [0069], [0133], coprocessor-specific opcodes).
Regarding claim 6, the combination of Sankaran and Ebersole teach the method of claim 1, further comprising: in response to determining that the first machine code instruction corresponds to the coprocessor operation, determining that a third machine code instruction of the plurality of machine code instructions is a load instruction; and performing a load operation, according to the load instruction, by the processor core and using a register of the coprocessor as a destination register (Sankaran [0932], loading data to accelerator storage, [1047], load to register).
Regarding claim 7, the combination of Sankaran and Ebersole teach the method of claim 1, further comprising: in response to determining that the first machine code instruction corresponds to the coprocessor operation, determining that a third machine code instruction of the plurality of machine code instructions is a load instruction; and performing a load operation, according to the load instruction, by the processor core and using a register of the coprocessor as a destination register (Sankaran [0902], [1042], store to register).
Regarding claim 8, the combination of Sankaran and Ebersole teach the method of claim 1, further comprising: receiving the second machine code instruction at the coprocessor; decoding the second machine code instruction by the coprocessor to generate a decoded instruction; and executing the decoded instruction by the coprocessor (Sankaran [0878-0880], execution by processing elements of accelerators).
Regarding claim 9, the combination of Sankaran and Ebersole teach the method of claim 1, further comprising: fetching a subsequent instruction packet having a subsequent plurality of machine code instructions by the processor core, wherein a third machine code instruction of the subsequent plurality of machine code instructions has a same opcode as the second machine code instruction; and decoding the third machine code instruction of the plurality of machine code instructions by the processor core to generate a subsequent decoded instruction, wherein the subsequent decoded instruction is different from the decoded instruction (Sankaran [0237], Ebersole [0074], decoding and executing subsequent instructions).
Regarding claim 10, the combination of Sankaran and Ebersole teach the method of claim 1, wherein the instruction packet includes the plurality of machine code instructions configured for processing in a same clock cycle (Sankaran [1085], [1114], parallel instruction execution).
Regarding claim 21, the combination of Sankaran and Ebersole teach the method of claim 1, wherein fetching the instruction packet includes a single fetch operation moving the plurality of machine code instructions from memory (Ebersole [0061-0062], fetching batches and individual instructions).
Regarding claim 18, Sankaran teaches a non-transitory computer readable medium storing computer executable code, which when executed by one or more processors causes the one or more processors to perform actions, wherein the computer executable code comprises:
a plurality of machine code instructions including (Fig 1, [0165], cores, memory, & dedicated SIMD or accelerator cores as coprocessors, [1105], embodying cores as coprocessors, [1036-1037] instruction fetching, [1107], fetch stage):
a first machine code instruction having a first opcode decoded by the one or more processors ([1107-1109], decode stage, [1051], instruction opcodes); and
a second machine code instruction having a second opcode, ([1107-1110], dispatching decoded instructions to execution units based on operation needs and core type, [1105], coprocessor usage, [1051], opcodes).
Sankaran fails to teach wherein the first and second opcode are configured to indicate that the a packet having the plurality of machine code instructions corresponds to a coprocessor and correspond to a first operation when executed by the one or more processors and a second operation when executed by the coprocessor.
Ebersole teaches a system comprising one or more processors wherein a first and second opcode are configured to indicate that a packet having the plurality of machine code instructions corresponds to a coprocessor and correspond to a first operation when executed by the one or more processors and a second operation when executed by the coprocessor (Table 1, [0069], opcodes, [0090], [0096], [0100], x86 opcode executed or treated as exception according to instruction mode, [0077-0080], [0133], [0138], [0149], handling coprocessor specific instructions according to which ISA the opcode corresponds to, [0062], fetching instruction batches).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sankaran and Ebersole to utilize opcode-specified coprocessor instructions. While Sankaran does disclose the use of opcodes and multiple ISAs such as x86 and ARM (Sankaran [1148]), Sankaran does not explicitly disclose that these instruction sets may be distinguished specifically by an opcode. However, as both the use of a coprocessor as the use of opcodes for distinguishing between instruction types are routine and conventional aspects of the microprocessor art, utilizing them would merely entail a simple substitution of known prior art elements to achieve predictable results, and therefore would have been obvious to one of ordinary skill in the art.
Regarding claim 19, the combination of Sankaran and Ebersole teach the non-transitory computer readable medium of claim 18, wherein the first machine code instruction further has an operand identifying the coprocessor among a plurality of coprocessors (Sankaran [1082], opcodes & [0411-0412], opcodes specific to accelerator, Ebersole [0133], coprocessor specific instructions).
Regarding claim 20, the combination of Sankaran and Ebersole teach the non-transitory computer readable medium of claim 18, wherein the plurality of machine code instructions further includes a third machine code instruction, wherein the third machine code instruction is a load or store instruction having an operand that identifies a register in the coprocessor as a source or destination register (Sankaran [0932], loading data to accelerator storage, [1047], load to register & [0902], [1042], store to register).
4. Claims 11-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran, Ebersole, and Fleck et al (US 2001/0042193, herein Fleck).
Regarding claim 11, Sankaran teaches a system comprising:
a processor core having hardware logic and a decoder; a memory; and a coprocessor (Fig 1, [0165], cores, memory, & dedicated SIMD or accelerator cores as coprocessors, [1105], embodying cores as coprocessors);
wherein the processor core is configured to:
fetch a plurality of machine code instructions from the memory ([1036-1037] instruction fetching, [1107], fetch stage);
decode an opcode of a first machine code instruction of the plurality of machine code instructions, using the decoder ([1107-1109], decode stage, [1085], [1389], opcode); and
transmit the second machine code instruction to the coprocessor based decoding the opcode of the first machine code instruction ([1107-1110], dispatching decoded instructions to execution units based on operation needs and core type, [1105], coprocessor usage, [1085], [1389], opcodes).
Sankaran fails to teach the processor core being configured to determine, based on decoding the opcode of the first machine code instruction hat the first machine code instruction is associated with a coprocessor operation, or wherein a second machine code instruction of the plurality of machine code instructions corresponds to a no-operation for the processor core based on decoding the opcode of the first machine code instruction.
Ebersole teaches a system comprising a processor core configured to fetch a packet having a plurality of machine code instructions ([0062], fetching instructions in batches) and determine, based on decoding the opcode of the first machine code instruction that the packet is associated with a coprocessor operation ([0133], [0149], instructions that specify a routine to be handled by a specified coprocessor, [0069], [0091], use of opcodes), and determine by hardware logic that a machine code instruction of a plurality of machine code instructions corresponds to a no-operation for the processor core based on decoding the opcode of the first machine code instruction ([0149], treat decoded coprocessor routine instruction as no-op).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sankaran and Ebersole to utilize coprocessor-specific as well as no-op instructions. Sankaran does disclose the use of a coprocessor operation, but does not disclose explicit details of how such instructions are detected. Additionally, while Sankaran does disclose the use of no-op operations (Sankaran [0619-0622]), Sankaran discloses these for use in fence operations and interrupts. However, as detecting and handling both coprocessor-specific and no-op instructions are a routine and conventional aspect of the microprocessor art, utilizing them in a standard instruction set architecture would merely entail a simple substitution of known prior art elements to achieve predictable results, and therefore would have been obvious to one of ordinary skill in the art.
Sankaran and Ebersole fail to teach wherein the opcode designates the packet as being associated with the coprocessor operation.
Fleck teaches a system comprising a processor core, memory, and coprocessor (Fig 1, [0012-0015], processor, memory and cache, coprocessors), wherein an opcode designates an instruction as being associated with a coprocessor operation ([0016-0017], coprocessor identification within bits of opcode field).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sankaran and Ebersole with those of Fleck to utilize coprocessor designation within instruction opcodes. While Sankaran does teach the use of opcodes which are indicative of coprocessor operations, Sankaran and Ebersole do not explicitly state that bits of an opcode may designate a coprocessor to be used by the instruction. However, as all three references disclose coprocessor-specific instructions that utilize instruction opcodes, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 12, the combination of Sankaran, Ebersole, and Fleck teaches the system of claim 11, herein the processor core is further configured to: determine that all machine code instructions of the plurality of machine code instructions, except for any load or store instructions, correspond to no-operations based on the decoding the opcode of the first machine code instruction (Ebersole [0149], treat microcode routines as no-ops, [0056], [0069], [0091], translating instructions into microinstructions; instruction opcodes).
Regarding claim 13, the combination of Sankaran, Ebersole, and Fleck teaches the system of claim 11, wherein the processor core is further configured to: decode a third machine code instruction of the plurality of machine code instructions to generate a decoded instruction; and perform a load operation according to the decoded instruction by the processor core, including using a register within the coprocessor as a destination register (Sankaran [0932], loading data to accelerator storage, [1047], load to register).
Regarding claim 14, the combination of Sankaran, Ebersole, and Fleck teaches the system of claim 13, wherein the processor core is further configured to: decode a fourth machine code instruction of the plurality of machine code instructions to generate a further decoded instruction; and perform a store operation according to the further decoded instruction by the processor core, including using another register within the coprocessor as a source register (Sankaran [0902], [1042], store to register)
Regarding claim 15, the combination of Sankaran, Ebersole, and Fleck teaches the system of claim 11, wherein the processor core is configured to transmit the second machine code instruction using a plurality of hardware signals, wherein the plurality of hardware signals are configured to carry data indicating an opcode of the second machine code instruction (Sankaran [1082], instruction opcodes).
Regarding claim 17, the combination of Sankaran, Ebersole, and Fleck teaches the system of claim 11, wherein the processor core is further configured to transmit the second machine code instruction to the coprocessor based on an operand of the first machine code instruction, where the operand is configured to identify the coprocessor (Sankaran [1082], opcodes & [0411-0412], opcodes specific to accelerator, Ebersole [0133], coprocessor specific instructions).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fryman (US 2019/0303159) discloses a processor that fetches instruction packets to be executed by a coprocessor.
Sundar (US 2016/0011875) discloses a processor wherein instruction opcodes correspond to a coprocessor.
Jensen (US 2007/0234020) discloses a processor wherein an opcode designates an instruction for a specific coprocessor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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