CTFR 18/810,333 CTFR 92202 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments 07-37 AIA 1 . Applicant's arguments filed November 10 th , 2025 have been fully considered but they are not persuasive. As Applicant’s arguments are directed toward limitations of the claims modified via amendment, they will be addressed in the rejections below . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 2 . Claim s 1-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al (US 2019/0347125, herein Sankaran) in view of Ebersole (US 2013/0305013) . In the following rejections, the system embodiment of claim 11 will be addressed first. Regarding claim 11, Sankaran teaches a system comprising: a processor core having hardware logic and a decoder; a memory; and a coprocessor (Fig 1, [0165], cores, memory, & dedicated SIMD or accelerator cores as coprocessors, [1105], embodying cores as coprocessors); wherein the processor core is configured to: fetch a plurality of machine code instructions from the memory ([1036-1037] instruction fetching, [1107], fetch stage); decode an opcode of a first machine code instruction of the plurality of machine code instructions, using the decoder ([1107-1109], decode stage, [1085], [1389], opcode); and transmit the second machine code instruction to the coprocessor based decoding the opcode of the first machine code instruction ([1107-1110], dispatching decoded instructions to execution units based on operation needs and core type, [1105], coprocessor usage, [1085], [1389], opcodes). Sankaran fails to teach the processor core being configured to determine, based on decoding the opcode of the first machine code instruction hat the first machine code instruction is associated with a coprocessor operation, or wherein a second machine code instruction of the plurality of machine code instructions corresponds to a no-operation for the processor core based on decoding the opcode of the first machine code instruction. Ebersole teaches a system comprising a processor core configured to determine, based on decoding the opcode of the first machine code instruction that the first machine code instruction is associated with a coprocessor operation ([0133], [0149], instructions that specify a routine to be handled by a specified coprocessor, [0069], [0091], use of opcodes), and determine by hardware logic that a machine code instruction of a plurality of machine code instructions corresponds to a no-operation for the processor core based on decoding the opcode of the first machine code instruction ([0149], treat decoded coprocessor routine instruction as no-op). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sankaran and Ebersole to utilize coprocessor-specific as well as no-op instructions. Sankaran does disclose the use of a coprocessor operation, but does not disclose explicit details of how such instructions are detected. Additionally, while Sankaran does disclose the use of no-op operations (Sankaran [0619-0622]), Sankaran discloses these for use in fence operations and interrupts. However, as detecting and handling both coprocessor-specific and no-op instructions are a routine and conventional aspect of the microprocessor art, utilizing them in a standard instruction set architecture would merely entail a simple substitution of known prior art elements to achieve predictable results, and therefore would have been obvious to one of ordinary skill in the art. Regarding claim 12, the combination of Sankaran and Ebersole teach the system of claim 11, herein the processor core is further configured to: determine that all machine code instructions of the plurality of machine code instructions, except for any load or store instructions, correspond to no-operations based on the decoding the opcode of the first machine code instruction (Ebersole [0149], treat microcode routines as no-ops, [0056], [0069], [0091], translating instructions into microinstructions; instruction opcodes). Regarding claim 13, the combination of Sankaran and Ebersole teach the system of claim 11, wherein the processor core is further configured to: decode a third machine code instruction of the plurality of machine code instructions to generate a decoded instruction; and perform a load operation according to the decoded instruction by the processor core, including using a register within the coprocessor as a destination register (Sankaran [0932], loading data to accelerator storage, [1047], load to register). Regarding claim 14, the combination of Sankaran and Ebersole teach the system of claim 13, wherein the processor core is further configured to: decode a fourth machine code instruction of the plurality of machine code instructions to generate a further decoded instruction; and perform a store operation according to the further decoded instruction by the processor core, including using another register within the coprocessor as a source register (Sankaran [0902], [1042], store to register) Regarding claim 15, the combination of Sankaran and Ebersole teach the system of claim 11, wherein the processor core is configured to transmit the second machine code instruction using a plurality of hardware signals, wherein the plurality of hardware signals are configured to carry data indicating an opcode of the second machine code instruction (Sankaran [1082], instruction opcodes). Regarding claim 17, the combination of Sankaran and Ebersole teach the system of claim 11, herein the processor core is further configured to transmit the second machine code instruction to the coprocessor based on an operand of the first machine code instruction, where the operand is configured to identify the coprocessor (Sankaran [1082], opcodes & [0411-0412], opcodes specific to accelerator, Ebersole [0133], coprocessor specific instructions). Claims 1, 3, 4, 6, and 7 refer to a method embodiment of the system embodiment of claims 11, 15, 17, 13, and 14, respectively. Therefore, the above rejections for claims 11, 15, 17, 13, and 14 are applicable to claims 1, 3, 4, 6, and 7, respectively. Regarding claim 2, the combination of Sankaran and Ebersole teach the method of claim 1, further comprising: in response to determining that the first machine code instruction corresponds to the coprocessor operation, treating the second machine code instruction as a no-operation for the processor core (Ebersole [0149], treat coprocessor routines as no-ops). Regarding claim 5, the combination of Sankaran and Ebersole teach the method of claim 4, further comprising determining whether to transmit the second machine code instruction to the coprocessor or another coprocessor of the plurality of coprocessors based on the opreand (Sankaran [1082], opcodes & [0411-0412], opcodes specific to accelerator, Ebersole [0069], [0133], coprocessor-specific opcodes). Regarding claim 8, the combination of Sankaran and Ebersole teach the method of claim 1, further comprising: receiving the second machine code instruction at the coprocessor; decoding the second machine code instruction by the coprocessor to generate a decoded instruction; and executing the decoded instruction by the coprocessor (Sankaran [0878-0880], execution by processing elements of accelerators). Regarding claim 9, the combination of Sankaran and Ebersole teach the method of claim 1, further comprising: fetching a subsequent instruction packet having a subsequent plurality of machine code instructions by the processor core, wherein a third machine code instruction of the subsequent plurality of machine code instructions has a same opcode as the second machine code instruction; and decoding the third machine code instruction of the plurality of machine code instructions by the processor core to generate a subsequent decoded instruction, wherein the subsequent decoded instruction is different from the decoded instruction (Sankaran [0237], Ebersole [0074], decoding and executing subsequent instructions). Regarding claim 10, the combination of Sankaran and Ebersole teach the method of claim 1, wherein the instruction packet includes the plurality of machine code instructions configured for processing in a same clock cycle (Sankaran [1085], [1114], parallel instruction execution). Regarding claim 18, Sankaran teaches a non-transitory computer readable medium storing computer executable code, which when executed by one or more processors causes the one or more processors to perform actions, wherein the computer executable code comprises: a plurality of machine code instructions including (Fig 1, [0165], cores, memory, & dedicated SIMD or accelerator cores as coprocessors, [1105], embodying cores as coprocessors, [1036-1037] instruction fetching, [1107], fetch stage): a first machine code instruction having a first opcode decoded by the one or more processors ([1107-1109], decode stage, [1051], instruction opcodes); and a second machine code instruction having a second opcode, ([1107-1110], dispatching decoded instructions to execution units based on operation needs and core type, [1105], coprocessor usage, [1051], opcodes). Sankaran fails to teach wherein the first and second opcode are configured to indicate that the plurality of machine code instructions corresponds to a coprocessor and correspond to a first operation when executed by the one or more processors and a second operation when executed by the coprocessor. Ebersole teaches a system comprising one or more processors wherein a first and second opcode are configured to indicate that the plurality of machine code instructions corresponds to a coprocessor and correspond to a first operation when executed by the one or more processors and a second operation when executed by the coprocessor (Table 1, [0069], opcodes, [0090], [0096], [0100], x86 opcode executed or treated as exception according to instruction mode, [0077-0080], [0133], [0138], [0149], handling coprocessor specific instructions according to which ISA the opcode corresponds to). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Sankaran and Ebersole to utilize opcode-specified coprocessor instructions. While Sankaran does disclose the use of opcodes and multiple ISAs such as x86 and ARM (Sankaran [1148]), Sankaran does not explicitly disclose that these instruction sets may be distinguished specifically by an opcode. However, as both the use of a coprocessor as the use of opcodes for distinguishing between instruction types are routine and conventional aspects of the microprocessor art, utilizing them would merely entail a simple substitution of known prior art elements to achieve predictable results, and therefore would have been obvious to one of ordinary skill in the art. Claims 19 and 20 refer to a medium embodiment of the system embodiment of claims 17 and the combination of 13 and 14, respectively. Therefore, the above rejections for claims 17, 13, and 14 are applicable to claims 19 and 20, respectively . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Muller (US 2021/0109760) discloses a processor that indicates a coprocessor operation with a decoded opcode of an instruction. Frank (US 2010/0153686) discloses a processor that fetches and decodes instructions which routes instructions to a coprocessor based on an opcode. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL J METZGER/ Primary Examiner, Art Unit 2183 Application/Control Number: 18/810,333 Page 2 Art Unit: 2183 Application/Control Number: 18/810,333 Page 3 Art Unit: 2183 Application/Control Number: 18/810,333 Page 4 Art Unit: 2183 Application/Control Number: 18/810,333 Page 5 Art Unit: 2183 Application/Control Number: 18/810,333 Page 6 Art Unit: 2183 Application/Control Number: 18/810,333 Page 7 Art Unit: 2183 Application/Control Number: 18/810,333 Page 8 Art Unit: 2183 Application/Control Number: 18/810,333 Page 9 Art Unit: 2183
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