Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on June 10th, 2024. It is noted, however, that applicant has not filed a certified copy of the KR10-2024-0074972 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 7-9, 12-15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Manning et al. (US 11,430,539), hereinafter Manning.
Regarding claim 1, Manning teaches a memory (Manning, Fig. 1, memory device 110) comprising: a memory array (Manning, Fig. 1, memory array 170, col. 3, lines 20-22, “a memory device 110 may include one or more microprocessors 175 on a same die 160 as a memory array 170”) configured to store write data therein and provide the write data stored therein as read data (Manning, col. 4, lines 65-67 through col. 5, lines 1-3, “the memory device 110 may receive a write command indicating that the memory device 110 is to store data for the host device 105-which may be referred to as user data-or a read command indicating that the memory device 110 is to provide data stored in a memory die 160 to the host device 105”); a nonvolatile memory circuit configured to store repair information therein (Manning, col. 2, lines 28-30, “If a memory device includes a non-volatile memory array [e.g., a ferroelectric memory array], repair information for the memory array may be stored in the memory array itself”); a repair latch circuit configured to receive the repair information from the nonvolatile memory circuit and store the received repair information during a boot-up operation (Manning, col. 2, lines 31-36, “The memory device may also include an on-die microprocessor, which may retrieve the repair information from the memory array [e.g., as part of a boot procedure for the die] and write the repair information to repair circuitry to support run-time comparisons of the repair information [e.g., to a set of latches…]”; the set of latches in the repair circuitry equates to a repair latch circuit); and a repair circuit configured to repair the memory array using the stored repair information of the repair latch circuit (Manning, col. 7, lines 1-5, “memory device 110 may receive the command from the host device 105, and may identify [e.g., using the repair circuitry] the memory address as a defective memory address based on the repair information previously programmed into the repair circuitry”).
Manning fails to explicitly teach wherein the boot-up operation is performed during an initial operation period of the memory and is performed one or more times thereafter. However, this teaching is obvious to the teachings of Manning because Manning teaches subsequent repair updates during the operation of the memory array (Manning, Abstract, lines 8-11, “The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array”; Fig. 7 teaches subsequent repair updates, specifically in steps 720 through 730).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Manning by including the functionality of configuring the microprocessor to configure the boot-up operation to be performed not just during an initial operation period, but also performed one or more times thereafter, as recited in the claim.
The suggestion/motivation for doing so would be to increase device accuracy and reliability (Manning, col. 2, lines 55-60, “Storing the repair information in the memory array, and programming the information from the array to repair circuitry by the microprocessor, may increase device accuracy, reliability, and speed, as well as decrease a footprint of the memory device [e.g., by reducing or eliminating one-time programmable repair information and related structures]”).
Regarding claim 2, Manning teaches the memory of claim 1, further comprising a boot-up control circuit configured to generate a boot-up signal, wherein, during the boot-up operation, the nonvolatile memory circuit transmits the repair information to the repair latch circuit in response to the boot-up signal (Manning, Fig. 6 teaches a repair operation initiated by control circuitry in a microprocessor; col. 13, lines 49-52, “In some cases, the microprocessor 320 may access and program the repair information during a startup of a memory device [e.g., as part of a boot procedure or a boot event]”).
Regarding claim 3, Manning teaches the memory of claim 2, wherein the boot-up control circuit activates the boot-up signal during the initial operation period of the memory (Manning, Fig. 6, col. 5, lines 40-44, “During a boot or start-up procedure [e.g., or at another time] the microprocessor 175 may access the repair information stored in the memory array 170 and may program the repair information into repair circuitry associated with the memory array 170”), and periodically activates the boot-up signal thereafter (Manning, Fig. 7 teaches updating/reprogramming the repair information multiple times after the initial repair information is stored).
Regarding claim 7, Manning teaches the memory of claim 2, wherein the boot-up control circuit activates the boot-up signal during the initial operation period of the memory (Manning, Fig. 6, col. 5, lines 40-44, “During a boot or start-up procedure [e.g., or at another time] the microprocessor 175 may access the repair information stored in the memory array 170 and may program the repair information into repair circuitry associated with the memory array 170”), and activates the boot-up signal when the boot-up operation is instructed by an external device of the memory (Manning, col. 3, lines 63-66, “the memory device 110 may act as a slave-type device to the host device 105 [e.g., responding to and executing commands provided by the host device 105 through the external memory controller 120]”).
Regarding claim 8, Manning teaches the memory of claim 7, wherein the external device incudes a memory controller, and the instruction on the boot-up operation is received from the memory controller through a command address bus (Manning, col. 3, lines 63-66, “the memory device 110 may act as a slave-type device to the host device 105 [e.g., responding to and executing commands provided by the host device 105 through the external memory controller 120]”). While the reference does not explicitly teach a command address bus, it teaches a memory controller issuing commands to control the memory. It is inherent that these instructions are conveyed via a command address bus, as that is the standard interface between a memory controller and a memory device.
Regarding claim 9, Manning teaches the memory of claim 7, wherein the external device includes a baseboard management controller (BMC), and the instruction on the boot-up operation is received from the baseboard management controller through a management bus (Manning, col. 3, lines 63-66, “the memory device 110 may act as a slave-type device to the host device 105 [e.g., responding to and executing commands provided by the host device 105 through the external memory controller 120]”). While the reference does not explicitly teach a baseboard management controller (BMC), a BMC is a well-known type of external management controller used to initiate recovery operations. It would have been obvious to one of ordinary skill in the art to use a BMC as the external device instructing the boot-up operation. Also, it would have been obvious that the instructions from the BMC would be received via a management bus, since management buses are conventionally used for communication between a BMC and system components.
Regarding claim 12, Manning teaches the memory of claim 1, wherein the nonvolatile memory circuit further stores setting information therein (Manning, col. 2, lines 28-30, “If a memory device includes a non-volatile memory array [e.g., a ferroelectric memory array], repair information for the memory array may be stored in the memory array itself”), and the memory further comprises: a setting latch circuit configured to store the setting information received from the nonvolatile memory circuit during the boot-up operation (Manning, Fig. 6, step 615); and a setting circuit configured to perform a setting operation of the memory using the setting information stored in the setting latch circuit (Manning, col. 11, lines 7-14, “the repair circuitry 275 may include some quantity of latches that the microprocessor 270 may program to store the repair information, and the repair circuitry 275 may also include comparison circuitry configured to compare memory addresses associated with access operations [e.g., memory addresses received from a host device] with the defective memory addresses associated with the repair information”).
Claim 13 is a memory system with limitations similar to the memory of claim 1, and is rejected under the same rationale.
Claim 14 is a memory system with limitations similar to the memory of claim 2, and is rejected under the same rationale.
Claim 15 is a memory system with limitations similar to the memory of claim 3, and is rejected under the same rationale.
Claim 19 is a memory system with limitations similar to the memory of claim 8, and is rejected under the same rationale.
Claim 20 is a memory system with limitations similar to the memory of claim 9, and is rejected under the same rationale.
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Manning, in view of Hummler (US 7,401,270).
Regarding claim 4, Manning teaches the memory of claim 2, wherein the boot-up control circuit activates the boot-up signal during the initial operation period of the memory (Manning, Fig. 6).
Manning fails to teach further comprising a latch error risk determination circuit configured to determine a risk of error of the repair latch circuit and activates the boot-up signal when the latch error risk determination circuit determines that there is the risk of error occurrence in the repair latch circuit.
However, Hummler, in an analogous art, teaches a memory further comprising a latch error risk determination circuit (Hummler, Fig. 4, steps 240-260 teach the existence of latches that store failure information and it also recognizes that failure information stored in the latches are susceptible to errors) configured to determine a risk of error occurrence (Hummler, Fig. 5, step 310, col. 4, lines 62-66, “In step 310, errors associated with accessing memory cells are monitored in order to detect when and if there are substantial errors that cannot be overcome by error correction techniques. Such errors may be called catastrophic errors”) of the repair latch circuit and activates the boot-up signal when the latch error risk determination circuit determines that there is the risk of error occurrence in the repair latch circuit (Hummler, Fig. 5, steps 320-330, col. 4, lines 67-68 through col. 5, lines 1-10, “In the event a catastrophic error condition is detected in step 310, then in step 320, the system is put in a standby mode during which time all data stored in the memory device is maintained as is; no further writing occurs. The command to put the memory device in standby may be an externally supplied command that is made after a system user [or application] is informed of the condition and a system user has indicated the desire to initiate the standby mode and re-issue the fuse pulse. Next, in step 330, the fuse pulse is re-issued to scan across the fuse banks and thereby restore the failure address information contained in the fuse banks to corresponding fuse latches”).
Manning and Hummler are both considered to be analogous to the claimed invention because both are in the same field of memory devices that utilize repair information.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Manning to incorporate the teachings of Hummler by including the functionality of configuring the boot-up operation control circuit to activate the boot-up operation not only during the initial start-up, but also in response to a risk determination process.
The suggestion/motivation for doing so would be to restore reliable repair information and improve memory reliability.
Claim 16 is a memory system with limitations similar to the memory of claim 4, and is rejected under the same rationale.
Allowable Subject Matter
Claims 5-6, 10-11, 17-18, and 21-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 24 and 25 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 24 is considered allowable over the prior art of record, as the cited references fail to teach of suggest a memory system including a baseboard memory controller connected via a management bus and configured to instruct the memory to perform a boot-up operation after the initial operation period.
Claim 25 is dependent on claim 24 and is allowed for the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Franceschini et al. (US 2014/0185398) teaches failure determination logic in a memory system, and the use of latches that use initial values to identify redundant elements.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112