DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2024-0020397, filed on 2/13/2024.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/21/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “SEMICONDUCTOR PACKAGE COMPRISING VERTICALLY STACKED OF MEMORY DIES WITH VIAS FOR CAPACITIVE ALINMENT OF THE MEMORY DIES AND METHOD FABRICATING THE SAME”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites on the last two lines of the claim that “a capacitance that corresponds to the first and second capacitors corresponds to an alignment between the first memory die and the second memory die”. Here, it is unclear what it is meant by the phrase “a capacitance that corresponds to the first and second capacitors”. For the purpose of examination, the limitation is considered to be “a capacitance measured by the first and second capacitors corresponds to an alignment between the first memory die and the second memory die”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-612 (US 2023/0139612 A1) in view of Ma (CN 117198907 A).
Regarding claim 1, Kim-612 teaches a semiconductor package (semiconductor module 100, Fig. 1, [0021]) comprising:
a package substrate (interposer 10, Fig. 1: the Examiner notes that the interposer was wrongly labeled as 20 in Fig. 1, please see the description in [0021]);
a first semiconductor chip (logic device 20, Fig. 1, [0021]) mounted on the package substrate (interposer 10, Fig. 1); and
a second semiconductor chip (semiconductor die stack 40 on the left, Fig. 1, [0021]) mounted on the package substrate (interposer 10, Fig. 1) and spaced apart from the first semiconductor chip (logic device 20, Fig. 1),
wherein the second semiconductor chip (semiconductor die stack 40 on the left, Fig. 1) includes:
a buffer die (base die 41, Figs. 2A-B, [0022]);
a first passivation film (front side passivation layer 61 on base die 41, Fig. 2B, [0032]) on the buffer die (base die 41, Fig. 2B);
a first memory die (lower core die 43a, Fig. 2B, [0041]: “The semiconductor substrate 60 of the core dies 43a-43c may include a silicon wafer and memory circuits that are formed on the silicon wafer.”) stacked on the first passivation film (front side passivation layer 61 on base die 41, Fig. 2B);
a second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B, [0032]) on the first memory die (lower core die 43a, Fig. 2B);
a second memory die (intermediate core die 43b, Fig. 2B, [0062]) stacked on the second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B);
first vias (through-vias 62, Fig. 2B) in the buffer die (base die 41, Fig. 2B), the first passivation film (front side passivation layer 61 on base die 41, Fig. 2B), the first memory die (lower core die 43a, Fig. 2B), the second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B), and the second memory die (intermediate core die 43b, Fig. 2B).
Kim-612, however, does not disclose second vias for alignment and therefore, does not teach
second vias in the first memory die and the second memory die, respectively, and
wherein the second vias are configured to indicate an alignment between the first memory die and the second memory die.
Ma, on the other hand, teaches a three-dimensional chip stack (Figs. 1-2. [0004]-[0006]), wherein the three dimensional chip stack comprises a first die (second chip unit 200, Figs. 1-2, [0070]), a second passivation film (first top dielectric layer 102, Figs. 1-2, [0070]) on the first die, and a second die (first chip unit 100, Figs. 1-2, [0070]) on the second passivation film (first top dielectric layer 102, Figs. 1-2, [0070]), and first vias (the vias through which the first bonding structure 104 and second bonding structure 204 and their extensions into the first and second chip units go through, see Illustrative Fig. 1, which is an annotated version of Ma’s Fig. 1, [0070]). Ma further teaches
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second vias (first conductive hole 108 ([0087]) and third conductive hole 206 ([0088]), which are labeled as second vias in Illustrative Fig. 1) in the first memory die (second chip unit 200, Illustrative Fig. 1) and the second memory die (first chip unit 100, Illustrative Fig. 1), respectively, and
wherein the second vias (second vias, Illustrative Fig. 1) are configured to indicate an alignment between the first memory die (second chip unit 200, Illustrative Fig. 1) and the second memory die (first chip unit 100, Illustrative Fig. 1: second vias are connected to first test structure 103 and the second test structure 203 (Illustrative Fig. 1), and “The test structure is used to form a plate capacitor with the test structure on the oppositely arranged chip unit, and the capacitance value of the plate capacitor is used to reflect the alignment of the bonding structure of the two oppositely arranged chip units.”, [0031]).
Ma further discloses that “no matter how advanced the alignment technology is, alignment deviations in hybrid bonding are inevitable” ([0067]), and misalignments might lead the metal atoms to diffuse into dielectric layers and cause leakage current ([0073]). Ma discloses that including the second vias as taught by Ma allows “more accurately test[ing] the bonding alignment of the three-dimensional chip” and helps to avoid the production of three-dimensional chips with excessive leakage current ([0073]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that memory dies of Kim-612 are also bonded by hybrid bonding method (see Figs. 7A-B, [0061]), and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include second vias in the semiconductor package of Kim-612, as taught by Ma, to be able to measure the alignment accuracy of the memory dies to minimize the manufacturing of devices with high leakage current.
Regarding claim 2, while Kim-612 in view of Ma teaches the semiconductor package of claim 1,
Kim-612 is silent on second vias and therefore does not teach that the second vias are not in the second passivation film.
Ma, on the other hand, teaches that the second vias (second vias, Illustrative Fig. 1) are not in the second passivation film (corresponding to first top dielectric layer 102 and second top dielectric layer 202, Fig.1, [0070]).
Ma further discloses that the second passivation layer (corresponding to first top dielectric layer 102 and second top dielectric layer 202, Fig.1) between the second vias provides the vertical distance d (Figs. 1-2, [0099]) for the capacitor formed between the test structures 103 and 203. A person of ordinary skill in the art before the effective filing date of the claimed invention would understand that, in this fashion, the distance d will be fixed to the thickness of the second passivation layer, which can be controlled independent of the memory dies, and accordingly the capacitance value between test structure will depend only on the lateral alignment. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the second vias in the semiconductor package of Kim-612 in view of Ma such that second vias are not in the second passivation film, as taught by Ma, which would provide the benefit of forming a capacitor to measure the lateral alignment between memory dies with a vertical distance of the capacitor determined by the thickness of the passivation layer.
Regarding claim 3, Kim-612 in view of Ma teaches the semiconductor package of claim 1, wherein
The combination of Kim-612 and Ma (see claim 1 rejection for the combination) further teaches that
the second vias (second vias of Illustrative Fig. 1 incorporated in Kim-612’s semiconductor package) include a conductive material ([0087]-[0089]: first conductive hole 108, first test structure 103, second test structure 203, and third conductive hole 206 are all conductive), and
the second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B) includes an insulating material ([0053], [0057] and [0058]: all are insulating materials).
Regarding claim 4, Kim-612 in view of Ma teaches the semiconductor package of claim 3, wherein
the combination of Kim-612 and Ma (see claim 1 rejection for the combination) further teaches that the alignment between the first memory die (lower core die 43a, Fig. 2B) and the second memory die (intermediate core die 43b, Fig. 2B) corresponds to a capacitance (Ma, [0074]: “The difference in capacitance value can reflect the alignment of the two relatively arranged test structures, and the alignment of the two relatively arranged test structures can further reflect the alignment of the two bonded chip units, so as to accurately test the misalignment of the bonding connection between the chip units of the three-dimensional chip.”) that is based on the second vias (second vias of Illustrative Fig. 1 incorporated in Kim-612’s semiconductor package).
Regarding claim 6, Kim-612 in view of Ma teaches the semiconductor package of claim 4, wherein
the combination of Kim-612 and Ma (see claim 1 rejection for the combination) further teaches the capacitance is based on a region of overlap between the second via (second via in the second chip unit 200 of Illustrative Fig. 1) in the first memory die (second chip unit 200 of Ma corresponding to the first memory die of Kim-612 in view of Ma, Illustrative Fig. 1) and the second via (second via in the first chip unit 100 of Illustrative Fig. 1) in the second memory die (first chip unit 100 of Ma corresponding to the second memory die of Kim-612 in view of Ma; Ma,[0072]: “If the area deviation caused by this shift is ΔS, then the facing area of the first test structure 103 and the second test structure 203 is S0 - ΔS. When the area of the test structure 203 changes, the capacitance value between the first test structure 103 and the second test structure 203 will also change” (see Ma’s Figs. 1-2). Because the test structures are attached to the second vias, the capacitance value is also related to the areal overlap between second vias (see Ma’s Figs. 1-2)).
Regarding claim 7, Kim-612 in view of Ma teaches the semiconductor package of claim 4, wherein
the combination of Kim-612 and Ma further teaches that a value of the capacitance indicates the alignment (“The difference in capacitance value can reflect the alignment of the two relatively arranged test structures”, and therefore the capacitance value indicates the alignment).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim-612 (US 2023/0139612 A1) in view of Ma (CN 117198907 A) as applied to claims 1-4 and 6-7 above, and further in view of Bohl (Bohl, S.; Weikert, S.; Wegener, K. Enhancing Signal Quality of Capacitive Displacement Measurements in Machine Tool Environments. J. Manuf. Mater. Process. 2019, 3, 76. https://doi.org/10.3390/jmmp3030076).
Regarding claim 5, while Kim-612 in view of Ma teaches the semiconductor package of claim 4,
Kim-612 nor Ma are silent about the circuit for measuring the capacitance between the second vias and therefore do not teach that
the second via in the first memory die is electrically connected to a first capacitor,
the second via in the second memory die is electrically connected to a second capacitor, and
the first and second capacitors are configured to measure the capacitance.
Bohl on the other hand teaches a full capacitor bridge circuit (Fig. 5a; page 6, section 1.4.3) for measuring capacitive displacements (Abstract), wherein the circuit comprises connecting the measured capacitor (C1 in Fig. 5a) to a first capacitor (C2) and a second capacitor (C4), wherein the capacitors C2 and C4 are configured to measure the capacitance of C1.
Using full capacitor bridge circuits is a common method for measuring capacitance changes caused by displacements of capacitor plates. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply the full capacitator bridge circuit of Bohl as the sensing circuit in the semiconductor package of Kim-612 in view of Ma to be able to measure the capacitance change as the memory chips are aligned. Accordingly, it would have been obvious to a person of ordinary skill in the art to integrate the full capacitor bridge circuit with the semiconductor package of Kim-612 and Ma in a way that
the second via (which connects to one of the plates of the measured capacitor, see Ma, Figs. 1-2) in the first memory die is electrically connected to a first capacitor (one of the capacitors in the full capacitor bridge circuit),
the second via (which connects to the other plate of the measured capacitor, see Ma, Figs. 1-2) in the second memory die is electrically connected to a second capacitor (another capacitor in the full capacitor bridge circuit), and
the first and second capacitors are configured to measure the capacitance.
Thus, the combination of Kim-612, Ma and Bohl meets all the limitations of claim 5.
Claim 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-612 (US 2023/0139612 A1) in view of Ma (CN 117198907 A) as applied to claims 1-4 and 6-7 above, and further in view of Kim-393 (US 2020/0411393 A1).
Regarding claim 8, Kim-612 in view of Ma teaches the semiconductor package of claim 1, wherein
Kim-612 further teaches that
the second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B) includes a second lower insulating film (bonding insulating layer 67, Fig. 2B) on the first memory die (lower core die 43a, Fig. 2B) and a second upper insulating film (front side passivation layer 61, Fig. 2B) on the second lower insulating film (bonding insulating layer 67, Fig. 2B).
Kim-612 and Ma do not teach that
the second via in the second memory die is in the second upper insulating film.
Kim-393, on the other hand, teaches a semiconductor package (chip-stacked semiconductor package 1000, Fig. 11, [0102]) with capacitive alignment structures (detection pad group MPD, Fig. 11, [0108]), wherein
the second via (vias of MPD) in the second die (second chip 200, Fig. 11, [0119]) is in the second upper insulating film (passivation layer 224, Fig. 11, [0120]; passivation layer 224 is analogous to the front side passivation layer 61 of Kim 612).
Kim-393 further discloses that the vertical distance between the capacitor plates (detection pads 16 and 26, Figs. 5A-C, [0070]) formed at the ends of second vias determines the reference capacitance value for the alignment (Figs. 5A-C, [0070]-[0072]), and the capacitor value between the plates increases as the vertical distance d between the plates decreases ([0070]-[0072]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that decreasing the vertical distance d leads to increasing capacitor value, which in turn increases the measurement accuracy. Relevantly, Ma discloses that the vertical distance d (Figs. 1-2, [0099]) for the capacitor is set to be equal to the thickness of the second passivation film. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the first test structure 103 of Kim-612 in view of Ma in the second upper insulating film (front side passivation layer 61, Fig. 2B)by extending the second vias into the second upper insulating layer, as taught by Kim-393, in the semiconductor package of Kim-612 in view Ma, which would reduce vertical distance d and improve the measurement accuracy, while determining the vertical distance d by the thickness of the lower second lower insulating film.
Thus, the combination of Kim-612, Ma, and Kim-393 meets all the limitations of claim 8.
Regarding claim 9, Kim-612 in views of Ma and Kim-393 teaches the semiconductor package of claim 8, wherein
the combination of Kim-612, Ma, and Kim-393 further teaches that the second vias (second vias of Illustrative Fig. 1 incorporated in the semiconductor package (Figs. 2A-B of Kim-612) of Kim-612 in view of Ma) are not in the second lower insulating film (bonding insulating layer 67, Fig. 2B).
Regarding claim 10, Kim-612 in views of Ma and Kim-393 teaches the semiconductor package of claim 8, wherein
Kim-612 further teaches that
the second lower insulating film (bonding insulating layer 67, Fig. 2B) includes a first element (nitrogen, [0038]: “silicon nitride”) and a second element (silicon, [0034]: “silicon nitride”),
the second upper insulating film (front side passivation layer 61, Fig. 2B) includes the first element (nitrogen, [0034]: “polyimide”) and a third element (carbon, [0034]: “polyimide”), and
wherein the third element (carbon) is a different material from the second element (silicon).
Regarding claim 11, Kim-612 in views of Ma and Kim-393 teaches the semiconductor package of claim 8, wherein
the combination of Kim-612, Ma, and Kim-393 further teaches that the first via (bumps 71 and the support patterns 73 of the first via, Figs. 2A-B) in the first passivation film (front side passivation layer 61 on base die 41, Figs. 2A-B) has a different width (see Ma’s Fig. 1: the first structure is wider than the width of the connection structures 104/204) from the second via (width of the second vias of Illustrative Fig. 1 incorporated with the semiconductor package of Kim-612 has the width of through vias 62 of Kim-612) in the second upper insulating film (front side passivation layer 61, Fig. 2B).
Regarding claim 12, while Kim-612 in views of Ma and Kim-393 teaches the semiconductor package of claim 11, wherein
the combination of Kim-612, Ma and Kim-393 (see claim 11 rejection above) teaches that the first via in the first passivation film (bumps 71 and the support patterns 73 of the first via, Figs. 2A-B) has a larger width than the second via in the second upper insulating film (width of the second vias of Illustrative Fig. 1 incorporated with the semiconductor package of Kim-612 has the width of through vias 62 of Kim-612).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim-612 (US 2023/0139612 A1) in views of Ma (CN 117198907 A), Kim-393 (US 2020/0411393 A1), and Bohl (Bohl, S.; Weikert, S.; Wegener, K. Enhancing Signal Quality of Capacitive Displacement Measurements in Machine Tool Environments. J. Manuf. Mater. Process. 2019, 3, 76. https://doi.org/10.3390/jmmp3030076).
Regarding claim 20, Kim-612 teaches a semiconductor package (semiconductor module 100, Fig. 1, [0021]) comprising:
a package substrate (interposer 10, Fig. 1: the Examiner notes that the interposer was wrongly labeled as 20 in Fig. 1, please see the description in [0021]);
a first semiconductor chip (logic device 20, Fig. 1, [0021]) mounted on the package substrate (interposer 10, Fig. 1); and
a second semiconductor chip (semiconductor die stack 40 on the left, Fig. 1, [0021]) mounted on the package substrate (interposer 10, Fig. 1) and spaced apart from the first semiconductor chip (logic device 20, Fig. 1),
wherein the second semiconductor chip (semiconductor die stack 40 on the left, Fig. 1) includes a buffer die (base die 41, Fig. 2B, [0022]), a first passivation film (front side passivation layer 61 on base die 41, Fig. 2B, [0032]) on the buffer die (base die 41, Fig. 2B), a first memory die (lower core die 43a, Fig. 2B, [0041]: “The semiconductor substrate 60 of the core dies 43a-43c may include a silicon wafer and memory circuits that are formed on the silicon wafer.”) stacked on the first passivation film (front side passivation layer 61 on base die 41, Fig. 2B), a second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a , Fig. 2B, [0032]) on the first memory die (lower core die 43a, Fig. 2B), a second memory die (intermediate core die 43b, Fig. 2B, [0062]) stacked on the second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a , Fig. 2B), first vias (comprising through-vias 62, vias of bumps 71 and seed layer 64, Fig. 2B, [0036]) in the buffer die (base die 41, Fig. 2B), the first passivation film (front side passivation layer 61 on base die 41, Fig. 2B), the first memory die (lower core die 43a, Fig. 2B), the second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a , Fig. 2B), and the second memory die (intermediate core die 43b, Fig. 2B),
wherein the second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B) includes a second lower insulating film (bonding insulating layer 67, Fig. 2B) on the first memory die (lower core die 43a, Fig. 2B) and a second upper insulating film (front side passivation layer 61, Fig. 2B) on the second lower insulating film (bonding insulating layer 67, Fig. 2B), and
wherein the second passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B) includes an insulating material ([0053], [0057] and [0058]: all are silicon nitride (SiN)).
Kim-612, however, does not disclose second vias for alignment and therefore, does not teach
second vias in the first memory die and the second memory die;
wherein the second vias are in the second upper insulating film and are not in the second lower insulating film,
wherein the second vias include a conductive material,
wherein the second via in the first memory die is electrically connected to a first capacitor,
wherein the second via in the second memory die is electrically connected to a second capacitor, and
wherein a capacitance that corresponds to the first and second capacitors corresponds to an alignment between the first memory die and the second memory die.
Ma, on the other hand, teaches a three-dimensional chip stack (Figs. 1-2. [0004]-[0006]), wherein the three dimensional chip stack comprises a first die (second chip unit 200, Figs. 1-2, [0070]), a second passivation film (first top dielectric layer 102, Figs. 1-2, [0070]) on the first die, and a second die (first chip unit 100, Figs. 1-2, [0070]) on the second passivation film (first top dielectric layer 102, Figs. 1-2, [0070]), and first vias (the vias through which the first bonding structure 104 and second bonding structure 204 and their extensions into the first and second chip units go through, see Illustrative Fig. 1, which is an annotated version of Ma’s Fig. 1, [0070]). Ma further teaches
second vias (first conductive hole 108 ([0087]) and third conductive hole 206 ([0088]), which are labeled as second vias in Illustrative Fig. 1) in the first memory die (second chip unit 200, Illustrative Fig. 1) and the second memory die (first chip unit 100, Illustrative Fig. 1);
wherein the second vias (second vias, Illustrative Fig. 1) are not in the second lower insulating film (corresponding to first top dielectric layer 102 and second top dielectric layer 202, which is analogous to the second passivation layer of Kim-612, Fig.1, [0070]),
wherein the second vias (second vias, Illustrative Fig. 1) include a conductive material ([0087]-[0089]: first conductive hole 108, first test structure 103, second test structure 203, and third conductive hole 206 are all conductive).
Ma further discloses that “no matter how advanced the alignment technology is, alignment deviations in hybrid bonding are inevitable” ([0067]), and misalignments might lead the metal atoms to diffuse into dielectric layers and cause leakage current ([0073]). Ma discloses that including the second vias as taught by Ma allows “more accurately test[ing] the bonding alignment of the three-dimensional chip” and helps to avoid the production of three-dimensional chips with excessive leakage current ([0073]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that memory dies of Kim-612 are also bonded by hybrid bonding method (see Figs. 7A-B, [0061]), and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include second vias in the semiconductor package of Kim-612, as taught by Ma, to be able to measure the alignment accuracy of the memory dies to minimize the manufacturing of devices with high leakage current. Thus, the combination of Kim-612 and Ma teaches that
second vias in the first memory die and the second memory die;
wherein the second vias are not in the second lower insulating film,
wherein the second vias include a conductive material.
Kim-612 and Ma, however, do not teach that
the second vias are in the second upper insulating film,
the second via in the first memory die is electrically connected to a first capacitor,
the second via in the second memory die is electrically connected to a second capacitor, and
a capacitance that corresponds to the first and second capacitors corresponds to an alignment between the first memory die and the second memory die.
Kim-393, on the other hand, teaches a semiconductor package (chip-stacked semiconductor package 1000, Fig. 11, [0102]) with capacitive alignment structures (detection pad group MPD, Fig. 11, [0108]), wherein
the second vias (vias of MPD) in the second upper insulating film (passivation layer 224, Fig. 11, [0120]; passivation layer 224 is analogous to the front side passivation layer 61 of Kim 612).
Kim-393 further discloses that the vertical distance between the capacitor plates (detection pads 16 and 26, Figs. 5A-C, [0070]) formed at the ends of second vias determines the reference capacitance value for the alignment (Figs. 5A-C, [0070]-[0072]), and the capacitor value between the plates increases as the vertical distance d between the plates decreases ([0070]-[0072]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that decreasing the vertical distance d leads to increasing capacitor value, which in turn increases the measurement accuracy. Relevantly, Ma discloses that the vertical distance d (Figs. 1-2, [0099]) for the capacitor is set to be equal to the thickness of the second passivation film. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the first test structure 103 of Kim-612 in view of Ma in the second upper insulating film (front side passivation layer 61, Fig. 2B) by extending the second vias into the second upper insulating layer, as taught by Kim-393, in the semiconductor package of Kim-612 in view Ma, which would reduce vertical distance d and improve the measurement accuracy, while determining the vertical distance d by the thickness of the lower second lower insulating film.
Thus, the combination of Kim-612, Ma, and Kim-393 teaches that
the second vias are in the second upper insulating film
Kim-612, Ma, and Kim-393, however, do not teach that
the second via in the first memory die is electrically connected to a first capacitor,
the second via in the second memory die is electrically connected to a second capacitor, and
a capacitance that corresponds to the first and second capacitors corresponds to an alignment between the first memory die and the second memory die.
Bohl on the other hand teaches a full capacitor bridge circuit (Fig. 5a; page 6, section 1.4.3) for measuring capacitive displacements (Abstract), wherein the circuit comprises connecting the measured capacitor (C1 in Fig. 5a) to a first capacitor (C2) and a second capacitor (C4), wherein the capacitors C2 and C4 are configured to measure the capacitance of C1.
Using full capacitor bridge circuits is a common method for measuring capacitance changes caused by displacements of capacitor plates. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply the full capacitator bridge circuit of Bohl as the sensing circuit in the semiconductor package of Kim-612 in views of Ma and Kim-393 to be able to measure the capacitance change as the memory chips are aligned. Accordingly, it would have been obvious to a person of ordinary skill in the art to integrate the full capacitor bridge circuit with the semiconductor package of Kim-612, Ma, and Kim-393 in a way that
the second via (which connects to one of the plates of the measured capacitor, see Ma, Figs. 1-2) in the first memory die is electrically connected to a first capacitor (one of the capacitors in the full capacitor bridge circuit),
the second via (which connects to the other plate of the measured capacitor, see Ma, Figs. 1-2) in the second memory die is electrically connected to a second capacitor (another capacitor in the full capacitor bridge circuit), and
a capacitance that corresponds to the first and second capacitors (in a bridge circuit first and second capacitor values are selected according to the corresponds to an alignment between the first memory die and the second memory die (Ma, [0074]: “The difference in capacitance value can reflect the alignment of the two relatively arranged test structures, and the alignment of the two relatively arranged test structures can further reflect the alignment of the two bonded chip units, so as to accurately test the misalignment of the bonding connection between the chip units of the three-dimensional chip.”).
Thus, the combination of Kim-612, Ma, Kim-393, and Bohl meets all the limitations of claim 20.
Claims 21-22 and 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-612 (US 2023/0139612 A1) in view of Ma (CN 117198907 A).
Regarding claim 21, Kim-612 teaches a semiconductor package (semiconductor module 100, Fig. 1, [0021]) comprising:
a package substrate (interposer 10, Fig. 1: the Examiner notes that the interposer was wrongly labeled as 20 in Fig. 1, please see the description in [0021]); and
a first semiconductor chip (logic device 20, Fig. 1, [0021]) and a second semiconductor chip (semiconductor die stack 40 on the left, Fig. 1, [0021]) that are on the package substrate (interposer 10, Fig. 1),
wherein the second semiconductor chip (semiconductor die stack 40 on the left, Fig. 1) comprises:
a first memory die (lower core die 43a, Figs. 2A-B, [0041]: “The semiconductor substrate 60 of the core dies 43a-43c may include a silicon wafer and memory circuits that are formed on the silicon wafer.”);
a second memory die (intermediate core die 43b, Figs. 2A-B, [0062]) that is on the first memory die (lower core die 43a, Figs. 2A-B);
a passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B, [0032]) that is between the first memory die (lower core die 43a, Fig. 2B) and the second memory die (intermediate core die 43b, Fig. 2B);
a first via (comprising through-vias 62, vias of bumps 71 and seed layer 64, Fig. 2B, [0036]) that extends through the passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B) and the second memory die (intermediate core die 43b, Fig. 2B);
Kim-612, however, does not teach
a second via that is in the first memory die; and
a third via that is in the second memory die,
wherein a lower surface of the third via overlaps an upper surface of the second via, and
wherein the passivation film is between the lower surface of the third via and the upper surface of the second via.
Ma, on the other hand, teaches a three-dimensional chip stack (Figs. 1-2, [0004]-[0006]), wherein the three dimensional chip stack comprises a first die (second chip unit 200, Figs. 1-2, [0070]), a passivation film (comprising first top dielectric layer 102 and second top dielectric layer 202, Figs. 1-2, [0070]) on the first die, and a second die (first chip unit 100, Figs. 1-2, [0070]) on the passivation film (comprising first top dielectric layer 102 and second top dielectric layer 202, Figs. 1-2), and first vias (the vias through which the first bonding structure 104 and second bonding structure 204 and their extensions into the first and second chip units go through, see Illustrative Fig. 2, which is an annotated version of Ma’s Fig. 1, [0070]). Ma further teaches
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a second via (second test structure 203 ([0084] and third conductive hole 206 ([0088]), which are labeled as second via in Illustrative Fig. 2) that is in the first memory die (second chip unit 200, Illustrative Fig. 2);
a third via (first conductive hole 108 ([0087]) and first test structure 103 ([0084]), which are labeled as third via in Illustrative Fig. 2) that is in the second memory die (first chip unit 100, Illustrative Fig. 2);
wherein a lower surface of the third via (lower surface of the first test structure 103, Illustrative Fig. 2) overlaps an upper surface of the second via (upper surface of the second test structure 203, Illustrative Fig. 2), and
wherein the passivation film (first top dielectric layer 102 and second top dielectric layer 202, Illustrative Fig. 2) is between the lower surface of the third via (lower surface of the first test structure 103, Illustrative Fig. 2) and the upper surface of the second via (upper surface of the second test structure 203, Illustrative Fig. 2).
Ma further discloses that “no matter how advanced the alignment technology is, alignment deviations in hybrid bonding are inevitable” ([0067]), and misalignments might lead the metal atoms to diffuse into dielectric layers and cause leakage current ([0073]). Ma discloses that including a capacitor formed by overlapping second and third vias, as taught by Ma, allows “more accurately test[ing] the bonding alignment of the three-dimensional chip” and helps to avoid the production of three-dimensional chips with excessive leakage current ([0073]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that memory dies of Kim-612 are also bonded by hybrid bonding method (see Figs. 7A-B, [0061]), and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include second and third vias in the semiconductor package of Kim-612, as taught by Ma, to be able to measure the alignment accuracy of the memory dies to minimize the manufacturing of devices with high leakage current. Thus the combination of Kim-612 and Ma meets all the limitations of claim 21.
Regarding claim 22, Kim-612 in view of Ma teaches the semiconductor package of Claim 21, wherein
Kim-612 further teaches that
the passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B) comprises an upper layer (front side passivation layer 61, Fig. 2B) and a lower layer (bonding insulating layer 67, Fig. 2B).
Kim-612 is, however, silent of on the second and third vias, and therefore does not teach that
the second via and the third via are not in the lower layer.
The combination of Kim-612 and Ma (see claim 21 rejection above, on the other hand, teaches that the second via and third via (second and third vias of Ma (Illustrative Fig. 1) incorporated in the semiconductor package of Kim-612 (Kim-612’s Figs. 2A-B as taught by Ma) do not enter the passivation layer. Therefore, the combination of Kim-612 and Ma further teaches that
the second via and the third via are not in the lower layer.
Regarding claim 26, Kim-612 in view of Ma teaches the semiconductor package of Claim 21, wherein
Kim-612 further teaches that
the first via includes a conductive material (comprising through-vias 62, vias of bumps 71 and seed layer 64, Fig. 2B, [0035]-[0036]: all conductive),
wherein the passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Fig. 2B) includes an insulating material ([0053], [0057] and [0058]: all are insulating materials).
Kim-612, however, is silent on second and third vias and therefore does not teach that
the second via and the third via include a conductive material,
the second via, the passivation film, and the third via collectively provide a metal insulator metal (MIM) structure, and
wherein a capacitance corresponding to the MIM structure is based on an amount of overlap between the second via and the third via.
The combination of Kim-612 and Ma (see claim 21 rejection above), on the other hand, teaches that
the second via (Ma’s second test structure 203 and third conductive hole 206, Fig. 1) and the third via (Ma’s first test structure 103 and first conductive hole 108, Fig. 1) include a conductive material ([0070]: all conductive material),
the second via (Ma’s second test structure 203 and third conductive hole 206, Fig. 1), the passivation film (the passivation film in between second and third vias), and the third via (Ma’s first test structure 103 and first conductive hole 108, Fig. 1) collectively provide a metal insulator metal (MIM) structure (Ma, [0070]: “The first test structure 103 and the second test structure 203 can be made of metallic materials” and “The oppositely arranged first test structures 103 and second test structures 203 can form a plate capacitor”. Therefore, the structure is a MIM capacitor structure.), and
wherein a capacitance corresponding to the MIM structure ([0070]: “The oppositely arranged first test structures 103 and second test structures 203 can form a plate capacitor”) is based on an amount of overlap between the second via (second test structure 203 and third conductive hole 206, Figs. 1-2) and the third via (first test structure 103 and first conductive hole 108, Figs. 1-2, [0070]: “The capacitance value of the plate capacitor can reflect the bonding alignment of the bonding structure between chip units” and [0071]: “The design capacitance is the capacitance when the projections of the test structure on the bonding surface completely overlap”. Therefore, as illustrated in Figs. 1-2, the capacitance depends on the amount od overlap between the second and third vias.).
Thus, the combination of Kim-612 and Ma teaches all the limitations of claim 26.
Regarding claim 27, Kim-612 in view of Ma teaches the semiconductor package of Claim 21, wherein
Kim-612 further teaches that the first via (comprising through-vias 62, vias of bumps 71 and seed layer 64, Figs. 2A-B) is part of a via structure that extends through the passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Figs. 2A-B) and the second memory die (intermediate core die 43b, Figs. 2A-B: the through vias 62 go completely through the intermediate core die 43b).
Claim 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim-612 (US 2023/0139612 A1) in view of Ma (CN 117198907 A) as applied to claims 21-22 and 26-27 above, and further in view of Kim-393 (US 2020/0411393 A1).
Regarding claim 23, while Kim-612 in view of Ma teaches the semiconductor package of Claim 22,
neither Kim-612 nor Ma teaches that the third via is in the upper layer.
Kim-393, on the other hand, teaches a semiconductor package (chip-stacked semiconductor package 1000, Fig. 11, [0102]) with capacitive alignment structures (detection pad group MPD, Fig. 11, [0108]) comprising a second via (comprising second detection pad 170b and attached TSV 130, Fig. 11, [0103]) and a third via (second detection pad 170b and attached via, Fig. 11, [0107]),
wherein the third via (second detection pad 170b and attached via, Fig. 11) is in the upper layer (passivation layer 224, Fig. 11).
Kim-393 further discloses that the vertical distance between the capacitor plates (detection pads 16 and 26, Figs. 5A-C, [0070]) formed by second via and third via determines the reference capacitance value for the alignment (Figs. 5A-C, [0070]-[0072]), and the capacitor value between the plates increases as the vertical distance d between the plates decreases ([0070]-[0072]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that decreasing the vertical distance d leads to increasing capacitor value, which in turn increases the measurement accuracy. Relevantly, Ma discloses that the vertical distance d (Figs. 1-2, [0099]) for the capacitor is set to be equal to the thickness of the passivation film. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the first test structure 103 of Kim-612 in view of Ma in the upper layer (front side passivation layer 61, Fig. 2B) by extending the third via into the second upper insulating layer, as taught by Kim-393, in the semiconductor package of Kim-612 in view Ma, which would reduce vertical distance d and improve the measurement accuracy, while determining the vertical distance d by the thickness of the lower second lower insulating film. Thus, the combination of Kim-612, Ma, and Kim-393 meets all the limitations of claim 23.
Regarding claim 24, Kim-612 in views of Ma and Kim-393 teaches the semiconductor package of Claim 23, wherein
The combination of Kim-612, Ma, and Kim-393 further teaches that a portion of the third via (first conductive hole 108 of Ma as the portion of the third via (Ma’s Fig. 1) incorporated into the semiconductor package of Kim-612 (see claim 21 rejection above), and further modified by Kim -393 (see claim 23 rejection above)) that is in the upper layer (front side passivation layer 61, Fig. 2B) is narrower than a portion of the first via (bumps 71 and seed layer 64 as a portion of the first via, Kim-612’s Fig. 2B) that is in the passivation film (comprising back side passivation layer 69, bonding insulating layer 67, and front side passivation layer 61 on the top surface of the lower core die 43a, Kim-612’s Fig. 2B).
Regarding claim 25, Kim-612 in views of Ma and Kim-393 teaches the semiconductor package of Claim 24, wherein
Kim 612 further teaches that the portion of the first via (bumps 71 and seed layer 64 as the portion of the first via, Kim-612’s Figs. 2A-B) is wider than another portion of the first via (through-vias 62 as the another portion of the first via, Figs. 2A-B) that is in the first memory die (lower core die 43a, Figs. 2A-B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yokomizo (US 2022/0285234 A1) teaches a stack of memory dies with capacitive alignment structures, which is relevant to all claims.
Lee (US 2020/0350258 A1) a stack of dies with capacitive alignment structures, which is relevant to all claims.
Li (US 2022/0285233 A1) teaches a stack of memory dies with capacitive alignment structures, which is relevant to all claims.
Kim (US 2018/0006006 A1) teaches a package comprising a stack of memory dies and an adjacent semiconductor die, which is relevant to claims 1, 20, and 21.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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