DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed by Applicant on 12/29/2025. This action is made FINAL.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding Applicant’s statement that “there is no apparent reason why one of ordinary skill in the art before the effective filing date of the present application would have combined the art of record to arrive at the claimed embodiment of amended claim 1. Thus, this claim would not have been obvious over the art of record before the effective filing date of the present application. Accordingly, Applicant respectfully submits that claim 1 is patentable over the art of record, and respectfully requests that this claim be allowed,” the reason for combination of references was given in page 4 of the office action mailed on 09/29/2025.
Regarding Applicant’s statement that “the cited portions of Kim, Hong, and Li do not appear to mention, disclose, or propose the configuration of the timing controller that transmits to the data driver an identification signal for identifying a transmission time point of the first image data when lock of the clock signal is completed,” exemplary claim 1 resumes transmission when lock of the clock signal is completed, AND NOT identifying a transmission time point of the first image data when lock of the clock signal is completed. Exemplary claim 1 is not worded in a similar manner as argued by the Applicant. The difference between Applicant’s argument and the claimed limitation can be apparent from at least that the claim does not link identifying a transmission time point to when lock of the clock signal is completed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Publication number: US 2023/0215317) in view of Hong et al (Publication number: US 2023/0014733) in view of Ichikura (Publication number: US 2022/0199048).
Consider Claim 1, Kim shows a display device (see figure 6), comprising:
(a) A display panel (see figure 6; and paragraph 47); (Read as display panel 150).
(b) A timing controller configured to output image data (see figure 6; and paragraph 47); (Read as timing controller 120).
(c) A data driver configured to receive the image data from the timing controller (see figure 6; paragraph 47); (read as data driver 140); to divide the received image data into first image data and second image data, and to alternately output the first image data and the second image data (see figure 6; paragraphs 40-44, and 58-60); (The image supplier 110 (a set or a host system) may output various driving signals together with an image data signal supplied from an exterior thereof or an image data signal. he plurality of data drivers 140a to 140d may each include a first lock signal terminal LOCK1 and a second lock signal terminal LOCK2 in order to transmit and receive lock signals).
(d) A switching circuit configured to receive the first image data and the second image data from the data driver, to supply the first image data to sub-pixels of a first group in the display panel, and to supply the second image data to sub-pixels of a second group in the display panel (see figure 6; and paragraphs 56-57); (The plurality of data drivers 140a to 140d may have communication interfaces, and may receive signals including a clock signal, a data signal, etc. output from the timing controller 120 in the form of a data packet via the communication interfaces).
(e) Wherein the timing controller is configured to: identify that a lock fail of a clock signal has occurred in the data driver upon receiving a first control signal from the data driver while transmitting the image data for one frame; and upon identifying the lock fail, to interrupt transmission of the image data and to transmit a signal to the data driver to lock the clock signal (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
(f) Resume transmission of the image data when lock of the clock signal is completed, and to transmit to the data driver an identification signal for identifying a transmission time point of the first image data (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
However, Kim does not specifically show transmitting a clock training signal to the data driver.
In the same field of endeavor, Hong et al shows transmitting a clock training signal to the data driver (see paragraph 25).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the clock training signal of Hong et al into the teachings of Kim in order to restore the configuration of the environment for the high-speed communication (see Hong et al; paragraph 25).
However, Kim in view of Hong et al do not specifically show that the switching circuit comprises a demultiplexer.
In related art, Ichikura shows that the switching circuit comprises a demultiplexer (see figure 2; and paragraphs 47-50); (Please refer to the DMX block in Ichikura).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the switching circuit of Ichikura into the driving circuit of Kim in view of Hong et al in order to select between data lined on the basis of connection control signals (see Ichikura; paragraph 50).
Consider Claim 13, Kim shows a method for driving a display device (see figure 6), the method comprising:
(a) Outputting, by a timing controller, image data; receiving, by a data driver, the image data from the timing controller to divide the received image data into first image data and second image data; alternately outputting, by the data driver, the first image data and the second image data (see figure 6; paragraphs 40-44, and 58-60); (The image supplier 110 (a set or a host system) may output various driving signals together with an image data signal supplied from an exterior thereof or an image data signal. he plurality of data drivers 140a to 140d may each include a first lock signal terminal LOCK1 and a second lock signal terminal LOCK2 in order to transmit and receive lock signals).
(b) Receiving, by a switching circuit, the first image data and the second image data from the data driver, to supply the first image data to sub-pixels of a first group in a display panel, and to supply the second image data to sub-pixels of a second group in the panel (see figure 6; and paragraphs 56-57); (The plurality of data drivers 140a to 140d may have communication interfaces, and may receive signals including a clock signal, a data signal, etc. output from the timing controller 120 in the form of a data packet via the communication interfaces).
(c) Identifying, by the timing controller, that a lock fail of a clock signal has occurred in the data driver upon receiving a first control signal from the data driver while transmitting the image data for one frame; upon identifying the lock fail by the timing controller (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
(d) Interrupting transmission of the image data and transmitting a signal to the data driver to lock the clock signal (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
(e) Resuming, by the timing controller, transmission of the image data when lock of the clock signal is completed, and transmitting to the data driver an identification signal for identifying a transmission time point of the first image data (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
However, Kim does not specifically show transmitting a clock training signal to the data driver.
In the same field of endeavor, Hong et al shows transmitting a clock training signal to the data driver (see paragraph 25).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the clock training signal of Hong et al into the teachings of Kim in order to restore the configuration of the environment for the high-speed communication (see Hong et al; paragraph 25).
However, Kim in view of Hong et al do not specifically show that the switching circuit comprises a demultiplexer.
In related art, Ichikura shows that the switching circuit comprises a demultiplexer (see figure 2; and paragraphs 47-50); (Please refer to the DMX block in Ichikura).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the switching circuit of Ichikura into the driving circuit of Kim in view of Hong et al in order to select between data lined on the basis of connection control signals (see Ichikura; paragraph 50).
Claims 2-4 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Publication number: US 2023/0215317) in view of Hong et al (Publication number: US 2023/0014733) and Ichikura in view of Li et al (Publication number: US 2022/0036791).
Consider Claims 2 and 14, Kim in view of Hong et al, and Ichikura do not specifically show sub-pixels of the first group are odd sub-pixels of a plurality of sub-pixels in the display panel that are arranged in odd columns, and wherein the sub-pixels of the second group are even sub-pixels of the plurality of sub-pixels that are arranged in even columns.
In related art, Li et al shows sub-pixels of the first group are odd sub-pixels of a plurality of sub-pixels in the display panel that are arranged in odd columns, and wherein the sub-pixels of the second group are even sub-pixels of the plurality of sub-pixels that are arranged in even columns (see figures 3 and 7; paragraphs 67 and 75).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Li et al into the teaching of Kim and Hong et al, and Ichikura in order to extend service life (see Li et al; paragraphs 4-7).
Consider Claims 3 and 15, Kim shows that the timing controller is configured to output the first image data when resuming transmission of the image data (see figure 6; paragraphs 40-44, and 58-60); (The image supplier 110 (a set or a host system) may output various driving signals together with an image data signal supplied from an exterior thereof or an image data signal. he plurality of data drivers 140a to 140d may each include a first lock signal terminal LOCK1 and a second lock signal terminal LOCK2 in order to transmit and receive lock signals).
Consider Claims 4 and 16, Hong et al shows that the timing controller, upon receiving the first control signal, is configured to transmit a second control signal for controlling training of the data driver and the clock training signal to the data driver (see paragraph 25).
Allowable Subject Matter
Claims 5-12, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 04/30/2026
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