DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/01/2026 has been entered.
Examiner’s Notes
Applicant’s amendments seem to newly include the term “identification signal.” While Applicant’s arguments do not provide further explanation or context of the term, paragraph 144 of the instant application states that “[t]he display device according to some embodiments of the present disclosure further outputs an identification signal Fsync to distinguish the type of image data input from the timing controller 170 when the timing controller 170 resumes transmission of image data. For example, when image data is retransmitted, the data driver 121 can distinguish whether the received image data is first image data (e.g., odd data) or second image data (e.g., even data) based on the identification signal Fsync. In this manner, when a lock fail occurs in the data driver 121, the display device according to some embodiments of the present disclosure can recover it as shown in the example of FIG. 9 and Table 2 during the recovery process.”
For the best chance to reach an allowability agreement, it is recommended that the Applicant incorporates the inventive concept encompassed by paragraph 144 of the instant application. For example, the claim states “divide the received image,” but the inventive concept is distinguishing between odd data and even data based on the Fsync signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Publication number: US 2023/0215317) in view of Hong et al (Publication number: US 2023/0014733) in view of Ichikura (Publication number: US 2022/0199048) in view of Kim et al (Publication number: US 2021/0398470).
Consider Claim 1, Kim shows a display device (see figure 6), comprising:
(a) A display panel (see figure 6; and paragraph 47); (Read as display panel 150).
(b) A timing controller configured to output image data (see figure 6; and paragraph 47); (Read as timing controller 120).
(c) A data driver configured to receive the image data from the timing controller (see figure 6; paragraph 47); (read as data driver 140); to divide the received image data into first image data and second image data, and to alternately output the first image data and the second image data (see figure 6; paragraphs 40-44, and 58-60); (The image supplier 110 (a set or a host system) may output various driving signals together with an image data signal supplied from an exterior thereof or an image data signal. he plurality of data drivers 140a to 140d may each include a first lock signal terminal LOCK1 and a second lock signal terminal LOCK2 in order to transmit and receive lock signals).
(d) A switching circuit configured to receive the first image data and the second image data from the data driver, to supply the first image data to sub-pixels of a first group in the display panel, and to supply the second image data to sub-pixels of a second group in the display panel (see figure 6; and paragraphs 56-57); (The plurality of data drivers 140a to 140d may have communication interfaces, and may receive signals including a clock signal, a data signal, etc. output from the timing controller 120 in the form of a data packet via the communication interfaces).
(e) Wherein the timing controller is configured to: identify that a lock fail of a clock signal has occurred in the data driver upon receiving a first control signal from the data driver while transmitting the image data for one frame; and upon identifying the lock fail, to interrupt transmission of the image data and to transmit a signal to the data driver to lock the clock signal (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
(f) Resume transmission of the image data when lock of the clock signal is completed, and to transmit to the data driver an identification signal for identifying a transmission time point of the first image data (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
However, Kim does not specifically show transmitting a clock training signal to the data driver.
In the same field of endeavor, Hong et al shows transmitting a clock training signal to the data driver (see paragraph 25).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the clock training signal of Hong et al into the teachings of Kim in order to restore the configuration of the environment for the high-speed communication (see Hong et al; paragraph 25).
However, Kim in view of Hong et al do not specifically show that the switching circuit comprises a demultiplexer.
In related art, Ichikura shows that the switching circuit comprises a demultiplexer (see figure 2; and paragraphs 47-50); (Please refer to the DMX block in Ichikura).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the switching circuit of Ichikura into the driving circuit of Kim in view of Hong et al in order to select between data lined on the basis of connection control signals (see Ichikura; paragraph 50).
However, Kim, Hong, and Ichikura do not specifically show that dividing the received image data into first and second image data based on an identification signal.
In related art, Kim et al shows that dividing the received image data into first and second image data based on an identification signal (see paragraphs 8-10, and 33-35); (A display driving device may include first and second data wires configured to connect a transmitter of a timing controller and a receiver of a source driver, first and second terminating resistors configured to connect the first and second data wires, and a noise reduction circuit configured to detect a lock fail in response to a clock signal, determine whether the detected lock fail satisfies a preset condition, generate a common voltage when the detected lock fail satisfies the preset condition).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Kim et al into the teaching of Kim, Hing, and Ichikura in order to reduce noise (see Kim et al; paragraphs 3-7).
Consider Claim 13, Kim shows a method for driving a display device (see figure 6), the method comprising:
(a) Outputting, by a timing controller, image data; receiving, by a data driver, the image data from the timing controller to divide the received image data into first image data and second image data; alternately outputting, by the data driver, the first image data and the second image data (see figure 6; paragraphs 40-44, and 58-60); (The image supplier 110 (a set or a host system) may output various driving signals together with an image data signal supplied from an exterior thereof or an image data signal. he plurality of data drivers 140a to 140d may each include a first lock signal terminal LOCK1 and a second lock signal terminal LOCK2 in order to transmit and receive lock signals).
(b) Receiving, by a switching circuit, the first image data and the second image data from the data driver, to supply the first image data to sub-pixels of a first group in a display panel, and to supply the second image data to sub-pixels of a second group in the panel (see figure 6; and paragraphs 56-57); (The plurality of data drivers 140a to 140d may have communication interfaces, and may receive signals including a clock signal, a data signal, etc. output from the timing controller 120 in the form of a data packet via the communication interfaces).
(c) Identifying, by the timing controller, that a lock fail of a clock signal has occurred in the data driver upon receiving a first control signal from the data driver while transmitting the image data for one frame; upon identifying the lock fail by the timing controller (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
(d) Interrupting transmission of the image data and transmitting a signal to the data driver to lock the clock signal (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
(e) Resuming, by the timing controller, transmission of the image data when lock of the clock signal is completed, and transmitting to the data driver an identification signal for identifying a transmission time point of the first image data (see figures 14-16; and paragraphs 92-95); (The data driver recognizes lock signal failure Lock Fail according to generation of an internal lock signal. When short is generated on an interface of a second data driver 140b and a timing controller 120, the second data driver 140b may output the black-level voltage. As a result, a black image is displayed on a display panel controlled by the second data driver 140b, identically to first, third and fourth data drivers 140a, 140c and 140d).
However, Kim does not specifically show transmitting a clock training signal to the data driver.
In the same field of endeavor, Hong et al shows transmitting a clock training signal to the data driver (see paragraph 25).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the clock training signal of Hong et al into the teachings of Kim in order to restore the configuration of the environment for the high-speed communication (see Hong et al; paragraph 25).
However, Kim in view of Hong et al do not specifically show that the switching circuit comprises a demultiplexer.
In related art, Ichikura shows that the switching circuit comprises a demultiplexer (see figure 2; and paragraphs 47-50); (Please refer to the DMX block in Ichikura).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the switching circuit of Ichikura into the driving circuit of Kim in view of Hong et al in order to select between data lined on the basis of connection control signals (see Ichikura; paragraph 50).
However, Kim, Hong, and Ichikura do not specifically show that dividing the received image data into first and second image data based on an identification signal.
In related art, Kim et al shows that dividing the received image data into first and second image data based on an identification signal (see paragraphs 8-10, and 33-35); (A display driving device may include first and second data wires configured to connect a transmitter of a timing controller and a receiver of a source driver, first and second terminating resistors configured to connect the first and second data wires, and a noise reduction circuit configured to detect a lock fail in response to a clock signal, determine whether the detected lock fail satisfies a preset condition, generate a common voltage when the detected lock fail satisfies the preset condition).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Kim et al into the teaching of Kim, Hing, and Ichikura in order to reduce noise (see Kim et al; paragraphs 3-7).
Claims 2-4 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Publication number: US 2023/0215317) in view of Hong et al (Publication number: US 2023/0014733) and Ichikura and Kim et al in view of Li et al (Publication number: US 2022/0036791).
Consider Claims 2 and 14, Kim in view of Hong et al, and Ichikura and Kim et al do not specifically show sub-pixels of the first group are odd sub-pixels of a plurality of sub-pixels in the display panel that are arranged in odd columns, and wherein the sub-pixels of the second group are even sub-pixels of the plurality of sub-pixels that are arranged in even columns.
In related art, Li et al shows sub-pixels of the first group are odd sub-pixels of a plurality of sub-pixels in the display panel that are arranged in odd columns, and wherein the sub-pixels of the second group are even sub-pixels of the plurality of sub-pixels that are arranged in even columns (see figures 3 and 7; paragraphs 67 and 75).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Li et al into the teaching of Kim and Hong et al, and Ichikura and Kim et al in order to extend service life (see Li et al; paragraphs 4-7).
Consider Claims 3 and 15, Kim shows that the timing controller is configured to output the first image data when resuming transmission of the image data (see figure 6; paragraphs 40-44, and 58-60); (The image supplier 110 (a set or a host system) may output various driving signals together with an image data signal supplied from an exterior thereof or an image data signal. he plurality of data drivers 140a to 140d may each include a first lock signal terminal LOCK1 and a second lock signal terminal LOCK2 in order to transmit and receive lock signals).
Consider Claims 4 and 16, Hong et al shows that the timing controller, upon receiving the first control signal, is configured to transmit a second control signal for controlling training of the data driver and the clock training signal to the data driver (see paragraph 25).
Allowable Subject Matter
Claims 5, 7-12, and 17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 08/08/2026
Prosecution Insights