DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on August 21, 2024, September 25, 2024 and August 11, 2025 have been considered by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7-9 and 12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ren et al (US 10,791,629; hereinafter Ren).
Regarding claim 1, Ren discloses a printed circuit board (4), comprising: a top layer (10) with a first conductive trace (60 Tx); a bottom layer (20) with a second conductive trace (60 Rx); a first signal VIA (52 Tx) connected to the first conductive trace (60 Tx); and a second signal VIA (52 Rx) connected to the second conductive trace (60 Rx), wherein a portion of the first signal VIA (52 Tx) overlaps a portion of the second signal VIA (52 Rx) along a Z-axis of the printed circuit board (see figure 4).
Regarding claim 4, Ren disclose the printed circuit board (4), wherein the top layer (10) has a top side cage signal structure that has a fanout pattern (see figure 6a; column 9 lines 1-37).
Regarding claim 7, Ren discloses the printed circuit board (4), wherein a bottom side signal cage structure on the bottom layer (20) has a VIA in pad type structure (see figure 6a, column 9 lines 1-37).
Regarding claim 8, Ren discloses a printed circuit board (4), comprising: a plurality of layers (column including ground layers, signal layers, a top layer, and a bottom layer, the top layer (10) having a first conductive trace (60 Tx), and the bottom layer (20) having a second conductive trace (60 Rx); a first signal VIA (52 Tx) extending through several layers of the plurality of layers, the first signal VIA (52Tx) being connected to the first conductive trace (60 Tx), the first signal VIA (52Tx) having a first distal end; and a second signal VIA (52 Rx) extending through several layers of the plurality of layers, the second signal VIA (52 Rx) being connected to the second conductive trace (60 Rx), the second signal VIA (52 Rx) having a second distal end, wherein the first distal end of the first signal VIA is closer to the bottom layer than the second distal end of the second signal VIA (see figure 4).
Regarding claim 9, Ren discloses the printed circuit board (4), wherein a portion of the first signal VIA (52 Tx) overlaps a portion of the second signal VIA (52 Rx) along a Z-axis of the printed circuit board (see figure 4).
Regarding claim 12, Ren disclose the printed circuit board (4), wherein the top layer (10) has a top side cage signal structure that has a fanout pattern (see figure 6a; column 9 lines 1-37).
Allowable Subject Matter
Claims 15-20 are allowed.
Claims 2, 3, 5, 6, 10, 11, 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance: The primary reasons for the indication of the allowability of claims 2, 3, 5, 6, 10, 11 and 13-20 are:
Regarding claim 2, the prior art does not teach or fairly suggest in combination with the other claimed limitations a printed circuit board, comprising, wherein the printed circuit board includes a ground VIA extending from the top layer to the bottom layer, and the ground VIA is located between the first signal VIA and the second signal VIA.
Regarding claim 3, the prior art does not teach or fairly suggest in combination with the other claimed limitations a printed circuit board, comprising, wherein the first signal VIA has a first distal end, the second signal VIA has a second distal end, a distance between the first distal end of the first signal VIA and the bottom layer is a first distance, a distance between the second distal end of the second signal VIA and the bottom layer is a second distance, and the first distance is less than the second distance.
Regarding claims 5 and 6, the prior art does not teach or fairly suggest in combination with the other claimed limitations a printed circuit board, comprising, further comprising: a first microstrip having a first end and a second end; and a pad, wherein the first signal VIA is connected to the first end of the first microstrip, and the second end of the first microstrip is connected to the pad.
Regarding claims 10 and 11, the prior art does not teach or fairly suggest in combination with the other claimed limitations a printed circuit board, wherein a distance between the first distal end of the first signal VIA and the top layer is a first distance, a distance between the second distal end of the second signal VIA and the top layer is a second distance, and the first distance is greater than the second distance.
Regarding claims 13 and 14, the prior art does not teach or fairly suggest in combination with the other claimed limitations the printed circuit board, further comprising: a first microstrip having a first end and a second end; and a pad, wherein the first signal VIA is connected to the first end of the first microstrip, and the second end of the first microstrip is connected to the pad.
Regarding claims 15-20, the prior art does not teach or fairly suggest in combination with the other claimed limitations a printed circuit board, comprising a ground VIA extending through several layers of the plurality of layers, the ground VIA being located between the first signal VIA and the second signal VIA, wherein a distance between the first distal end and the bottom layer is a first distance, a distance between the second distal end and the bottom layer is a second distance, and the first distance is less than the second distance.
These limitation is found in claims 2, 3, 5, 6, 10, 11 and 13-20, and are neither disclosed nor taught by the prior art of record, alone or in combination.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lam (US 8, 748, 753), Gruendler et al (US 8,492,658), Pai et al (US 7,968,802), Zhao et al (US 7,676,919), Tsuk (US 2005/0205295) and Chang et al (US 6,828,514) disclose a printed circuit board.
6. Any inquiry concerning this communication should be directed to Angel R. Estrada at telephone number (571) 272-1973. The Examiner can normally be reached on Monday-Friday (8:30am -5:00pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Imani N. Hayman can be reached on (571) 270-5528. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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October 2, 2026
/ANGEL R ESTRADA/Primary Examiner, Art Unit 2841
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