DETAILED ACTION
Reissue
The present reissue application is directed to US 11,538,881 B2 (“881 Patent”). 881 Patent issued on December 27, 2022 with claims 1-13 from application 17/029,843 filed on September 23, 2020, and claims priority to KR 10-2019-0139738 filed on November 4, 2019.
This application was filed on August 21, 2024. Since this date is after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions. Furthermore, the present application is being examined under the first inventor to file provisions of the AIA .
This application presents broadened claims, which are permitted because Applicant filed these claims and demonstrated an intent to broaden within two years of the issue date of 881 Patent.
The most recent amendment was filed on January 15, 2026. The status of the claims is:
Claims 1, 6, 12: Amended
Claims 2-5, 7-11, and 13: Original
Claims 14 and 15: New
This is a final action.
References and Documents Cited in this Action
881 Patent (US 11,538,881 B2)
Response (response filed by Applicant on January 15, 2026)
Kim (US 2013/0313529 A1)
Summary of Rejections and Objections in this Action
Examiner objects to the claim amendment.
Claim 6 is rejected under 35 U.S.C. 112(d) as being of improper dependent form
Claims 14 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim.
Claims 1-5 and 7-13 are allowed.
Summary of the Claims
881 Patent is generally directed to a display apparatus including a thin film transistor including a first semiconductor layer and a first gate electrode, and a first gate insulating layer in between. Claim 14 is representative:
14. A display apparatus comprising:
a first transistor on a layer in a first direction, and
a display element electrically connected to the first transistor, wherein
the first transistor includes:
a first semiconductor layer; and
a first gate electrode on the first semiconductor layer in the first direction, the first gate electrode overlapping the first semiconductor layer in a plan view, and
a first insulating layer disposed on the first semiconductor layer in the first direction and under the first gate electrode in the first direction.
Claims 1, 12, and 14 are the independent claims. Claims 1 and 12 each also recite a display element and a first transistor including a first semiconductor layer, a first gate electrode, and a first insulating layer, and further recite a storage capacitor including a lower electrode and an upper electrode.
Claim Amendment
Examiner objects to the claim amendment filed on January 15, 2026 because it does not comply with 37 CFR 1.173. In claim 6, the deleted words must be marked with brackets instead of strikethrough. See 37 CFR 1.173(d).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 6 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding claim 6, its parent claim 1 previously recites “a first gate electrode overlapping the first semiconductor layer” and “an upper electrode overlapping the lower electrode.” Claim 6 further recites “wherein the first gate electrode functions as the upper electrode.” Claim 6 thus does not include every limitation of parent claim 1 (i.e., a first gate electrode and an upper electrode that are two individual elements).
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim.
Regarding independent claim 14, Kim discloses a display apparatus (Figure 1) comprising:
a first transistor TR on a layer in a first direction (i.e., substrate 10; the “first direction” is pointing down in Kim, Figure 1), and
a display element PXL electrically connected to the first transistor, wherein
the first transistor includes:
a first semiconductor layer 214 (paragraph [0049]); and
a first gate electrode (i.e., gate electrode 212 and/or 213) on the first semiconductor layer 214 in the first direction, the first gate electrode overlapping the first semiconductor layer in a plan view and
a first insulating layer 13 disposed on the first semiconductor layer in the first direction and under the first gate electrode in the first direction (paragraph [0048]; as the “first direction” is pointing down in Kim, Figure 1, insulating layer 13 is “under” gate electrodes 212/13 and “disposed on" first semiconductor layer 214).
PNG
media_image1.png
429
667
media_image1.png
Greyscale
Regarding claim 15, Kim further discloses:
a capacitor CAP including:
a lower electrode including a first lower layer and a first upper layer disposed on the first lower layer (i.e., the electrode comprising layers 314, 316, and 317; paragraphs [0053]-[0054]);
an upper electrode including a second lower layer and a second upper layer disposed on the second lower layer (i.e., the electrode comprising layers 312 and 313; paragraphs [0053]-[0054]),
the upper electrode overlapping the lower electrode in a plan view;
a second insulating layer disposed directly on the lower electrode and directly under the upper electrode (i.e., another part of insulating layer 13 is disposed between the lower and upper electrodes of the capacitor; Figure 1; paragraph [0055]).
PNG
media_image2.png
438
762
media_image2.png
Greyscale
Examiner notes that Kim discloses first and second insulating layers as recited in the claim at least because Kim, Figure 1 shows a first part of insulating layer 13 disposed on the first semiconductor layer and under the first gate electrode of transistor TR, and a second part of insulating layer 13 disposed directly on the lower electrode and directly under the upper electrode of capacitor CAP. Examiner acknowledges that Applicant’s Figure 3, for example, shows a slightly different arrangement including a first insulating layer 113 and a second insulating layer 114 that is further disposed on the first insulating layer 113. However, these details are not recited in the claim, and Kim’s disclosure reads on the broader recitation in the claim.
Allowable Subject Matter
Claims 1-5 and 7-13 are allowed. Claim 6 may contain allowable subject matter if rewritten to overcome the rejection of the claim under 35 U.S.C. 112(d).
The prior art does not specifically disclose or fairly suggest a display apparatus including the combination of all of the elements, steps, and limitations recited in claims 1-13 (including all of the limitations of any respective parent claims), particularly including:
a thin film transistor on the substrate in a first direction and a second gate insulating layer disposed directly between the upper electrode and the lower electrode, wherein the second gate insulating layer is spaced apart from the first gate insulating layer in the first direction (e.g., claims 1-11); or
a thin film transistor on the substrate in a first direction and a lower electrode disposed on the first gate insulating layer in the first direction, wherein the lower electrode is spaced apart from the upper electrode in the first direction (e.g., claims 12 and 13).
Response to Arguments
Applicant’s Response, including the amendment to the claims, has been fully considered.
The reissue declaration filed on January 15, 2026 has overcome the rejection of the claims under 35 U.S.C. 251 as being based upon a defective reissue declaration.
Examiner acknowledges the cancelation of claims 16-26.
Applicant’s amendment to claim 6 has overcome the rejections of claim 6 under 35 U.S.C. 251 for not being the same invention as disclosed as being the invention in the original patent and under 35 U.S.C. 112(a) as failing to comply with the written description requirement. However, the amendment has necessitated a new rejection under 35 U.S.C. 112(d) as set forth above.
Applicant’s arguments with respect to claims 1-13, in view of the amendment to claims 1 and 12, are persuasive. Claims 1-5 and 7-13 are allowed. Claim 6 may contain allowable subject matter if rewritten to overcome the rejection of the claim under 35 U.S.C. 112(d).
Applicant’s arguments with respect to claims 14 and 15 are not persuasive. Claims 14 and 15 do not recite the allowable limitations recited in claims 1 and 12. For example, claims 14 and 15 do not recite that the second gate insulating layer is spaced apart from the first gate insulating layer in the first direction; or that the lower electrode is disposed on the first gate insulating layer in the first direction, wherein the lower electrode is also spaced apart from the upper electrode in the first direction. Claim 14 in particular does not even recite a second gate insulating layer or lower and upper electrodes.
Examiner maintains that Kim still reads on claims 14 and 15 despite the addition of a “first direction” to the claims. Again, Kim discloses first and second insulating layers as recited in the claim at least because Kim, Figure 1 shows a first part of insulating layer 13 disposed on the first semiconductor layer and under the first gate electrode of transistor TR, and a second part of insulating layer 13 disposed directly on the lower electrode and directly under the upper electrode of capacitor CAP. Examiner acknowledges that Applicant’s Figure 3, for example, shows a slightly different arrangement including a first insulating layer 113 and a second insulating layer 114 that is further disposed on the first insulating layer 113. However, these details are not recited in claims 14 and 15, and Kim’s disclosure reads on the broader recitation in the claims.
Furthermore, Kim discloses two capacitor electrodes, each having multiple layers. The labels “lower” and “upper” can be arbitrarily assigned to the electrodes because claim 15 does not further recite details distinguishing a “lower” electrode from an “upper” electrode. In order for the first insulating layer to be “under the first gate electrode in the first direction” and the second insulating layer to be “directly under the upper electrode” as recited in claims 14 and 15, the “first direction” is the down direction in Kim, Figure 1; the “upper electrode” is the electrode comprising layers 312 and 313; and the “lower electrode” is the electrode comprising layers 314, 316, and 317:
PNG
media_image2.png
438
762
media_image2.png
Greyscale
Kim thus still discloses the claimed elements arranged as recited in claims 14 and 15.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which this reissue application is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation. Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application. These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant is notified that any subsequent amendment to the specification and/or claims must comply with 37 CFR 1.173(b).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patents/laws/interview-practice.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Any inquiry concerning this communication or earlier communications from the examiner, or as to the status of this proceeding, should be directed to Examiner Christina Leung at telephone number (571) 272-3023; the Examiner’s supervisor, SPE Patricia Engle at (571) 272-6660; or the Central Reexamination Unit at (571) 272-7705.
/CHRISTINA Y. LEUNG/Primary Examiner, Art Unit 3991
Conferees:
/DEANDRA M HUGHES/Reexamination Specialist, Art Unit 3992
/Patricia L Engle/SPRS, Art Unit 3991