Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-40 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hosomura (Patent Application Publication 2008/0198667).
Claim 21. A method, comprising: providing a first voltage level to a first access line associated with a memory array (voltage applied to CG1, Hosomura Fig. 8); providing a second voltage level to a second access line associated with the memory array (providing a second voltage level to CG2); and controlling the first access line and the second access line to have a substantially equal voltage (CG1 and CG2 to an equalization potential through T1 and T2, equalizing after a write Hosomura Abstract).
Claim 22. The method of claim 21, wherein the substantially equal voltage is different than a ground reference potential (when programming a logic high to the WLs the substantially equal voltage is different than a ground reference potential and Vdd [0111] is different than ground).
Claim 23. The method of claim 21, comprising: after controlling the first access line and the second access line to have the substantially equal voltage (CG1 and CG2 to an equalization potential through T1 and T2), discharging the first access line and the second access line to a ground reference potential (Through discharge transistors HT1 and HT2 Hosomura, Fig. 8. Ground potential coupled to the discharge transistors taught in, Hosomura [0106] and [0109]).
Claim 24. The method of claim 21, comprising after controlling the first access line and the second access line to have the substantially equal voltage (CG1 and CG2 to an equalization potential through T1 and T2), controlling the first access line or the second access line, or both, to have a third voltage that is different from the substantially equal voltage (programming to a logic low is different from the substantially equal voltage when programming a logic high).
Claim 25. The method of claim 21, comprising after controlling the first access line and the second access line to have the substantially equal voltage (CG1 and CG2 to an equalization potential through T1 and T2), controlling the first access line or the second access line, or both, to have a third voltage that is different from a ground reference potential (programming to a logic low is different from a ground reference potential).
Claim 26. The method of claim 21, wherein the second voltage level is higher than the first voltage level (choosing the logic high as the second voltage and logic low as the first voltage, the second voltage is higher than the first voltage level).
Claim 27. An apparatus, comprising: an array of memory cells (cells in array 2 Fig 1); and control circuitry coupled to the array (comprising WL Driver 3 Fig 1) and configured to (configured to is functional language): perform a read operation comprising: providing a first voltage to a selected access line of the array (providing a ground voltage through discharge transistor HT1); providing a second voltage to a non-selected access line of the array (voltage applied to CG2, Hosomura Fig. 8 when programming a logic low), a magnitude of the second voltage being greater than a magnitude of the first voltage (magnitude for a logic high is greater than ground); and subsequently to performing the read operation, provide a third voltage to the selected access line, the magnitude of the first voltage and a magnitude of the third voltage being different from each other (programming to a logic low is different from the substantially equal voltage when programming a logic high), and the third voltage being different than a ground voltage (programming to a logic low is different from a ground reference potential).
Claim 28. The apparatus of claim 27, wherein the third voltage is greater than the ground voltage (Logic low voltage is greater than ground).
Claim 29. The apparatus of claim 27, wherein the array is a three dimensional array (Memory cell array 2 represents a three dimensional array, Hosomura Fig 2), and wherein the selected access line and the unselected access line are coupled to a same string of the array (access of array in Fig 2 taught in Fig 8 ).
Claim 30. The apparatus of claim 29, wherein the array comprises a plurality of access lines formed as respective stair steps of a stair step structure (stair steps structure taught in Hosomura Fig 5).
Claim 31. The apparatus of claim 29, wherein the third voltage is an equalization voltage to which the selected access line and the unselected access line are commonly driven as part of an equalization operation (logic low is equalized on CG1 and CG2 to an equalization potential through T1 and T2).
Claim 32. The apparatus of claim 31, wherein the control circuitry is configured to (configured to is functional language), subsequent to the equalization operation, drive the unselected access line and the selected access line to a fourth voltage via a number of string drivers (driving the access lines comprising CG1 and CG2 to a fourth voltage vide string drivers Tn or HTn).
Claim 33. The apparatus of claim 32, wherein a magnitude of the fourth voltage is less than the magnitude of the equalization voltage (when discharging to ground the magnitude of the fourth voltage is less than the magnitude of the logic low equalization voltage).
Claim 34. The apparatus of claim 33, wherein the fourth voltage is the ground voltage (when discharging through discharge transistor HTn Fig 8, the magnitude of the fourth voltage is ground).
Claim 35. An apparatus, comprising: a host interface configured to (configured to is functional language) couple to a host (coupled through CG driver 4, Hosomura Fig 1); a controller coupled to the host interface (WL Driver 3 Fig 1); and a memory device coupled to the controller and comprising a three dimensional array of memory cells (Memory cell array 2 represents a three dimensional array, Hosomura Fig 2); and wherein the controller is configured to (configured to is functional language), subsequent to performing a read operation in which a selected access line is biased at a first voltage and an unselected access line is biased at a second voltage (Biasing to a logic low through CGn), perform an equalization operation in which the selected access line and the unselected access line are brought to a same voltage that is between the first voltage and the second voltage (CG1 and CG2 to an equalization potential through T1 and T2, equalizing after a write Hosomura Abstract).
Claim 36. The apparatus of claim 35, wherein the controller is configured to (configured to is functional language), subsequent to the equalization operation, apply a third voltage to the selected access line and the unselected access line (applying a logic high voltage through CG1 and CG2).
Claim 37. The apparatus of claim 36, wherein the third voltage is different than the same voltage (logic high voltage is different than a logic low or ground voltage).
Claim 38. The apparatus of claim 35, wherein the apparatus is a solid state drive (NAND flash for Fig 8 taught in [0011]. NAND flash is used in solid state drives.).
Claim 39. The apparatus of claim 35, wherein the three dimensional array comprises a stair step structure with the steps corresponding to different respective access lines (stair steps structure taught in Hosomura Fig 5).
Claim 40 The apparatus of claim 35, wherein the controller is configured to (configured to is functional language), subsequent to the equalization operation, discharge to ground a number of global control lines to which the selected access line and the unselected access line are coupled (transistors HTn Fig 8 discharge to ground a number of global control lines comprising gates CGn to which the selected access line and the unselected access line are coupled).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827