DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: it is best understood by the examiner that there is a typographical error wherein instead of “a metal nitride layer on the gate electrode:” it should be “a metal nitride layer on the gate electrode;”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 2021/0118995 A1 hereinafter referred to as “Cheng”).
With respect to claim 1, Cheng discloses, in Figs.1A-17B, a semiconductor device comprising: a gate electrode (135); a metal nitride layer (1354) on the gate electrode: a gate insulating film (128) on the metal nitride layer; a channel (120) on the gate insulating film; a source electrode on one side of the channel; and a drain electrode (126) on another side of the channel (see Par.[0041], [0049]-[0050] wherein gate metal fill layers 135A-135B; see Par.[0097]-[0100] wherein metal nitride capping layer 1354 can include TiSiN or TiN and can be deposited by an ALD or a CVD process using titanium tetrachloride (TiCl.sub.4), silane (SiH.sub.4), and ammonia (NH.sub.3) as precursors at a temperature ranging from about 400° C. to about 500° C; metal nitride capping layer 1354 can have a thickness ranging from about 1 nm to about 3 nm and can react with gate dielectric layer 128 during subsequent first and/or second spike annealing processes (described below) to form a barrier layer (not shown) on gate dielectric layer 128; see Par.[0039]-[0040] wherein nanostructured channel regions 120B and 122B can be interposed between a pair of S/D regions 126A-126B, respectively, as shown in FIGS. 1C-1D and 2A-2B).
With respect to claim 2, Cheng discloses, in Figs.1A-17B, the devive, wherein the metal nitride (1354) layer comprises transition metal and nitrogen (see Par.[0097]-[0100] wherein metal nitride capping layer 1354 can include TiSiN or TiN and can be deposited by an ALD or a CVD process using titanium tetrachloride (TiCl.sub.4), silane (SiH.sub.4), and ammonia (NH.sub.3) as precursors at a temperature ranging from about 400° C. to about 500° C; metal nitride capping layer 1354 can have a thickness ranging from about 1 nm to about 3 nm and can react with gate dielectric layer 128 during subsequent first and/or second spike annealing processes (described below) to form a barrier layer (not shown) on gate dielectric layer 128).
With respect to claim 3, Cheng discloses, in Figs.1A-17B, the device, wherein the metal nitride layer comprises a material represented by M1N, where M1 is Mo, W, Nb, V, Ta, Ti, Zr, or Hf (see Par.[0097]-[0100] wherein metal nitride capping layer 1354 can include TiSiN or TiN and can be deposited by an ALD or a CVD process using titanium tetrachloride (TiCl.sub.4), silane (SiH.sub.4), and ammonia (NH.sub.3) as precursors at a temperature ranging from about 400° C. to about 500° C; metal nitride capping layer 1354 can have a thickness ranging from about 1 nm to about 3 nm and can react with gate dielectric layer 128 during subsequent first and/or second spike annealing processes (described below) to form a barrier layer (not shown) on gate dielectric layer 128).
With respect to claim 11, Cheng discloses, in Figs.1A-17B, a method of manufacturing a semiconductor device, the method comprising: depositing a metal layer (1354) on a gate electrode (135); forming a metal nitride layer (1354) by reacting nitrogen to the metal layer (see Par.[0041], [0049]-[0050] wherein gate metal fill layers 135A-135B; see Par.[0097]-[0100] wherein metal nitride capping layer 1354 can include TiSiN or TiN and can be deposited by an ALD or a CVD process using titanium tetrachloride (TiCl.sub.4), silane (SiH.sub.4), and ammonia (NH.sub.3) as precursors at a temperature ranging from about 400° C. to about 500° C; metal nitride capping layer 1354 can have a thickness ranging from about 1 nm to about 3 nm and can react with gate dielectric layer 128 during subsequent first and/or second spike annealing processes (described below) to form a barrier layer (not shown) on gate dielectric layer 128); forming a gate insulating film (128) on the metal nitride layer (1354); forming a channel (120) on the gate insulating film (128); and forming a source electrode and a drain electrode (126) on opposite sides of the channel (120) (see Par.[0039]-[0040] wherein nanostructured channel regions 120B and 122B can be interposed between a pair of S/D regions 126A-126B, respectively, as shown in FIGS. 1C-1D and 2A-2B).
With respect to claim 12, Cheng discloses, in Figs.1A-17B, the method, wherein the metal nitride (1354) layer comprises transition metal and nitrogen (see Par.[0097]-[0100] wherein metal nitride capping layer 1354 can include TiSiN or TiN and can be deposited by an ALD or a CVD process using titanium tetrachloride (TiCl.sub.4), silane (SiH.sub.4), and ammonia (NH.sub.3) as precursors at a temperature ranging from about 400° C. to about 500° C; metal nitride capping layer 1354 can have a thickness ranging from about 1 nm to about 3 nm and can react with gate dielectric layer 128 during subsequent first and/or second spike annealing processes (described below) to form a barrier layer (not shown) on gate dielectric layer 128).
With respect to claim 13, Cheng discloses, in Figs.1A-17B, the method, wherein the metal nitride layer comprises a material represented by M1N, where M1 is Mo, W, Nb, V, Ta, Ti, Zr, or Hf (see Par.[0097]-[0100] wherein metal nitride capping layer 1354 can include TiSiN or TiN and can be deposited by an ALD or a CVD process using titanium tetrachloride (TiCl.sub.4), silane (SiH.sub.4), and ammonia (NH.sub.3) as precursors at a temperature ranging from about 400° C. to about 500° C; metal nitride capping layer 1354 can have a thickness ranging from about 1 nm to about 3 nm and can react with gate dielectric layer 128 during subsequent first and/or second spike annealing processes (described below) to form a barrier layer (not shown) on gate dielectric layer 128).
Claims 1-6, 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shen et al. (US 2021/0313454 A1 hereinafter referred to as “Shen”).
With respect to claim 1, Shen discloses, in Figs.1A-10, a semiconductor device comprising: a gate electrode (42); a metal nitride layer (95) on the gate electrode (see Par.[0066], [0068], [0073] wherein the oxygen content of the oxide layer M2O.sub.n further away from the gate electrode layer 100 is lower than the oxygen content of the oxide layer M2O.sub.m because of the intervening oxygen absorbing layers 85 that react with the oxygen that is driven or diffused into the gate stack structure 75; a gate metal electrode layer 100 is subsequently formed over the second type WFM layer; see Par.[0071] wherein the first and second metal nitride layers are TiN and the TiN is formed by an ALD process by the following reaction: TiCl.sub.4+NH.sub.3.fwdarw.TiN.sub.(solid)+HCl.sub.(gas); the Ti atomic concentration in the TiN is varied by adjusting the ratio of the TiCl.sub.4 and NH.sub.3 reactants, the pressure of the reactant gases, the flowrate of the TiCl.sub.4 and NH.sub.3 reactants, and duration of time the TiCl.sub.4 and NH.sub.3 reactants are supplied to the deposition chamber); a gate insulating film (80) on the metal nitride layer (see Par.[0054]-[0056] wherein the gate stack 75 includes a gate dielectric layer 80 formed over the channel region 70 of the fin structure 20); a channel (70) on the gate insulating film; a source electrode (32) on one side of the channel; and a drain electrode (34) on another side of the channel (see Par.[0087] wherein an oxygen absorbing layer 85 are formed over a channel region 70 of the semiconductor device; see Par.[0025] wherein a gate dielectric layer 35 and a gate electrode 42; the fin 20 may be intrinsic and may appropriately be doped with an n-type impurity or a p-type impurity. In some embodiments, source and drain regions 32 and 34 are heavily doped and may contain impurities having a concentration in a range from about 5×10.sup.19 cm.sup.−3 to 1×10.sup.20 cm.sup.−3, while a channel region 22, e.g., a gate region, is undoped or lightly doped).
With respect to claim 2, Shen discloses, in Figs.1A-10, the semiconductor device, wherein the metal nitride layer comprises transition metal and nitrogen (see Par.[0066], [0068], [0073] wherein the oxygen content of the oxide layer M2O.sub.n further away from the gate electrode layer 100 is lower than the oxygen content of the oxide layer M2O.sub.m because of the intervening oxygen absorbing layers 85 that react with the oxygen that is driven or diffused into the gate stack structure 75; a gate metal electrode layer 100 is subsequently formed over the second type WFM layer; see Par.[0071] wherein the first and second metal nitride layers are TiN and the TiN is formed by an ALD process by the following reaction: TiCl.sub.4+NH.sub.3.fwdarw.TiN.sub.(solid)+HCl.sub.(gas); the Ti atomic concentration in the TiN is varied by adjusting the ratio of the TiCl.sub.4 and NH.sub.3 reactants, the pressure of the reactant gases, the flowrate of the TiCl.sub.4 and NH.sub.3 reactants, and duration of time the TiCl.sub.4 and NH.sub.3 reactants are supplied to the deposition chamber).
With respect to claim 3, Shen discloses, in Figs.1A-10, the device, wherein the metal nitride layer comprises a material represented by M1N, where M1 is Mo, W, Nb, V, Ta, Ti, Zr, or Hf (see Par.[0066], [0068], [0073] wherein the oxygen content of the oxide layer M2O.sub.n further away from the gate electrode layer 100 is lower than the oxygen content of the oxide layer M2O.sub.m because of the intervening oxygen absorbing layers 85 that react with the oxygen that is driven or diffused into the gate stack structure 75; a gate metal electrode layer 100 is subsequently formed over the second type WFM layer; see Par.[0071] wherein the first and second metal nitride layers are TiN and the TiN is formed by an ALD process by the following reaction: TiCl.sub.4+NH.sub.3.fwdarw.TiN.sub.(solid)+HCl.sub.(gas); the Ti atomic concentration in the TiN is varied by adjusting the ratio of the TiCl.sub.4 and NH.sub.3 reactants, the pressure of the reactant gases, the flowrate of the TiCl.sub.4 and NH.sub.3 reactants, and duration of time the TiCl.sub.4 and NH.sub.3 reactants are supplied to the deposition chamber).
With respect to claim 4, Shen discloses, in Figs.1A-10, the device, wherein the metal nitride layer has a nitrogen content in a range of about 10 at% to about 50 at% (see Par.[0070] wherein the metal nitride is titanium nitride, the second titanium nitride layer 85 contains from about 3 at. % to about 30 at. % more titanium than the first titanium nitride layer 90).
With respect to claim 5, Shen discloses, in Figs.1A-10, the device, wherein the metal nitride layer (95) has a thickness of about 0 nm to about 3 nm (see Par.[0058] wherein he thickness of the work function metal layers range from about 0.2 nm to about 10 nm in some embodiments, and between about 0.5 nm to about 5 nm).
With respect to claim 6, Shen discloses, in Figs.1A-10, the device, wherein the channel comprises a material represented by M2X2, where M2 is Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, or Re, and X is S, Se, or Te (see Par.[0043] wherein The nWFM layers can include a metallic material with a work function value closer to a conduction band energy than a valence band energy of a material of nanostructured channel regions 120B. For example, the nWFM layers can include an Al-based or Al-doped metallic material with a work function value less than 4.5 eV (e.g., about 3.5 eV to about 4.4 eV), which can be closer to the conduction band energy (e.g., 4.1 eV of Si or 3.8 eV of SiGe) than the valence band energy (e.g., 5.2 eV of Si or 4.8 eV of SiGe) of Si-based or SiGe-based nanostructured channel regions 120B, respectively. In some embodiments, the nWFM layers can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or a combination thereof).
With respect to claim 11, Shen discloses, in Figs.1A-10, a method of manufacturing a semiconductor device, the method comprising: depositing a metal layer (95) on a gate electrode (42/100); forming a metal nitride layer (95) by reacting nitrogen to the metal layer (see Par.[0066], [0068], [0073] wherein the oxygen content of the oxide layer M2O.sub.n further away from the gate electrode layer 100 is lower than the oxygen content of the oxide layer M2O.sub.m because of the intervening oxygen absorbing layers 85 that react with the oxygen that is driven or diffused into the gate stack structure 75; a gate metal electrode layer 100 is subsequently formed over the second type WFM layer; see Par.[0071] wherein the first and second metal nitride layers are TiN and the TiN is formed by an ALD process by the following reaction: TiCl.sub.4+NH.sub.3.fwdarw.TiN.sub.(solid)+HCl.sub.(gas); the Ti atomic concentration in the TiN is varied by adjusting the ratio of the TiCl.sub.4 and NH.sub.3 reactants, the pressure of the reactant gases, the flowrate of the TiCl.sub.4 and NH.sub.3 reactants, and duration of time the TiCl.sub.4 and NH.sub.3 reactants are supplied to the deposition chamber); forming a gate insulating film (80) on the metal nitride layer (see Par.[0054]-[0056] wherein the gate stack 75 includes a gate dielectric layer 80 formed over the channel region 70 of the fin structure 20); forming a channel (70) on the gate insulating film (80) (see Par.[0087] wherein an oxygen absorbing layer 85 are formed over a channel region 70 of the semiconductor device); and forming a source electrode (32) and a drain electrode (34) on opposite sides of the channel (22) (see Par.[0025] wherein a gate dielectric layer 35 and a gate electrode 42; the fin 20 may be intrinsic and may appropriately be doped with an n-type impurity or a p-type impurity. In some embodiments, source and drain regions 32 and 34 are heavily doped and may contain impurities having a concentration in a range from about 5×10.sup.19 cm.sup.−3 to 1×10.sup.20 cm.sup.−3, while a channel region 22, e.g., a gate region, is undoped or lightly doped).
With respect to claim 12, Shen discloses, in Figs.1A-10, the method, wherein the metal nitride layer comprises transition metal and nitrogen (see Par.[0066], [0068], [0073] wherein the oxygen content of the oxide layer M2O.sub.n further away from the gate electrode layer 100 is lower than the oxygen content of the oxide layer M2O.sub.m because of the intervening oxygen absorbing layers 85 that react with the oxygen that is driven or diffused into the gate stack structure 75; a gate metal electrode layer 100 is subsequently formed over the second type WFM layer; see Par.[0071] wherein the first and second metal nitride layers are TiN and the TiN is formed by an ALD process by the following reaction: TiCl.sub.4+NH.sub.3.fwdarw.TiN.sub.(solid)+HCl.sub.(gas); the Ti atomic concentration in the TiN is varied by adjusting the ratio of the TiCl.sub.4 and NH.sub.3 reactants, the pressure of the reactant gases, the flowrate of the TiCl.sub.4 and NH.sub.3 reactants, and duration of time the TiCl.sub.4 and NH.sub.3 reactants are supplied to the deposition chamber).
With respect to claim 13, Shen discloses, in Figs.1A-10, the method, wherein the metal nitride layer comprises a material represented by M1N, where M1 is Mo, W, Nb, V, Ta, Ti, Zr, or Hf (see Par.[0066], [0068], [0073] wherein the oxygen content of the oxide layer M2O.sub.n further away from the gate electrode layer 100 is lower than the oxygen content of the oxide layer M2O.sub.m because of the intervening oxygen absorbing layers 85 that react with the oxygen that is driven or diffused into the gate stack structure 75; a gate metal electrode layer 100 is subsequently formed over the second type WFM layer; see Par.[0071] wherein the first and second metal nitride layers are TiN and the TiN is formed by an ALD process by the following reaction: TiCl.sub.4+NH.sub.3.fwdarw.TiN.sub.(solid)+HCl.sub.(gas); the Ti atomic concentration in the TiN is varied by adjusting the ratio of the TiCl.sub.4 and NH.sub.3 reactants, the pressure of the reactant gases, the flowrate of the TiCl.sub.4 and NH.sub.3 reactants, and duration of time the TiCl.sub.4 and NH.sub.3 reactants are supplied to the deposition chamber).
With respect to claim 14, Shen discloses, in Figs.1A-10, the method, wherein the metal nitride layer has a nitrogen content in a range of about 10 at% to about 50 at% (see Par.[0070] wherein the metal nitride is titanium nitride, the second titanium nitride layer 85 contains from about 3 at. % to about 30 at. % more titanium than the first titanium nitride layer 90).
With respect to claim 15, Shen discloses, in Figs.1A-10, the method, wherein the metal nitride layer (95) has a thickness of about 0 nm to about 3 nm (see Par.[0058] wherein he thickness of the work function metal layers range from about 0.2 nm to about 10 nm in some embodiments, and between about 0.5 nm to about 5 nm).
With respect to claim 16, Shen discloses, in Figs.1A-10, the method, wherein the channel comprises a material represented by M2X2, where M2 is Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, or Re, and X is S, Se, or Te (see Par.[0043] wherein The nWFM layers can include a metallic material with a work function value closer to a conduction band energy than a valence band energy of a material of nanostructured channel regions 120B. For example, the nWFM layers can include an Al-based or Al-doped metallic material with a work function value less than 4.5 eV (e.g., about 3.5 eV to about 4.4 eV), which can be closer to the conduction band energy (e.g., 4.1 eV of Si or 3.8 eV of SiGe) than the valence band energy (e.g., 5.2 eV of Si or 4.8 eV of SiGe) of Si-based or SiGe-based nanostructured channel regions 120B, respectively. In some embodiments, the nWFM layers can include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or a combination thereof).
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2023/0261064 A1 hereinafter referred to as “Park”).
With respect to claim 1, Park discloses, in Figs.1-36, a semiconductor device comprising: a gate electrode/(TiC, TaC, TiAlC satcking plurality of conductive layers) (130/230); a metal nitride layer/(TiN, TaN, TaCN satcking plurality of conductive layers) on the gate electrode (see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof); a gate insulating film (120) on the metal nitride layer (see Par.[0043]-[0044] wherein the first gate dielectric film 120 may include a dielectric material, for example, silicon oxide, silicon oxynitride, silicon nitride and/or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, but is not necessarily limited to including, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and/or combinations thereof); a channel (112, 114) on the gate insulating film (see Par.[0037]-[0038] wherein sheet patterns 112 and 114 may be used as channel regions of MBCFET, a multigate device produced by Samsung, including a multi-bridge channel; he first active pattern AP1 may include a two-dimensional semiconductor material; the two-dimensional semiconductor material may include, for example, but is not necessarily limited to including, graphene, carbon nanotube, transition metal dichalcogenide (TMD) or combinations thereof. The transition metal dichalcogenide (TMD) may include, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and/or Pb, and S, Se and/or Te); a source electrode (164) on one side of the channel; and a drain electrode (164) on another side of the channel (see Par.[0056]-[0062] wherein The first source/drain contact 160 may include a first contact insertion film 162 and a first filling metal film 164 that are stacked sequentially on the upper surface of the substrate 100 (or the first etching blocking film 105) and the side surfaces of the first gate electrode 130).
With respect to claim 2, Park discloses, in Figs.1-36, the semiconductor device, wherein the metal nitride layer comprises transition metal and nitrogen (see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof).
With respect to claim 3, Park discloses, in Figs.1-36, the semiconductor device, wherein the metal nitride layer comprises a material represented by M1N, where M1 is Mo, W, Nb, V, Ta, Ti, Zr, or Hf (see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof).
With respect to claim 6, Park discloses, in Figs.1-36, the semiconductor device, wherein the channel comprises a material represented by M2X2, where M2 is Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, or Re, and X is S, Se, or Te (see Par.[0037]-[0038] wherein sheet patterns 112 and 114 may be used as channel regions of MBCFET, a multigate device produced by Samsung, including a multi-bridge channel; the first active pattern AP1 may include a two-dimensional semiconductor material; the two-dimensional semiconductor material may include, for example, but is not necessarily limited to including, graphene, carbon nanotube, transition metal dichalcogenide (TMD) or combinations thereof. The transition metal dichalcogenide (TMD) may include, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and/or Pb, and S, Se and/or Te).
With respect to claim 7, Park discloses, in Figs.1-36, the semiconductor device, wherein the channel comprises MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, or ReSe2 (see Par.[0088], [0091] wherein second active pattern AP2, a second gate dielectric film 220, a second gate electrode 230, a second gate spacer 240, a second source/drain contact 260, and a second wiring structure WS2).
With respect to claim 8, Park discloses, in Figs.1-36, the semiconductor device, wherein the metal nitride layer further comprises carbon (see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof).
With respect to claim 9, Park discloses, in Figs.1-36, the semiconductor device, wherein the gate electrode is in direct contact with the metal nitride layer (see Fig.1-2).
With respect to claim 10, Park discloses, in Figs.1-36, the semiconductor device, wherein the channel comprises one to ten layers of two-dimensional semiconductor material layers (see Par.[0037]-[0038] wherein sheet patterns 112 and 114 may be used as channel regions of MBCFET, a multigate device produced by Samsung, including a multi-bridge channel; he first active pattern AP1 may include a two-dimensional semiconductor material; the two-dimensional semiconductor material may include, for example, but is not necessarily limited to including, graphene, carbon nanotube, transition metal dichalcogenide (TMD) or combinations thereof. The transition metal dichalcogenide (TMD) may include, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and/or Pb, and S, Se and/or Te).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Shen.
With respect to claim 11, Park discloses, in Figs.1-36, a method of manufacturing a semiconductor device, the method comprising: depositing a metal layer on a gate electrode; forming a metal nitride layer; forming a gate insulating film on the metal nitride layer; forming a channel on the gate insulating film; and forming a source electrode and a drain electrode on opposite sides of the channel (see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof; see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof; see Par.[0043]-[0044] wherein the first gate dielectric film 120 may include a dielectric material, for example, silicon oxide, silicon oxynitride, silicon nitride and/or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, but is not necessarily limited to including, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and/or combinations thereof; see Par.[0037]-[0038] wherein sheet patterns 112 and 114 may be used as channel regions of MBCFET, a multigate device produced by Samsung, including a multi-bridge channel; he first active pattern AP1 may include a two-dimensional semiconductor material; the two-dimensional semiconductor material may include, for example, but is not necessarily limited to including, graphene, carbon nanotube, transition metal dichalcogenide (TMD) or combinations thereof. The transition metal dichalcogenide (TMD) may include, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and/or Pb, and S, Se and/or Te; see Par.[0056]-[0062] wherein The first source/drain contact 160 may include a first contact insertion film 162 and a first filling metal film 164 that are stacked sequentially on the upper surface of the substrate 100 (or the first etching blocking film 105) and the side surfaces of the first gate electrode 130). However, Park does not explicitly disclose that forming a metal nitride layer by reacting nitrogen to the metal layer.
Shen discloses, in Figs.1A-10, a method of manufacturing a semiconductor device, the method comprising: depositing a metal layer (95) on a gate electrode (42/100); forming a metal nitride layer (95) by reacting nitrogen to the metal layer (see Par.[0066], [0068], [0073] wherein the oxygen content of the oxide layer M2O.sub.n further away from the gate electrode layer 100 is lower than the oxygen content of the oxide layer M2O.sub.m because of the intervening oxygen absorbing layers 85 that react with the oxygen that is driven or diffused into the gate stack structure 75; a gate metal electrode layer 100 is subsequently formed over the second type WFM layer; see Par.[0071] wherein the first and second metal nitride layers are TiN and the TiN is formed by an ALD process by the following reaction: TiCl.sub.4+NH.sub.3.fwdarw.TiN.sub.(solid)+HCl.sub.(gas); the Ti atomic concentration in the TiN is varied by adjusting the ratio of the TiCl.sub.4 and NH.sub.3 reactants, the pressure of the reactant gases, the flowrate of the TiCl.sub.4 and NH.sub.3 reactants, and duration of time the TiCl.sub.4 and NH.sub.3 reactants are supplied to the deposition chamber); forming a gate insulating film (80) on the metal nitride layer (see Par.[0054]-[0056] wherein the gate stack 75 includes a gate dielectric layer 80 formed over the channel region 70 of the fin structure 20); forming a channel (70) on the gate insulating film (80) (see Par.[0087] wherein an oxygen absorbing layer 85 are formed over a channel region 70 of the semiconductor device); and forming a source electrode (32) and a drain electrode (34) on opposite sides of the channel (22) (see Par.[0025] wherein a gate dielectric layer 35 and a gate electrode 42; the fin 20 may be intrinsic and may appropriately be doped with an n-type impurity or a p-type impurity. In some embodiments, source and drain regions 32 and 34 are heavily doped and may contain impurities having a concentration in a range from about 5×10.sup.19 cm.sup.−3 to 1×10.sup.20 cm.sup.−3, while a channel region 22, e.g., a gate region, is undoped or lightly doped).
Park and Shen are analogous art because they are all directed to a transistor metal nitride, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Park to include Shen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the metal nitride formation by including nitrogen diffusion reacting with metal as taught by Shen in order to utilize known in the art advantages offered by diffusion method such as high-purity, uniform, and durable coatings with excellent adhesion, even on complex geometries thereby enhancing quality of overall device.
With respect to claim 12, Park discloses, in Figs.1-36, the method, wherein the metal nitride layer comprises transition metal and nitrogen (see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof).
With respect to claim 13, Park discloses, in Figs.1-36, the method, wherein the metal nitride layer comprises a material represented by M1N, where M1 is Mo, W, Nb, V, Ta, Ti, Zr, or Hf (see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof).
With respect to claim 16, Park discloses, in Figs.1-36, the method, wherein the channel comprises a material represented by M2X2, where M2 is Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, or Re, and X is S, Se, or Te (see Par.[0037]-[0038] wherein sheet patterns 112 and 114 may be used as channel regions of MBCFET, a multigate device produced by Samsung, including a multi-bridge channel; the first active pattern AP1 may include a two-dimensional semiconductor material; the two-dimensional semiconductor material may include, for example, but is not necessarily limited to including, graphene, carbon nanotube, transition metal dichalcogenide (TMD) or combinations thereof. The transition metal dichalcogenide (TMD) may include, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and/or Pb, and S, Se and/or Te).
With respect to claim 17, Park discloses, in Figs.1-36, the method, wherein the channel comprises MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, ZrS2, ZrSe2, HfS2, HfSe2, NbSe2, or ReSe2 (see Par.[0088], [0091] wherein second active pattern AP2, a second gate dielectric film 220, a second gate electrode 230, a second gate spacer 240, a second source/drain contact 260, and a second wiring structure WS2).
With respect to claim 18, Park discloses, in Figs.1-36, the method, wherein the metal nitride layer further comprises carbon (see Par.[0039]-[0041] wherein the first gate electrode 130 may include a conductive material, for example, but is not necessarily limited to including, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and/or a combination thereof).
With respect to claim 19, Park discloses, in Figs.1-36, the method, wherein the gate electrode is in direct contact with the metal nitride layer (see Fig.1-2).
With respect to claim 20, Park discloses, in Figs.1-36, the method, wherein the channel comprises one to ten layers of two-dimensional semiconductor material layers (see Par.[0037]-[0038] wherein sheet patterns 112 and 114 may be used as channel regions of MBCFET, a multigate device produced by Samsung, including a multi-bridge channel; he first active pattern AP1 may include a two-dimensional semiconductor material; the two-dimensional semiconductor material may include, for example, but is not necessarily limited to including, graphene, carbon nanotube, transition metal dichalcogenide (TMD) or combinations thereof. The transition metal dichalcogenide (TMD) may include, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and/or Pb, and S, Se and/or Te).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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