DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (US 2017/0352313), in view of Lan et al (US 2006/0119548; hereinafter Lan).
NOTE: while claims 23 and 24 are not currently rejected as being unpatentable over Miyake, in view of Lan, they have been included in the following rejection of claims 1 and 2 to show how Miyake and Lan teach the limitations common to claims 1 and 2.
• Regarding claims 1, 23, and 24, Miyake discloses a display device (figures 2, 15, and 16) comprising:
a pixel circuit (figure 6D); and
a light-emitting element connected between a second node of the pixel circuit and a common voltage line (element 710(ij) in figure 6D and ¶ 63),
wherein:
the pixel circuit includes a first transistor, connected to a driving voltage line and the second node (element M in figure 6D and ¶ 67),
the first transistor includes a gate electrode connected to a first node (note the relationship between elements M and SW1 in figure 6D and ¶ 67), and a counter gate electrode connected to an emission line (note the relationship between G2(i) and element M in figure 6D and ¶ 67),
the first transistor comprises an active layer formed of an oxide semiconductor (¶ 97), and
the counter gate electrode note the relationship between elements 512 and 516 in figure 12 and ¶s 132, 133, and 162),
the counter gate electrode being connected to the emission line (G2 in figures 4 and 6D and ¶ 89),
the counter gate electrode note the relationship between G2 and element M in figure 6D),
the emission signal on the emission line switches between an active level and a non-active level to turn the first transistor on and off, respectively (G2 in figure 4 and ¶ 89), and
the counter gate electrode note where the back gate electrode of element M in figure 6D is connected to only G2).
However, Miyake fails to disclose the additional details of the display device.
In the same field of endeavor, Lan discloses where:
the first transistor comprises an active layer formed of an oxide semiconductor (element 106 in figure 1 and ¶ 50), and
the counter gate electrode is formed in an opaque metallic shield made of chrome (Cr) or molybdenum (Mo) (¶ 124, in view of ¶ 105), and
the opaque metallic shield disposed beneath the active layer (¶s 103 and 124),
the opaque metallic shield both shielding the channel region of the first transistor and serving as the counter gate electrode (¶s 97, 98, 103, 105, and 124),
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Miyake according to the teachings of Lan, for the purpose of keeping radiation from radiation emitting pixels from reaching the channel regions of driving transistors (¶ 124).
• Regarding claim 2, Miyake, in view of Lan, discloses everything claimed, as applied to claim 1. Additionally, Miyake discloses where:
Claims 2, 23, & 24: the display device further comprises:
a second transistor connected to a data line and the first node (element SW1 in figure 6D and ¶ 66).
Claims 3-10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake, in view of Lan, and further in view of Yang et al (US 2019/0180688; hereinafter Yang).
NOTE: while claims 23 and 24 are not currently rejected as being unpatentable over Miyake, in view of Lan and Yang, they have been included in the following rejection of claims 3-10 and 13 to show how Miyake and Lan teach the limitations common to claims 3-10 and 13.
• Regarding claims 3-10 and 13, Miyake, in view of Lan, discloses everything claimed, as applied to claim 2. Additionally, Miyake discloses where:
Claims 4, 23, & 24: the display device further comprises:
a fourth transistor connected to the second node and an initialization voltage line (element SW2 in figure 6D and ¶ 104).
Claims 5, 23, & 24: the display device further comprises:
a first capacitor connected to the first node and the second node (element Cs in figure 6D and ¶s 66 and 67).
Claims 6 & 23: the display device further comprises:
a first gate line connected to a gate electrode of the second transistor (G1(i) in figure 6D);
a third gate line connected to a gate electrode of the fourth transistor (G3(i) in figure 6D).
Claims 7 & 23: the data line transmits a data voltage (¶s 66 and 70),
the emission line transmits an emission signal (¶ 89),
the first gate line transmits a first gate signal (¶ 66), and
the third gate line transmits a third gate signal (¶ 103).
However, Miyake, in view of Lan, fails to disclose the additional details of the display device.
In the same field of endeavor, Yang discloses where:
Claims 3, 23, & 24: the display device further comprises:
a third transistor (element T3 in figures 2 and 10 and ¶ 69) connected to a reference voltage line and the first node (note the relationship between N1, VR, and element T3 in figures 2 and 10).
Claims 5, 23, & 24: the display device further comprises:
a second capacitor (element C2 in figures 2 and 10 and ¶ 77) connected to the second node and the driving voltage line (note the relationship between ELVDD, N2, and element C2 in figures 2 and 10).
Claims 6 & 23: the display device further comprises:
a second gate line connected to a gate electrode of the third transistor (note the relationship between G2 and element T3 in figures 2 and 10); and
Claims 7 & 23: the second gate line transmits a second gate signal (¶ 119).
Claims 8 & 23: during a first initialization period,
each of the second and third gate signals is at an active level (G2 and G3 during P1 in figures 3 and 11 and ¶ 82), and
each of the first gate signal and the emission signal is at a non-active level (G1 during P1 in figure 3 and ¶ 82).
Claims 9 & 23: during a threshold voltage detection period that follows the first initialization period,
each of the second gate signal and the emission signal is at the active level (G2 and G4 during P2 in figure 11), and
each of the first and third gate signals is at the non-active level (G1 and G3 during P2 in figure 11).
Claims 10 & 23: during a data write period that follows the threshold voltage detection period,
the first gate signal is at the active level (G1 during P3 in figure 11),
each of the second gate signal, the third gate signal, the emission signal is at the non-active level (G2-G4 during P3 in figure 11), and
the data voltage is applied to the data line (¶ 122).
Claim 13: when the emission signal is at the non-active level, the emission signal has a same value as or a smaller value than the first gate signal when the first gate signal is at the non-active level (G1 in figures 2 and 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Miyake, as modified by Lan, according to the teachings of Yang, for the purpose of improving image quality (¶s 4-7).
Claims 11, 12, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake, in view of Lan and Yang, and further in view of Park et al (US 2017/0124954; hereinafter Park).
• Regarding claims 11, 12, and 23, Miyake, in view of Lan, discloses everything claimed, as applied to claim 10. However, Miyake, in view of Lan, fails to disclose the additional details of the display device.
In the same field of endeavor, Yang discloses where:
Claims 12 & 23: during an emission period that follows the second initialization period,
the emission signal is at the active level (G4 during P4 in figure 11), and
each of the first, second, and third gate signals is at the non-active level (G1-G3 during P4 in figure 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Miyake, as modified by Lan, according to the teachings of Yang, for the purpose of improving image quality (¶s 4-7). However, Yang also fails to disclose the additional details of the display device.
In the same field of endeavor, Park discloses where:
Claims 11 & 23: during a second initialization period that follows the data write period,
the third gate signal is at the active level (GI during TINIT2 in figure 21 and ¶s 158-160), and
each of the first gate signal, the second gate signal, and the emission signal is at the non-active level (GC and SCAN during TINIT2 in figure 21 and ¶s 158-160; where TEMI following TINIT2 at least suggests that “the emission signal is at the non-active level”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Miyake, as modified by Lan and Yang, according to the teachings of Park, for the purpose of improving the luminance uniformity of pixels in a display (¶ 160).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Miyake, in view of Lan and Yang, and further in view of Kim (US 2009/0309503).
• Regarding claim 14, Miyake, in view of Lan and Yang, discloses everything claimed, as applied to claim 5. However, Miyake, in view of Lan and Yang, fails to disclose the additional details of the display device.
In the same field of endeavor, Kim discloses where a capacitance of the second capacitor is greater than a capacitance of the first capacitor (¶ 42).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Miyake, as modified by Lan and Yang, according to the teachings of Kim, for the purpose of stably maintaining the voltage of a node connected to a driving transistor (¶ 42).
Claims 15-22 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (US 2017/0352313), in view of Lan and Yang, and further in view of Son et al (US 2023/0029234; hereinafter Son).
• Regarding claims 15-22 and 24, Miyake, in view of Lan, discloses everything claimed, as applied to claim 5. Additionally, Miyake discloses where:
Claims 15 & 24: the display device further comprises:
the fourth transistor is connected to the anode of the light-emitting element and the initialization volage line (note the relationship between VR and elements 710(ij) and SW2 in figure 6D).
Claims 16 & 24: the display device further comprises:
a first gate line connected to a gate electrode of the second transistor (G1(i) in figure 6D); and
a third gate line connected to a gate electrode of the fourth transistor (G3(i) in figure 6D).
Claims 17 & 24: the data line transmits a data voltage (¶s 66 and 70),
the emission line transmits an emission signal (¶ 89),
the first gate line transmits a first gate signal (¶ 66),
the third gate line transmits a third gate signal (¶ 103).
However, Miyake, in view of Lan, fails to disclose the additional details of the display device.
In the same field of endeavor, Yang discloses where:
Claims 16 & 24: the display device further comprises:
a second gate line connected to a gate electrode of the third transistor (note the relationship between G2 and element T3 in figures 2 and 10).
Claims 17 & 24: the second gate line transmits a second gate signal (¶ 119).
Claims 18 & 24: during a first initialization period,
each of the second and third gate signals is at the active level (G2 and G3 during P1 in figures 3 and 11 and ¶ 82),and
each of the first gate signal and the emission signal is at the non-active level (G1 during P1 in figure 3 and ¶ 82).
Claims 19 & 24: during a threshold voltage detection period that follows the first initialization period,
each of the second gate signal and the emission signal is at the active level (G2 and G4 during P2 in figure 11), and
each of the first and third gate signals is at the non-active level (G1 and G3 during P2 in figure 11).
Claims 20 & 24: during a data write period that follows the threshold voltage detection period,
the first gate signal is at the active level (G1 during P3 in figure 11),
each of the second gate signal, the third gate signal, and the emission signal is at the non-active level (G2-G4 during P3 in figure 11), and
the data voltage is applied to the data line (¶ 122).
Claims 22 & 24: during an emission period that follows the second initialization period,
the emission signal is at the active level (G4 during P4 in figure 11), and
each of the first, second, and third gate signals is at the non-active level (G1-G3 during P4 in figure 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Miyake, as modified by Lan, according to the teachings of Yang, for the purpose of improving image quality (¶s 4-7). However, Yang also fails to disclose the additional details of the display device.
In the same field of endeavor, Son discloses where:
Claims 15 & 24: the display device further comprises:
a fifth transistor connected to the second node and an anode of the light-emitting element (element M54 in figure 20 and ¶ 209).
Claims 16 & 24: the display device further comprises:
a fourth gate line connected to a gate electrode of the fifth transistor (EM1 in figure 20 and ¶ 189).
Claims 17 & 24: the fourth gate line transmits a fourth gate signal (¶ 189).
Claims 18 & 24: during a first initialization period,
the fourth gate signal is at the active level (EM1 during period Ti in figure 21 and ¶ 189).
Claims 19 & 24: during a threshold voltage detection period that follows the first initialization period,
the fourth gate signal is at the non-active level (EM1 during period Ts in figure 21 and ¶s 190 and 191).
Claims 20 & 24: during a data write period that follows the threshold voltage detection period,
the fourth gate signal is at the non-active level (EM1 during period Tw in figure 21 and ¶s 192-194).
Claims 21 & 24: during a second initialization period that follows the data write period,
the third gate signal is at the active level (SENSE during period AR in figure 21 and ¶ 195), and
the fourth gate signal is at the active level (EM1 during period AR in figure 21 and ¶ 195), and
each of the first gate signal, the second gate signal, and the emission signal is at the non-active level (SCAN, INIT, and EM2 in period AR in figure 21 and ¶ 195).
Claims 22 & 24: during an emission period that follows the second initialization period,
the fourth gate signal is at the active level (EM1 during period Tem in figure 21 and ¶ 197).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Miyake, as modified by Lan and Yang, according to the teachings of Son, for the purpose of preventing flicker from being visually recognized by a user in the low-speed display driving mode (¶ 188).
Response to Arguments
Applicant’s arguments with respect to claims 1, 23, and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Closing Remarks/Comments
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622