Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: P202301180US01
Filling Date: 08/21/24
Applicant: Niskayuna et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 2023/0386929 A1) in view of Ando et al (US 2020/0365584 A1).
Regarding claim 1, Zhang discloses a semiconductor device (Fig. 10) comprising: a substrate 100 (Para. 17); a plurality of nanosheets 102 (Paras. 18, 3) located parallel to the substrate 100; a first dielectric bar 104 (Para. 18) extending upwards from the substrate 100 through the plurality of nanosheets 102, wherein the plurality of nanosheets 102 extend laterally from sidewalls of the first dielectric bar 104; a high-k dielectric metal (gate insulating layer, Para. 30, layer between 212 and 102) on a frontside surface and a backside surface of each nanosheet 102 in the plurality of nanosheets 102 and on the sidewalls of the first dielectric bar 104; a work function metal (Para. 30, consider the same shape with the gate dielectric layer, common in the art, WF material works as a barrier. So, it has to be all around the gate insulating layer in Fig. 10, layer between 212 and 102) on a frontside surface, a backside surface, and sidewalls of the high-k dielectric metal; and a conductive metal fill 212 (Para. 30) between one or more portions of the work function metal (Para. 30), wherein the conductive metal fill 212 connects (claim does not specify direct contact) to a sidewall of the work function metal (Para. 30).
Zhang does not explicitly disclose a high-k dielectric metal on a frontside surface and a backside surface of each nanosheet in the plurality of nanosheets and on the sidewalls of the first dielectric bar; a work function metal on a frontside surface, a backside surface, and sidewalls of the high-k dielectric metal.
However, Ando discloses a high-k dielectric metal 15B (Fig. 8, Para. 43) on a frontside surface and a backside surface of each nanosheet 13 (Para. 29) in the plurality of nanosheets 13 and on the sidewalls of the first dielectric bar 17 (Para. 49); a work function metal 16 (Para. 45) on a frontside surface, a backside surface, and sidewalls of the high-k dielectric metal 15B.
Ando teaches the above modification is used to improve electrical performance of the device (Para. 2). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute dielectric metal with Ando
high-k dielectric metal as suggested above to improve electrical performance of the device (Para. 2).
Regarding claim 2, Ando discloses the semiconductor device of claim 1, wherein the work function metal 16 is comprised of a titanium alloy (Para. 45).
Regarding claim 3, Zhang discloses the semiconductor device of claim 1, wherein the conductive metal fill 212 is comprised of W (Para. 30), TaN, Ru, Al, and TiAlC.
Regarding claim 4, Zhang discloses the semiconductor device of claim 1, further comprising: a second dielectric bar 213 (Para. 47) parallel to the plurality of nanosheets 102.
Regarding claim 5, Zhang discloses the semiconductor device of claim 4, wherein the high-k dielectric metal (Para. 30, spiral layer between 102 and 212) is continuous from a sidewall of the second dielectric bar 213 that is connected to a frontside surface of an STI region 105 (Para. 17).
Regarding claim 6, Zhang discloses the semiconductor device of claim 5, wherein the work function metal (Para. 30, common in the art) is continuous and in contact with the high-k dielectric metal (Para. 30, spiral layer between 102 and 212).
Regarding claim 7, Zhang discloses the semiconductor device of claim 1, further comprising: a dielectric fill 204 (Para. 34) connected to a sidewall of the conductive metal fill 212.
Regarding claim 15, Zhang discloses a semiconductor device (Figs. 9-10) comprising: a substrate 100; a plurality of nanosheets 102 located parallel to the substrate 100; a first dielectric bar 104 extending upwards from the substrate 100 through the plurality of nanosheets 102, wherein the plurality of nanosheets 102 extend laterally from sidewalls of the first dielectric bar 104; a high-k dielectric metal (gate insulating layer, Para. 30, layer between 212 and 102) on a frontside surface and a backside surface of each nanosheet in the plurality of nanosheets 102 and on the sidewalls of the first dielectric bar 104; a work function metal (Para. 30, consider the same shape with the gate dielectric layer, common in the art, WF material works as a barrier. So, it has to be all around the gate insulating layer in Fig. 10, layer between 212 and 102) on a frontside surface, a backside surface, and exposed sidewalls of the high-k dielectric metal; a conductive metal fill 212 between the work function metal (same spiral shape as gate dielectric), wherein the conductive metal 212 connects to a sidewall of the work function metal (Para. 30); a gate contact 210 (Para. 41, bottom portion) on a frontside surface of the first dielectric bar 104; and a via 210 (top portion) connected to the frontside surface of the gate contact 210.
Zhang does not explicitly disclose a high-k dielectric metal on a frontside surface and a backside surface of each nanosheet in the plurality of nanosheets and on the sidewalls of the first dielectric bar; a work function metal on a frontside surface, a backside surface, and sidewalls of the high-k dielectric metal.
However, Ando discloses a high-k dielectric metal 15B (Fig. 8, Para. 43) on a frontside surface and a backside surface of each nanosheet 13 (Para. 29) in the plurality of nanosheets 13 and on the sidewalls of the first dielectric bar 17 (Para. 49); a work function metal 16 (Para. 45) on a frontside surface, a backside surface, and sidewalls of the high-k dielectric metal 15B.
Ando teaches the above modification is used to improve electrical performance of the device (Para. 2). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute dielectric metal with Ando
high-k dielectric metal as suggested above to improve electrical performance of the device (Para. 2).
Regarding claim 16, Ando discloses the semiconductor device of claim 15, wherein the work function metal 16 is comprised of a titanium alloy (Para. 45).
Regarding claim 17, Zhang discloses the semiconductor device of claim 15, wherein the conductive metal fill 212 is comprised of W (Para. 30), TaN, Ru, Al, and TiAlC.
Regarding claim 18, Zhang discloses the semiconductor device of claim 15, further comprising: a second dielectric bar 213 parallel to the plurality of nanosheets 102.
Regarding claim 19, Zhang discloses the semiconductor device of claim 18, wherein the high-k dielectric metal (Para. 30) is continuous from a sidewall of the second dielectric bar 213 that is connected to a frontside surface of an STI region 105.
Regarding claim 20, Zhang discloses the semiconductor device of claim 19, wherein the work function metal (Para. 30, common in the art) is continuous and in contact with the high-k dielectric metal.
Allowable Subject Matter
Claims 8-13 and 14 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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